FPGA prototyping by VHDL examples: Xilinx Spartan-3 version
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| Format: | Book |
| Language: | English |
| Published: |
Hoboken, NJ
Wiley-Interscience
2008
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| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Physical Description: | XXV, 440 S. Ill., graph. Darst. |
| ISBN: | 0470185317 9780470185315 |
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MARC
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| 084 | |a ZN 4940 |0 (DE-625)157423: |2 rvk | ||
| 084 | |a ELT 453f |2 stub | ||
| 100 | 1 | |a Chu, Pong P. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a FPGA prototyping by VHDL examples |b Xilinx Spartan-3 version |c Pong P. Chu |
| 264 | 1 | |a Hoboken, NJ |b Wiley-Interscience |c 2008 | |
| 300 | |a XXV, 440 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 0 | |a Field programmable gate arrays / Design and construction | |
| 650 | 0 | |a Prototypes, Engineering | |
| 650 | 0 | |a VHDL (Computer hardware description language) | |
| 650 | 4 | |a Field programmable gate arrays |x Design and construction | |
| 650 | 4 | |a Prototypes, Engineering | |
| 650 | 4 | |a VHDL (Computer hardware description language) | |
| 650 | 0 | 7 | |a Field programmable gate array |0 (DE-588)4347749-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VHDL |0 (DE-588)4254792-1 |2 gnd |9 rswk-swf |
| 655 | 7 | |0 (DE-588)4173536-5 |a Patentschrift |2 gnd-content | |
| 689 | 0 | 0 | |a Field programmable gate array |0 (DE-588)4347749-5 |D s |
| 689 | 0 | 1 | |a VHDL |0 (DE-588)4254792-1 |D s |
| 689 | 0 | |5 DE-604 | |
| 856 | 4 | 2 | |m GBV Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016274175&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-016274175 | |
Record in the Search Index
| _version_ | 1809403557849333760 |
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| adam_text |
FPGA PROTOTYPING BY VHDL EXAMPLES XILINX SPARTAN*-3 VERSION PONG P. CHU
CLEVELAND STATE UNIVERSITY WILEY- INTERSCIENCE A JOHN WILEY & SONS,
INC., PUBLICATION CONTENTS PREFACE XIX ACKNOWLEDGMENTS XXV PART I BASIC
DIGITAL CIRCUITS 1 GATE-LEVEL COMBINATIONAL CIRCUIT 1 1.1 INTRODUCTION 1
1.2 GENERAL DESCRIPTION 2 1.2.1 BASIC LEXICAL RULES 2 1.2.2 LIBRARY AND
PACKAGE 3 1.2.3 ENTITY DECLARATION 3 1.2.4 DATA TYPE AND OPERATORS 3
1.2.5 ARCHITECTURE BODY 4 1.2.6 CODE OF A 2-BIT COMPARATOR 5 1.3
STRUCTURAL DESCRIPTION 6 1.4 TESTBENCH 8 1.5 BIBLIOGRAPHIC NOTES 9 1.6
SUGGESTED EXPERIMENTS 10 1.6.1 CODE FOR GATE-LEVEL GREATER-THAN CIRCUIT
10 1.6.2 CODE FOR GATE-LEVEL BINARY DECODER 10 2 OVERVIEW OF FPGA AND
EDA SOFTWARE 11 VII VIII CONTENTS 2.1 INTRODUCTION 11 2.2 FPGA 11 2.2.1
OVERVIEW OF A GENERAL FPGA DEVICE 11 2.2.2 OVERVIEW OF THE XILINX
SPARTAN-3 DEVICES 13 2.3 OVERVIEW OF THE DIGILENT S3 BOARD 13 2.4
DEVELOPMENT FLOW 15 2.5 OVERVIEW OF THE XILINX ISE PROJECT NAVIGATOR 17
2.6 SHORT TUTORIAL ON ISE PROJECT NAVIGATOR 19 2.6.1 CREATE THE DESIGN
PROJECT AND HDL CODES 21 2.6.2 CREATE A TESTBENCH AND PERFORM THE RTL
SIMULATION 22 2.6.3 ADD A CONSTRAINT FILE AND SYNTHESIZE AND IMPLEMENT
THE CODE 22 2.6.4 GENERATE AND DOWNLOAD THE CONFIGURATION FILE TO AN
FPGA DEVICE 24 2.7 SHORT TUTORIAL ON THE MODELSIM HDL SIMULATOR 27 2.8
BIBLIOGRAPHIC NOTES 32 2.9 SUGGESTED EXPERIMENTS 33 2.9.1 GATE-LEVEL
GREATER-THAN CIRCUIT 33 2.9.2 GATE-LEVEL BINARY DECODER 33 3 RT-LEVEL
COMBINATIONAL CIRCUIT 35 3.1 INTRODUCTION 35 3.2 RT-LEVEL COMPONENTS 35
3.2.1 RELATIONAL OPERATORS 37 3.2.2 ARITHMETIC OPERATORS 37 3.2.3 OTHER
SYNTHESIS-RELATED VHDL CONSTRUCTS 38 3.2.4 SUMMARY 40 3.3 ROUTING
CIRCUIT WITH CONCURRENT ASSIGNMENT STATEMENTS 41 3.3.1 CONDITIONAL
SIGNAL ASSIGNMENT STATEMENT 41 3.3.2 SELECTED SIGNAL ASSIGNMENT
STATEMENT 44 3.4 MODELING WITH A PROCESS 46 3.4.1 PROCESS 46 3.4.2
SEQUENTIAL SIGNAL ASSIGNMENT STATEMENT 46 3.5 ROUTING CIRCUIT WITH IF
AND CASE STATEMENTS 47 3.5.1 IF STATEMENT 47 3.5.2 CASE STATEMENT 49
3.5.3 COMPARISON TO CONCURRENT STATEMENTS 50 3.5.4 UNINTENDED MEMORY 52
3.6 CONSTANTS AND GENERICS 53 3.6.1 CONSTANTS 53 3.6.2 GENERICS 54 3.7
DESIGN EXAMPLES 56 3.7.1 HEXADECIMAL DIGIT TO SEVEN-SEGMENT LED DECODER
56 3.7.2 SIGN-MAGNITUDE ADDER 59 CONTENTS IX 3.7.3 BARREL SHIFTER 62
3.7.4 SIMPLIFIED FLOATING-POINT ADDER 63 69 69 69 69 69 70 70 70 71 71
71 72 73 74 74 77 78 79 79 79 81 84 88 88 96 100 104 105 105 105 105 106
106 106 106 5 FSM 107 5.1 INTRODUCTION 107 3.8 3.9 BIBLIOGRAPHIC NOTES
SUGGESTED EXPERIMENTS 3.9.1 3.9.2 3.9.3 3.9.4 3.9.5 3.9.6 MULTI-FUNCTION
BARREL SHIFTER DUAL-PRIORITY ENCODER BCD INCREMENTOR FLOATING-POINT
GREATER-THAN CIRCUIT FLOATING-POINT AND SIGNED INTEGER CONVERSION
CIRCUIT ENHANCED FLOATING-POINT ADDER REGULAR SEQUENTIAL CIRCUIT 4.1 4.2
4.3 4.4 4.5 4.6 4.7 INTRODUCTION 4.1.1 4.1.2 4.1.3 D FF AND REGISTER
SYNCHRONOUS SYSTEM CODE DEVELOPMENT HDL CODE OF THE FF AND REGISTER
4.2.1 4.2.2 4.2.3 4.2.4 SIMP! 4.3.1 4.3.2 DFF REGISTER REGISTER FILE
STORAGE COMPONENTS IN A SPARTAN-3 DEV\CE XLHNX S P ECI F TC E DESIGN
EXAMPLES SHIFT REGISTER BINARY COUNTER AND VARIANT TESTBENCH FOR
SEQUENTIAL CIRCUITS CASE J 4.5.1 4.5.2 4.5.3 BIBLIO TUDY LED
TIME-MULTIPLEXING CIRCUIT STOPWATCH FIFO BUFFER GRAPHIC NOTES SUGGESTED
EXPERIMENTS 4.7.1 4.7.2 4.7.3 4.7.4 4.7.5 4.7.6 4.7.7 PROGRAMMABLE
SQUARE WAVE GENERATOR PWM AND LED DIMMER ROTATING SQUARE CIRCUIT
HEARTBEAT CIRCUIT ROTATING LED BANNER CIRCUIT ENHANCED STOPWATCH STACK X
CONTENTS 5.1.1 MEALY AND MOORE OUTPUTS 107 5.1.2 FSM REPRESENTATION 108
5.2 FSM CODE DEVELOPMENT 111 5.3 DESIGN EXAMPLES 114 5.3.1 RISING-EDGE
DETECTOR 114 5.3.2 DEBOUNCING CIRCUIT 118 5.3.3 TESTING CIRCUIT 122 5.4
BIBLIOGRAPHIC NOTES 124 5.5 SUGGESTED EXPERIMENTS 124 5.5.1 DUAL-EDGE
DETECTOR 124 5.5.2 ALTERNATIVE DEBOUNCING CIRCUIT 124 5.5.3 PARKING LOT
OCCUPANCY COUNTER 125 6 FSMD 127 6.1 INTRODUCTION 127 6.1.1 SINGLE RT
OPERATION 127 6.1.2 ASMD CHART 128 6.1.3 DECISION BOX WITH A REGISTER
129 6.2 CODE DEVELOPMENT OF AN FSMD 131 6.2.1 DEBOUNCING CIRCUIT BASED
ON RT METHODOLOGY 132 6.2.2 CODE WITH EXPLICIT DATA PATH COMPONENTS 134
6.2.3 CODE WITH IMPLICIT DATA PATH COMPONENTS 136 6.2.4 COMPARISON 137
6.2.5 TESTING CIRCUIT 138 6.3 DESIGN EXAMPLES 140 6.3.1 FIBONACCI NUMBER
CIRCUIT 140 6.3.2 DIVISION CIRCUIT 143 6.3.3 BINARY-TO-BCD CONVERSION
CIRCUIT 147 6.3.4 PERIOD COUNTER 150 6.3.5 ACCURATE LOW-FREQUENCY
COUNTER 153 6.4 BIBLIOGRAPHIC NOTES 156 6.5 SUGGESTED EXPERIMENTS 157
6.5.1 ALTERNATIVE DEBOUNCING CIRCUIT 157 6.5.2 BCD-TO-BINARY CONVERSION
CIRCUIT 157 6.5.3 FIBONACCI CIRCUIT WITH BCD I/O: DESIGN APPROACH 1 157
6.5.4 FIBONACCI CIRCUIT WITH BCD I/O: DESIGN APPROACH 2 157 6.5.5
AUTO-SCALED LOW-FREQUENCY COUNTER 158 6.5.6 REACTION TIMER 158 6.5.7
BABBAGE DIFFERENCE ENGINE EMULATION CIRCUIT 159 PART II I/O MODULES
CONTENTS XI 7 UART 163 7.1 INTRODUCTION 163 7.2 UART RECEIVING SUBSYSTEM
164 7.2.1 OVERSAMPLING PROCEDURE 164 7.2.2 BAUD RATE GENERATOR 165 7.2.3
UART RECEIVER 165 7.2.4 INTERFACE CIRCUIT 168 7.3 UART TRANSMITTING
SUBSYSTEM 171 7.4 OVERALL UART SYSTEM 174 7.4.1 COMPLETE UART CORE 174
7.4.2 UART VERIFICATION CONFIGURATION 176 7.5 CUSTOMIZING A UART 178 7.6
BIBLIOGRAPHIC NOTES 180 7.7 SUGGESTED EXPERIMENTS 180 7.7.1
FULL-FEATURED UART 180 7.7.2 UART WITH AN AUTOMATIC BAUD RATE DETECTION
CIRCUIT 181 7.7.3 UART WITH AN AUTOMATIC BAUD RATE AND PARITY DETECTION
CIRCUIT 181 7.7.4 UART-CONTROLLED STOPWATCH 181 7.7.5 UART-CONTROLLED
ROTATING LED BANNER 182 8 PS2 KEYBOARD 183 8.1 INTRODUCTION 183 8.2 PS2
RECEIVING SUBSYSTEM 184 8.2.1 PHYSICAL INTERFACE OF A PS2 PORT 184 8.2.2
DEVICE-TO-HOST COMMUNICATION PROTOCOL 184 8.2.3 DESIGN AND CODE 184 8.3
PS2 KEYBOARD SCAN CODE 188 8.3.1 OVERVIEW OF THE SCAN CODE 188 8.3.2
SCAN CODE MONITOR CIRCUIT 189 8.4 PS2 KEYBOARD INTERFACE CIRCUIT 191
8.4.1 BASIC DESIGN AND HDL CODE 192 8.4.2 VERIFICATION CIRCUIT 194 8.5
BIBLIOGRAPHIC NOTES 196 8.6 SUGGESTED EXPERIMENTS 196 8.6.1 ALTERNATIVE
KEYBOARD INTERFACE I 196 8.6.2 ALTERNATIVE KEYBOARD INTERFACE II 196
8.6.3 PS2 RECEIVING SUBSYSTEM WITH WATCHDOG TIMER 197 8.6.4
KEYBOARD-CONTROLLED STOPWATCH 197 8.6.5 KEYBOARD-CONTROLLED ROTATING LED
BANNER 197 9 PS2 MOUSE 199 XII CONTENTS 9.1 INTRODUCTION 199 9.2 PS2
MOUSE PROTOCOL 200 9.2.1 BASIC OPERATION 200 9.2.2 BASIC INITIALIZATION
PROCEDURE 200 9.3 PS2 TRANSMITTING SUBSYSTEM 201 9.3.1
HOST-TO-PS2-DEVICE COMMUNICATION PROTOCOL 201 9.3.2 DESIGN AND CODE 202
9.4 BIDIRECTIONAL PS2 INTERFACE 206 9.4.1 BASIC DESIGN AND CODE 206
9.4.2 VERIFICATION CIRCUIT 208 9.5 PS2 MOUSE INTERFACE 210 9.5.1 BASIC
DESIGN 210 9.5.2 TESTING CIRCUIT 212 9.6 BIBLIOGRAPHIC NOTES 214 9.7
SUGGESTED EXPERIMENTS 214 9.7.1 KEYBOARD CONTROL CIRCUIT 214 9.7.2
ENHANCED MOUSE INTERFACE 214 9.7.3 MOUSE-CONTROLLED SEVEN-SEGMENT LED
DISPLAY 214 10 EXTERNAL SRAM 215 10.1 INTRODUCTION 215 10.2
SPECIFICATION OF THE IS61LV25616AL SRAM 216 10.2.1 BLOCK DIAGRAM AND I/O
SIGNALS 216 10.2.2 TIMING PARAMETERS 216 10.3 BASIC MEMORY CONTROLLER
220 10.3.1 BLOCK DIAGRAM 220 10.3.2 TIMING REQUIREMENT 221 10.3.3
REGISTER FILE VERSUS SRAM 222 10.4 A SAFE DESIGN 222 10.4.1 ASMD CHART
222 10.4.2 TIMING ANALYSIS 223 10.4.3 HDL IMPLEMENTATION 224 10.4.4
BASIC TESTING CIRCUIT 226 10.4.5 COMPREHENSIVE SRAM TESTING CIRCUIT 228
10.5 MORE AGGRESSIVE DESIGN 233 10.5.1 TIMING ISSUES 233 10.5.2
ALTERNATIVE DESIGN I 234 10.5.3 ALTERNATIVE DESIGN II 236 10.5.4
ALTERNATIVE DESIGN 111 237 *.5.5 \TOANCEDFPGMEATOES XIUNXSPECI F IC 1*
10.6 BIBLIOGRAPHIC NOTES 240 10.7 SUGGESTED EXPERIMENTS 240 CONTENTS
XIII 10.7.1 MEMORY WITH A 512K-BY-16 CONFIGURATION 240 10.7.2 MEMORY
WITH A LM-BY-8 CONFIGURATION 240 10.7.3 MEMORY WITH AN 8M-BY-L
CONFIGURATION 240 10.7.4 EXPANDED MEMORY TESTING CIRCUIT 241 10.7.5
MEMORY CONTROLLER AND TESTING CIRCUIT FOR ALTERNATIVE DESIGN I 241
10.7.6 MEMORY CONTROLLER AND TESTING CIRCUIT FOR ALTERNATIVE DESIGN II
241 10.7.7 MEMORY CONTROLLER AND TESTING CIRCUIT FOR ALTERNATIVE DESIGN
III 241 10.7.8 MEMORY CONTROLLER WITH DCM 241 10.7.9 HIGH-PERFORMANCE
MEMORY CONTROLLER 241 11 XILINX SPARTAN-3 SPECIFIC MEMORY 243 11.1
INTRODUCTION 243 11.2 EMBEDDED MEMORY OF SPARTAN-3 DEVICE 243 11.2.1
OVERVIEW 243 11.2.2 COMPARISON 244 11.3 METHOD TO INCORPORATE MEMORY
MODULES 244 11.3.1 MEMORY MODULE VIA HDL COMPONENT INSTANTIATION 245
11.3.2 MEMORY MODULE VIA CORE GENERATOR 245 11.3.3 MEMORY MODULE VIA HDL
INFERENCE 246 11.4 HDL TEMPLATES FOR MEMORY INFERENCE 246 11.4.1
SINGLE-PORT RAM 246 11.4.2 DUAL-PORT RAM 249 11.4.3 ROM 251 11.5
BIBLIOGRAPHIC NOTES 254 11.6 SUGGESTED EXPERIMENTS 254 11.6.1
BLOCK-RAM-BASED FIFO 254 11.6.2 BLOCK-RAM-BASED STACK 254 11.6.3
ROM-BASED SIGN-MAGNITUDE ADDER 255 11.6.4 ROM BASED SIN(X) FUNCTION 255
11.6.5 ROM-BASED SIN (*) AND COS(:R) FUNCTIONS 255 12 VGA CONTROLLER I:
GRAPHIC 257 12.1 INTRODUCTION 257 12.1.1 BASIC OPERATION OF A CRT 257
12.1.2 VGA PORT OF THE S3 BOARD 259 12.1.3 VIDEO CONTROLLER 259 12.2 VGA
SYNCHRONIZATION 260 12.2.1 HORIZONTAL SYNCHRONIZATION 260 12.2.2
VERTICAL SYNCHRONIZATION 262 12.2.3 TIMING CALCULATION OF VGA
SYNCHRONIZATION SIGNALS 263 12.2.4 HDL IMPLEMENTATION 263 XJV CONTENTS
12.2.5 TESTING CIRCUIT 266 12.3 OVERVIEW OF THE PIXEL GENERATION CIRCUIT
267 12.4 GRAPHIC GENERATION WITH AN OBJECT-MAPPED SCHEME 268 12.4.1
RECTANGULAR OBJECTS 269 12.4.2 NON-RECTANGULAR OBJECT 273 12.4.3
ANIMATED OBJECT 275 12.5 GRAPHIC GENERATION WITH A BIT-MAPPED SCHEME 282
12.5.1 DUAL-PORT RAM IMPLEMENTATION 282 12.5.2 SINGLE-PORT RAM
IMPLEMENTATION 287 12.6 BIBLIOGRAPHIC NOTES 287 12.7 SUGGESTED
EXPERIMENTS 287 12.7.1 VGA TEST PATTERN GENERATOR 287 12.7.2 SVGA MODE
SYNCHRONIZATION CIRCUIT 288 12.7.3 VISIBLE SCREEN ADJUSTMENT CIRCUIT 288
12.7.4 BALL-IN-A-BOX CIRCUIT 288 12.7.5 TWO-BALLS-IN-A-BOX CIRCUIT 289
12.7.6 TWO-PLAYER PONG GAME 289 12.7.7 BREAKOUT GAME 289 12.7.8
FULL-SCREEN DOT TRACE 289 12.7.9 MOUSE POINTER CIRCUIT 290 12.7.10
SMALL-SCREEN MOUSE SCRIBBLE CIRCUIT 290 12.7.11 FULL-SCREEN MOUSE
SCRIBBLE CIRCUIT 290 13 VGA CONTROLLER II: TEXT 291 13.1 INTRODUCTION
291 13.2 TEXT GENERATION 291 13.2.1 CHARACTER AS A TILE 291 13.2.2 FONT
ROM 292 13.2.3 BASIC TEXT GENERATION CIRCUIT 294 13.2.4 FONT DISPLAY
CIRCUIT 295 13.2.5 FONT SCALING 297 13.3 FULL-SCREEN TEXT DISPLAY 298
13.4 THE COMPLETE PONG GAME 302 13.4.1 TEXT SUBSYSTEM 302 13.4.2
MODIFIED GRAPHIC SUBSYSTEM 309 13.4.3 AUXILIARY COUNTERS 310 13.4.4
TOP-LEVEL SYSTEM 312 13.5 BIBLIOGRAPHIC NOTES 317 13.6 SUGGESTED
EXPERIMENTS 317 13.6.1 ROTATING BANNER 317 13.6.2 UNDERLINE FOR THE
CURSOR 317 13.6.3 DUAL-MODE TEXT DISPLAY 317 CONTENTS XV 13.6.4 KEYBOARD
TEXT ENTRY 317 13.6.5 UART TERMINAL 317 13.6.6 SQUARE WAVE DISPLAY 318
13.6.7 SIMPLE FOUR-TRACE LOGIC ANALYZER 318 13.6.8 COMPLETE TWO-PLAYER
PONG GAME 319 13.6.9 COMPLETE BREAKOUT GAME 319 PART III PICOBLAZE
MICROCONTROLLER* 77 7JVY SPECIFIC 14 PICOBLAZE OVERVIEW 323 14.1
INTRODUCTION 323 14.2 CUSTOMIZED HARDWARE AND CUSTOMIZED SOFTWARE 324
14.2.1 FROM SPECIAL-PURPOSE FSMD TO GENERAL-PURPOSE MICROCONTROLLER 324
14.2.2 APPLICATION OF MICROCONTROLLER 326 14.3 OVERVIEW OF PICOBLAZE 326
14.3.1 BASIC ORGANIZATION 326 14.3.2 TOP-LEVEL HDL MODULES 328 14.4
DEVELOPMENT FLOW 329 14.5 INSTRUCTION SET 329 14.5.1 PROGRAMMING MODEL
331 14.5.2 INSTRUCTION FORMAT 332 14.5.3 LOGICAL INSTRUCTIONS 332 14.5.4
ARITHMETIC INSTRUCTIONS 333 14.5.5 COMPARE AND TEST INSTRUCTIONS 334
14.5.6 SHIFT AND ROTATE INSTRUCTIONS 335 14.5.7 DATA MOVEMENT
INSTRUCTIONS 336 14.5.8 PROGRAM FLOW CONTROL INSTRUCTIONS 338 14.5.9
INTERRUPT RELATED INSTRUCTIONS 341 14.6 ASSEMBLER DIRECTIVES 342 14.6.1
THE KCPSM3 DIRECTIVES 342 14.6.2 THE PBLAZELDE DIRECTIVES 342 14.7
BIBLIOGRAPHIC NOTES 343 15 PICOBLAZE ASSEMBLY CODE DEVELOPMENT 345 15.1
INTRODUCTION 345 15.2 USEFUL CODE SEGMENTS 345 15.2.1 KCPSM3 CONVENTIONS
345 15.2.2 BIT MANIPULATION 346 15.2.3 MULTIPLE-BYTE MANIPULATION 347
15.2.4 CONTROL STRUCTURE 348 15.3 SUBROUTINE DEVELOPMENT 350 15.4
PROGRAM DEVELOPMENT 351 XVI CONTENTS 15.4.1 DEMONSTRATION EXAMPLE 352
15.4.2 PROGRAM DOCUMENTATION 356 15.5 PROCESSING OF THE ASSEMBLY CODE
358 15.5.1 COMPILING WITH KCSPM3 358 15.5.2 SIMULATION BY PBLAZELDE 359
15.5.3 RELOADING CODE VIA THE JTAG PORT 362 15.5.4 COMPILING BY
PBLAZELDE 362 15.6 SYNTHESES WITH PICOBLAZE 363 15.7 BIBLIOGRAPHIC NOTES
364 15.8 SUGGESTED EXPERIMENTS 365 15.8.1 SIGNED MULTIPLICATION 365
15.8.2 MULTI-BYTE MULTIPLICATION 365 15.8.3 BARREL SHIFT FUNCTION 365
15.8.4 REVERSE FUNCTION 365 15.8.5 BINARY-TO-BCD CONVERSION 365 15.8.6
BCD-TO-BINARY CONVERSION 365 15.8.7 HEARTBEAT CIRCUIT 365 15.8.8
ROTATING LED CIRCUIT 366 15.8.9 DISCRETE LED DIMMER 366 16 PICOBLAZE I/O
INTERFACE 367 16.1 INTRODUCTION 367 16.2 OUTPUT PORT 368 16.2.1 OUTPUT
INSTRUCTION AND TIMING 368 16.2.2 OUTPUT INTERFACE 369 16.3 INPUT PORT
371 16.3.1 INPUT INSTRUCTION AND TIMING 371 16.3.2 INPUT INTERFACE 371
16.4 SQUARE PROGRAM WITH A SWITCH AND SEVEN-SEGMENT LED DISPLAY
INTERFACE 373 16.4.1 OUTPUT INTERFACE 374 16.4.2 INPUT INTERFACE 375
16.4.3 ASSEMBLY CODE DEVELOPMENT 376 16.4.4 VHDL CODE DEVELOPMENT 384
16.5 SQUARE PROGRAM WITH A COMBINATIONAL MULTIPLIER AND UART CONSOLE 386
16.5.1 MULTIPLIER INTERFACE 387 16.5.2 UART INTERFACE 387 16.5.3
ASSEMBLY CODE DEVELOPMENT 389 16.5.4 VHDL CODE DEVELOPMENT 398 16.6
BIBLIOGRAPHIC NOTES 402 16.7 SUGGESTED EXPERIMENTS 402 16.7.1
LOW-FREQUENCY COUNTER I 402 16.7.2 LOW-FREQUENCY COUNTER II 402 CONTENTS
XVII 16.7.3 AUTO-SCALED LOW-FREQUENCY COUNTER 402 16.7.4 BASIC REACTION
TIMER WITH A SOFTWARE TIMER 403 16.7.5 BASIC REACTION TIMER WITH A
HARDWARE TIMER 403 16.7.6 ENHANCED REACTION TIMER 403 16.7.7
SMALL-SCREEN MOUSE SCRIBBLE CIRCUIT 403 16.7.8 FULL-SCREEN MOUSE
SCRIBBLE CIRCUIT 403 16.7.9 ENHANCED ROTATING BANNER 403 16.7.10 PONG
GAME 404 16.7.11 TEXT EDITOR 404 17 PICOBLAZE INTERRUPT INTERFACE 405
17.1 INTRODUCTION 405 17.2 INTERRUPT HANDLING IN PICOBLAZE 405 17.2.1
SOFTWARE PROCESSING 406 17.2.2 TIMING 407 17.3 EXTERNAL INTERFACE 408
17.3.1 SINGLE INTERRUPT REQUEST 408 17.3.2 MULTIPLE INTERRUPT REQUESTS
408 17.4 SOFTWARE DEVELOPMENT CONSIDERATIONS 409 17.4.1 INTERRUPT AS AN
ALTERNATIVE SCHEDULING SCHEME 409 17.4.2 DEVELOPMENT OF AN INTERRUPT
SERVICE ROUTINE 410 17.5 DESIGN EXAMPLE 410 17.5.1 INTERRUPT INTERFACE
410 17.5.2 INTERRUPT SERVICE ROUTINE DEVELOPMENT 411 17.5.3 ASSEMBLY
CODE DEVELOPMENT 411 17.5.4 VHDL CODE DEVELOPMENT 413 17.6 BIBLIOGRAPHIC
NOTES 417 17.7 SUGGESTED EXPERIMENTS 417 17.7.1 ALTERNATIVE TIMER
INTERRUPT SERVICE ROUTINE 417 17.7.2 PROGRAMMABLE TIMER 417 17.7.3
SET-BUTTON INTERRUPT SERVICE ROUTINE 417 17.7.4 INTERRUPT INTERFACE WITH
TWO REQUESTS 417 17.7.5 FOUR-REQUEST INTERRUPT CONTROLLER 418 APPENDIX
A: SAMPLE VHDL TEMPLATES 419 A. 1 GENERAL VHDL CONSTRUCTS 419 A. 1.1
OVERALL CODE STRUCTURE 419 A. 1.2 COMPONENT INSTANTIATION 420 A.2
COMBINATIONAL CIRCUITS 421 A.2.1 ARITHMETIC OPERATIONS 421 A.2.2
FIXED-AMOUNT SHIFT OPERATIONS 422 XVIII CONTENTS A. 2.3 ROUTING WITH
CONCURRENT STATEMENTS 422 A.2.4 ROUTING WITH IF AND CASE STATEMENTS 423
A.2.5 COMBINATIONAL CIRCUIT USING PROCESS 424 A.3 MEMORY COMPONENTS 425
A.3.1 REGISTER TEMPLATE 425 A.3.2 REGISTER FILE 426 A.4 REGULAR
SEQUENTIAL CIRCUITS 427 A.5 FSM 428 A.6 FSMD 430 A.7 S3 BOARD CONSTRAINT
FILE (S3. UCF) 433 REFERENCES 437 TOPIC INDEX 439 |
| adam_txt |
FPGA PROTOTYPING BY VHDL EXAMPLES XILINX SPARTAN*-3 VERSION PONG P. CHU
CLEVELAND STATE UNIVERSITY WILEY- INTERSCIENCE A JOHN WILEY & SONS,
INC., PUBLICATION CONTENTS PREFACE XIX ACKNOWLEDGMENTS XXV PART I BASIC
DIGITAL CIRCUITS 1 GATE-LEVEL COMBINATIONAL CIRCUIT 1 1.1 INTRODUCTION 1
1.2 GENERAL DESCRIPTION 2 1.2.1 BASIC LEXICAL RULES 2 1.2.2 LIBRARY AND
PACKAGE 3 1.2.3 ENTITY DECLARATION 3 1.2.4 DATA TYPE AND OPERATORS 3
1.2.5 ARCHITECTURE BODY 4 1.2.6 CODE OF A 2-BIT COMPARATOR 5 1.3
STRUCTURAL DESCRIPTION 6 1.4 TESTBENCH 8 1.5 BIBLIOGRAPHIC NOTES 9 1.6
SUGGESTED EXPERIMENTS 10 1.6.1 CODE FOR GATE-LEVEL GREATER-THAN CIRCUIT
10 1.6.2 CODE FOR GATE-LEVEL BINARY DECODER 10 2 OVERVIEW OF FPGA AND
EDA SOFTWARE 11 VII VIII CONTENTS 2.1 INTRODUCTION 11 2.2 FPGA 11 2.2.1
OVERVIEW OF A GENERAL FPGA DEVICE 11 2.2.2 OVERVIEW OF THE XILINX
SPARTAN-3 DEVICES 13 2.3 OVERVIEW OF THE DIGILENT S3 BOARD 13 2.4
DEVELOPMENT FLOW 15 2.5 OVERVIEW OF THE XILINX ISE PROJECT NAVIGATOR 17
2.6 SHORT TUTORIAL ON ISE PROJECT NAVIGATOR 19 2.6.1 CREATE THE DESIGN
PROJECT AND HDL CODES 21 2.6.2 CREATE A TESTBENCH AND PERFORM THE RTL
SIMULATION 22 2.6.3 ADD A CONSTRAINT FILE AND SYNTHESIZE AND IMPLEMENT
THE CODE 22 2.6.4 GENERATE AND DOWNLOAD THE CONFIGURATION FILE TO AN
FPGA DEVICE 24 2.7 SHORT TUTORIAL ON THE MODELSIM HDL SIMULATOR 27 2.8
BIBLIOGRAPHIC NOTES 32 2.9 SUGGESTED EXPERIMENTS 33 2.9.1 GATE-LEVEL
GREATER-THAN CIRCUIT 33 2.9.2 GATE-LEVEL BINARY DECODER 33 3 RT-LEVEL
COMBINATIONAL CIRCUIT 35 3.1 INTRODUCTION 35 3.2 RT-LEVEL COMPONENTS 35
3.2.1 RELATIONAL OPERATORS 37 3.2.2 ARITHMETIC OPERATORS 37 3.2.3 OTHER
SYNTHESIS-RELATED VHDL CONSTRUCTS 38 3.2.4 SUMMARY 40 3.3 ROUTING
CIRCUIT WITH CONCURRENT ASSIGNMENT STATEMENTS 41 3.3.1 CONDITIONAL
SIGNAL ASSIGNMENT STATEMENT 41 3.3.2 SELECTED SIGNAL ASSIGNMENT
STATEMENT 44 3.4 MODELING WITH A PROCESS 46 3.4.1 PROCESS 46 3.4.2
SEQUENTIAL SIGNAL ASSIGNMENT STATEMENT 46 3.5 ROUTING CIRCUIT WITH IF
AND CASE STATEMENTS 47 3.5.1 IF STATEMENT 47 3.5.2 CASE STATEMENT 49
3.5.3 COMPARISON TO CONCURRENT STATEMENTS 50 3.5.4 UNINTENDED MEMORY 52
3.6 CONSTANTS AND GENERICS 53 3.6.1 CONSTANTS 53 3.6.2 GENERICS 54 3.7
DESIGN EXAMPLES 56 3.7.1 HEXADECIMAL DIGIT TO SEVEN-SEGMENT LED DECODER
56 3.7.2 SIGN-MAGNITUDE ADDER 59 CONTENTS IX 3.7.3 BARREL SHIFTER 62
3.7.4 SIMPLIFIED FLOATING-POINT ADDER 63 69 69 69 69 69 70 70 70 71 71
71 72 73 74 74 77 78 79 79 79 81 84 88 88 96 100 104 105 105 105 105 106
106 106 106 5 FSM 107 5.1 INTRODUCTION 107 3.8 3.9 BIBLIOGRAPHIC NOTES
SUGGESTED EXPERIMENTS 3.9.1 3.9.2 3.9.3 3.9.4 3.9.5 3.9.6 MULTI-FUNCTION
BARREL SHIFTER DUAL-PRIORITY ENCODER BCD INCREMENTOR FLOATING-POINT
GREATER-THAN CIRCUIT FLOATING-POINT AND SIGNED INTEGER CONVERSION
CIRCUIT ENHANCED FLOATING-POINT ADDER REGULAR SEQUENTIAL CIRCUIT 4.1 4.2
4.3 4.4 4.5 4.6 4.7 INTRODUCTION 4.1.1 4.1.2 4.1.3 D FF AND REGISTER
SYNCHRONOUS SYSTEM CODE DEVELOPMENT HDL CODE OF THE FF AND REGISTER
4.2.1 4.2.2 4.2.3 4.2.4 SIMP! 4.3.1 4.3.2 DFF REGISTER REGISTER FILE
STORAGE COMPONENTS IN A SPARTAN-3 DEV\CE XLHNX S P ECI F TC E DESIGN
EXAMPLES SHIFT REGISTER BINARY COUNTER AND VARIANT TESTBENCH FOR
SEQUENTIAL CIRCUITS CASE J 4.5.1 4.5.2 4.5.3 BIBLIO TUDY LED
TIME-MULTIPLEXING CIRCUIT STOPWATCH FIFO BUFFER GRAPHIC NOTES SUGGESTED
EXPERIMENTS 4.7.1 4.7.2 4.7.3 4.7.4 4.7.5 4.7.6 4.7.7 PROGRAMMABLE
SQUARE WAVE GENERATOR PWM AND LED DIMMER ROTATING SQUARE CIRCUIT
HEARTBEAT CIRCUIT ROTATING LED BANNER CIRCUIT ENHANCED STOPWATCH STACK X
CONTENTS 5.1.1 MEALY AND MOORE OUTPUTS 107 5.1.2 FSM REPRESENTATION 108
5.2 FSM CODE DEVELOPMENT 111 5.3 DESIGN EXAMPLES 114 5.3.1 RISING-EDGE
DETECTOR 114 5.3.2 DEBOUNCING CIRCUIT 118 5.3.3 TESTING CIRCUIT 122 5.4
BIBLIOGRAPHIC NOTES 124 5.5 SUGGESTED EXPERIMENTS 124 5.5.1 DUAL-EDGE
DETECTOR 124 5.5.2 ALTERNATIVE DEBOUNCING CIRCUIT 124 5.5.3 PARKING LOT
OCCUPANCY COUNTER 125 6 FSMD 127 6.1 INTRODUCTION 127 6.1.1 SINGLE RT
OPERATION 127 6.1.2 ASMD CHART 128 6.1.3 DECISION BOX WITH A REGISTER
129 6.2 CODE DEVELOPMENT OF AN FSMD 131 6.2.1 DEBOUNCING CIRCUIT BASED
ON RT METHODOLOGY 132 6.2.2 CODE WITH EXPLICIT DATA PATH COMPONENTS 134
6.2.3 CODE WITH IMPLICIT DATA PATH COMPONENTS 136 6.2.4 COMPARISON 137
6.2.5 TESTING CIRCUIT 138 6.3 DESIGN EXAMPLES 140 6.3.1 FIBONACCI NUMBER
CIRCUIT 140 6.3.2 DIVISION CIRCUIT 143 6.3.3 BINARY-TO-BCD CONVERSION
CIRCUIT 147 6.3.4 PERIOD COUNTER 150 6.3.5 ACCURATE LOW-FREQUENCY
COUNTER 153 6.4 BIBLIOGRAPHIC NOTES 156 6.5 SUGGESTED EXPERIMENTS 157
6.5.1 ALTERNATIVE DEBOUNCING CIRCUIT 157 6.5.2 BCD-TO-BINARY CONVERSION
CIRCUIT 157 6.5.3 FIBONACCI CIRCUIT WITH BCD I/O: DESIGN APPROACH 1 157
6.5.4 FIBONACCI CIRCUIT WITH BCD I/O: DESIGN APPROACH 2 157 6.5.5
AUTO-SCALED LOW-FREQUENCY COUNTER 158 6.5.6 REACTION TIMER 158 6.5.7
BABBAGE DIFFERENCE ENGINE EMULATION CIRCUIT 159 PART II I/O MODULES
CONTENTS XI 7 UART 163 7.1 INTRODUCTION 163 7.2 UART RECEIVING SUBSYSTEM
164 7.2.1 OVERSAMPLING PROCEDURE 164 7.2.2 BAUD RATE GENERATOR 165 7.2.3
UART RECEIVER 165 7.2.4 INTERFACE CIRCUIT 168 7.3 UART TRANSMITTING
SUBSYSTEM 171 7.4 OVERALL UART SYSTEM 174 7.4.1 COMPLETE UART CORE 174
7.4.2 UART VERIFICATION CONFIGURATION 176 7.5 CUSTOMIZING A UART 178 7.6
BIBLIOGRAPHIC NOTES 180 7.7 SUGGESTED EXPERIMENTS 180 7.7.1
FULL-FEATURED UART 180 7.7.2 UART WITH AN AUTOMATIC BAUD RATE DETECTION
CIRCUIT 181 7.7.3 UART WITH AN AUTOMATIC BAUD RATE AND PARITY DETECTION
CIRCUIT 181 7.7.4 UART-CONTROLLED STOPWATCH 181 7.7.5 UART-CONTROLLED
ROTATING LED BANNER 182 8 PS2 KEYBOARD 183 8.1 INTRODUCTION 183 8.2 PS2
RECEIVING SUBSYSTEM 184 8.2.1 PHYSICAL INTERFACE OF A PS2 PORT 184 8.2.2
DEVICE-TO-HOST COMMUNICATION PROTOCOL 184 8.2.3 DESIGN AND CODE 184 8.3
PS2 KEYBOARD SCAN CODE 188 8.3.1 OVERVIEW OF THE SCAN CODE 188 8.3.2
SCAN CODE MONITOR CIRCUIT 189 8.4 PS2 KEYBOARD INTERFACE CIRCUIT 191
8.4.1 BASIC DESIGN AND HDL CODE 192 8.4.2 VERIFICATION CIRCUIT 194 8.5
BIBLIOGRAPHIC NOTES 196 8.6 SUGGESTED EXPERIMENTS 196 8.6.1 ALTERNATIVE
KEYBOARD INTERFACE I 196 8.6.2 ALTERNATIVE KEYBOARD INTERFACE II 196
8.6.3 PS2 RECEIVING SUBSYSTEM WITH WATCHDOG TIMER 197 8.6.4
KEYBOARD-CONTROLLED STOPWATCH 197 8.6.5 KEYBOARD-CONTROLLED ROTATING LED
BANNER 197 9 PS2 MOUSE 199 XII CONTENTS 9.1 INTRODUCTION 199 9.2 PS2
MOUSE PROTOCOL 200 9.2.1 BASIC OPERATION 200 9.2.2 BASIC INITIALIZATION
PROCEDURE 200 9.3 PS2 TRANSMITTING SUBSYSTEM 201 9.3.1
HOST-TO-PS2-DEVICE COMMUNICATION PROTOCOL 201 9.3.2 DESIGN AND CODE 202
9.4 BIDIRECTIONAL PS2 INTERFACE 206 9.4.1 BASIC DESIGN AND CODE 206
9.4.2 VERIFICATION CIRCUIT 208 9.5 PS2 MOUSE INTERFACE 210 9.5.1 BASIC
DESIGN 210 9.5.2 TESTING CIRCUIT 212 9.6 BIBLIOGRAPHIC NOTES 214 9.7
SUGGESTED EXPERIMENTS 214 9.7.1 KEYBOARD CONTROL CIRCUIT 214 9.7.2
ENHANCED MOUSE INTERFACE 214 9.7.3 MOUSE-CONTROLLED SEVEN-SEGMENT LED
DISPLAY 214 10 EXTERNAL SRAM 215 10.1 INTRODUCTION 215 10.2
SPECIFICATION OF THE IS61LV25616AL SRAM 216 10.2.1 BLOCK DIAGRAM AND I/O
SIGNALS 216 10.2.2 TIMING PARAMETERS 216 10.3 BASIC MEMORY CONTROLLER
220 10.3.1 BLOCK DIAGRAM 220 10.3.2 TIMING REQUIREMENT 221 10.3.3
REGISTER FILE VERSUS SRAM 222 10.4 A SAFE DESIGN 222 10.4.1 ASMD CHART
222 10.4.2 TIMING ANALYSIS 223 10.4.3 HDL IMPLEMENTATION 224 10.4.4
BASIC TESTING CIRCUIT 226 10.4.5 COMPREHENSIVE SRAM TESTING CIRCUIT 228
10.5 MORE AGGRESSIVE DESIGN 233 10.5.1 TIMING ISSUES 233 10.5.2
ALTERNATIVE DESIGN I 234 10.5.3 ALTERNATIVE DESIGN II 236 10.5.4
ALTERNATIVE DESIGN 111 237 *.5.5 \TOANCEDFPGMEATOES XIUNXSPECI F IC 1*
10.6 BIBLIOGRAPHIC NOTES 240 10.7 SUGGESTED EXPERIMENTS 240 CONTENTS
XIII 10.7.1 MEMORY WITH A 512K-BY-16 CONFIGURATION 240 10.7.2 MEMORY
WITH A LM-BY-8 CONFIGURATION 240 10.7.3 MEMORY WITH AN 8M-BY-L
CONFIGURATION 240 10.7.4 EXPANDED MEMORY TESTING CIRCUIT 241 10.7.5
MEMORY CONTROLLER AND TESTING CIRCUIT FOR ALTERNATIVE DESIGN I 241
10.7.6 MEMORY CONTROLLER AND TESTING CIRCUIT FOR ALTERNATIVE DESIGN II
241 10.7.7 MEMORY CONTROLLER AND TESTING CIRCUIT FOR ALTERNATIVE DESIGN
III 241 10.7.8 MEMORY CONTROLLER WITH DCM 241 10.7.9 HIGH-PERFORMANCE
MEMORY CONTROLLER 241 11 XILINX SPARTAN-3 SPECIFIC MEMORY 243 11.1
INTRODUCTION 243 11.2 EMBEDDED MEMORY OF SPARTAN-3 DEVICE 243 11.2.1
OVERVIEW 243 11.2.2 COMPARISON 244 11.3 METHOD TO INCORPORATE MEMORY
MODULES 244 11.3.1 MEMORY MODULE VIA HDL COMPONENT INSTANTIATION 245
11.3.2 MEMORY MODULE VIA CORE GENERATOR 245 11.3.3 MEMORY MODULE VIA HDL
INFERENCE 246 11.4 HDL TEMPLATES FOR MEMORY INFERENCE 246 11.4.1
SINGLE-PORT RAM 246 11.4.2 DUAL-PORT RAM 249 11.4.3 ROM 251 11.5
BIBLIOGRAPHIC NOTES 254 11.6 SUGGESTED EXPERIMENTS 254 11.6.1
BLOCK-RAM-BASED FIFO 254 11.6.2 BLOCK-RAM-BASED STACK 254 11.6.3
ROM-BASED SIGN-MAGNITUDE ADDER 255 11.6.4 ROM BASED SIN(X) FUNCTION 255
11.6.5 ROM-BASED SIN (*) AND COS(:R) FUNCTIONS 255 12 VGA CONTROLLER I:
GRAPHIC 257 12.1 INTRODUCTION 257 12.1.1 BASIC OPERATION OF A CRT 257
12.1.2 VGA PORT OF THE S3 BOARD 259 12.1.3 VIDEO CONTROLLER 259 12.2 VGA
SYNCHRONIZATION 260 12.2.1 HORIZONTAL SYNCHRONIZATION 260 12.2.2
VERTICAL SYNCHRONIZATION 262 12.2.3 TIMING CALCULATION OF VGA
SYNCHRONIZATION SIGNALS 263 12.2.4 HDL IMPLEMENTATION 263 XJV CONTENTS
12.2.5 TESTING CIRCUIT 266 12.3 OVERVIEW OF THE PIXEL GENERATION CIRCUIT
267 12.4 GRAPHIC GENERATION WITH AN OBJECT-MAPPED SCHEME 268 12.4.1
RECTANGULAR OBJECTS 269 12.4.2 NON-RECTANGULAR OBJECT 273 12.4.3
ANIMATED OBJECT 275 12.5 GRAPHIC GENERATION WITH A BIT-MAPPED SCHEME 282
12.5.1 DUAL-PORT RAM IMPLEMENTATION 282 12.5.2 SINGLE-PORT RAM
IMPLEMENTATION 287 12.6 BIBLIOGRAPHIC NOTES 287 12.7 SUGGESTED
EXPERIMENTS 287 12.7.1 VGA TEST PATTERN GENERATOR 287 12.7.2 SVGA MODE
SYNCHRONIZATION CIRCUIT 288 12.7.3 VISIBLE SCREEN ADJUSTMENT CIRCUIT 288
12.7.4 BALL-IN-A-BOX CIRCUIT 288 12.7.5 TWO-BALLS-IN-A-BOX CIRCUIT 289
12.7.6 TWO-PLAYER PONG GAME 289 12.7.7 BREAKOUT GAME 289 12.7.8
FULL-SCREEN DOT TRACE 289 12.7.9 MOUSE POINTER CIRCUIT 290 12.7.10
SMALL-SCREEN MOUSE SCRIBBLE CIRCUIT 290 12.7.11 FULL-SCREEN MOUSE
SCRIBBLE CIRCUIT 290 13 VGA CONTROLLER II: TEXT 291 13.1 INTRODUCTION
291 13.2 TEXT GENERATION 291 13.2.1 CHARACTER AS A TILE 291 13.2.2 FONT
ROM 292 13.2.3 BASIC TEXT GENERATION CIRCUIT 294 13.2.4 FONT DISPLAY
CIRCUIT 295 13.2.5 FONT SCALING 297 13.3 FULL-SCREEN TEXT DISPLAY 298
13.4 THE COMPLETE PONG GAME 302 13.4.1 TEXT SUBSYSTEM 302 13.4.2
MODIFIED GRAPHIC SUBSYSTEM 309 13.4.3 AUXILIARY COUNTERS 310 13.4.4
TOP-LEVEL SYSTEM 312 13.5 BIBLIOGRAPHIC NOTES 317 13.6 SUGGESTED
EXPERIMENTS 317 13.6.1 ROTATING BANNER 317 13.6.2 UNDERLINE FOR THE
CURSOR 317 13.6.3 DUAL-MODE TEXT DISPLAY 317 CONTENTS XV 13.6.4 KEYBOARD
TEXT ENTRY 317 13.6.5 UART TERMINAL 317 13.6.6 SQUARE WAVE DISPLAY 318
13.6.7 SIMPLE FOUR-TRACE LOGIC ANALYZER 318 13.6.8 COMPLETE TWO-PLAYER
PONG GAME 319 13.6.9 COMPLETE BREAKOUT GAME 319 PART III PICOBLAZE
MICROCONTROLLER* 77 7JVY SPECIFIC 14 PICOBLAZE OVERVIEW 323 14.1
INTRODUCTION 323 14.2 CUSTOMIZED HARDWARE AND CUSTOMIZED SOFTWARE 324
14.2.1 FROM SPECIAL-PURPOSE FSMD TO GENERAL-PURPOSE MICROCONTROLLER 324
14.2.2 APPLICATION OF MICROCONTROLLER 326 14.3 OVERVIEW OF PICOBLAZE 326
14.3.1 BASIC ORGANIZATION 326 14.3.2 TOP-LEVEL HDL MODULES 328 14.4
DEVELOPMENT FLOW 329 14.5 INSTRUCTION SET 329 14.5.1 PROGRAMMING MODEL
331 14.5.2 INSTRUCTION FORMAT 332 14.5.3 LOGICAL INSTRUCTIONS 332 14.5.4
ARITHMETIC INSTRUCTIONS 333 14.5.5 COMPARE AND TEST INSTRUCTIONS 334
14.5.6 SHIFT AND ROTATE INSTRUCTIONS 335 14.5.7 DATA MOVEMENT
INSTRUCTIONS 336 14.5.8 PROGRAM FLOW CONTROL INSTRUCTIONS 338 14.5.9
INTERRUPT RELATED INSTRUCTIONS 341 14.6 ASSEMBLER DIRECTIVES 342 14.6.1
THE KCPSM3 DIRECTIVES 342 14.6.2 THE PBLAZELDE DIRECTIVES 342 14.7
BIBLIOGRAPHIC NOTES 343 15 PICOBLAZE ASSEMBLY CODE DEVELOPMENT 345 15.1
INTRODUCTION 345 15.2 USEFUL CODE SEGMENTS 345 15.2.1 KCPSM3 CONVENTIONS
345 15.2.2 BIT MANIPULATION 346 15.2.3 MULTIPLE-BYTE MANIPULATION 347
15.2.4 CONTROL STRUCTURE 348 15.3 SUBROUTINE DEVELOPMENT 350 15.4
PROGRAM DEVELOPMENT 351 XVI CONTENTS 15.4.1 DEMONSTRATION EXAMPLE 352
15.4.2 PROGRAM DOCUMENTATION 356 15.5 PROCESSING OF THE ASSEMBLY CODE
358 15.5.1 COMPILING WITH KCSPM3 358 15.5.2 SIMULATION BY PBLAZELDE 359
15.5.3 RELOADING CODE VIA THE JTAG PORT 362 15.5.4 COMPILING BY
PBLAZELDE 362 15.6 SYNTHESES WITH PICOBLAZE 363 15.7 BIBLIOGRAPHIC NOTES
364 15.8 SUGGESTED EXPERIMENTS 365 15.8.1 SIGNED MULTIPLICATION 365
15.8.2 MULTI-BYTE MULTIPLICATION 365 15.8.3 BARREL SHIFT FUNCTION 365
15.8.4 REVERSE FUNCTION 365 15.8.5 BINARY-TO-BCD CONVERSION 365 15.8.6
BCD-TO-BINARY CONVERSION 365 15.8.7 HEARTBEAT CIRCUIT 365 15.8.8
ROTATING LED CIRCUIT 366 15.8.9 DISCRETE LED DIMMER 366 16 PICOBLAZE I/O
INTERFACE 367 16.1 INTRODUCTION 367 16.2 OUTPUT PORT 368 16.2.1 OUTPUT
INSTRUCTION AND TIMING 368 16.2.2 OUTPUT INTERFACE 369 16.3 INPUT PORT
371 16.3.1 INPUT INSTRUCTION AND TIMING 371 16.3.2 INPUT INTERFACE 371
16.4 SQUARE PROGRAM WITH A SWITCH AND SEVEN-SEGMENT LED DISPLAY
INTERFACE 373 16.4.1 OUTPUT INTERFACE 374 16.4.2 INPUT INTERFACE 375
16.4.3 ASSEMBLY CODE DEVELOPMENT 376 16.4.4 VHDL CODE DEVELOPMENT 384
16.5 SQUARE PROGRAM WITH A COMBINATIONAL MULTIPLIER AND UART CONSOLE 386
16.5.1 MULTIPLIER INTERFACE 387 16.5.2 UART INTERFACE 387 16.5.3
ASSEMBLY CODE DEVELOPMENT 389 16.5.4 VHDL CODE DEVELOPMENT 398 16.6
BIBLIOGRAPHIC NOTES 402 16.7 SUGGESTED EXPERIMENTS 402 16.7.1
LOW-FREQUENCY COUNTER I 402 16.7.2 LOW-FREQUENCY COUNTER II 402 CONTENTS
XVII 16.7.3 AUTO-SCALED LOW-FREQUENCY COUNTER 402 16.7.4 BASIC REACTION
TIMER WITH A SOFTWARE TIMER 403 16.7.5 BASIC REACTION TIMER WITH A
HARDWARE TIMER 403 16.7.6 ENHANCED REACTION TIMER 403 16.7.7
SMALL-SCREEN MOUSE SCRIBBLE CIRCUIT 403 16.7.8 FULL-SCREEN MOUSE
SCRIBBLE CIRCUIT 403 16.7.9 ENHANCED ROTATING BANNER 403 16.7.10 PONG
GAME 404 16.7.11 TEXT EDITOR 404 17 PICOBLAZE INTERRUPT INTERFACE 405
17.1 INTRODUCTION 405 17.2 INTERRUPT HANDLING IN PICOBLAZE 405 17.2.1
SOFTWARE PROCESSING 406 17.2.2 TIMING 407 17.3 EXTERNAL INTERFACE 408
17.3.1 SINGLE INTERRUPT REQUEST 408 17.3.2 MULTIPLE INTERRUPT REQUESTS
408 17.4 SOFTWARE DEVELOPMENT CONSIDERATIONS 409 17.4.1 INTERRUPT AS AN
ALTERNATIVE SCHEDULING SCHEME 409 17.4.2 DEVELOPMENT OF AN INTERRUPT
SERVICE ROUTINE 410 17.5 DESIGN EXAMPLE 410 17.5.1 INTERRUPT INTERFACE
410 17.5.2 INTERRUPT SERVICE ROUTINE DEVELOPMENT 411 17.5.3 ASSEMBLY
CODE DEVELOPMENT 411 17.5.4 VHDL CODE DEVELOPMENT 413 17.6 BIBLIOGRAPHIC
NOTES 417 17.7 SUGGESTED EXPERIMENTS 417 17.7.1 ALTERNATIVE TIMER
INTERRUPT SERVICE ROUTINE 417 17.7.2 PROGRAMMABLE TIMER 417 17.7.3
SET-BUTTON INTERRUPT SERVICE ROUTINE 417 17.7.4 INTERRUPT INTERFACE WITH
TWO REQUESTS 417 17.7.5 FOUR-REQUEST INTERRUPT CONTROLLER 418 APPENDIX
A: SAMPLE VHDL TEMPLATES 419 A. 1 GENERAL VHDL CONSTRUCTS 419 A. 1.1
OVERALL CODE STRUCTURE 419 A. 1.2 COMPONENT INSTANTIATION 420 A.2
COMBINATIONAL CIRCUITS 421 A.2.1 ARITHMETIC OPERATIONS 421 A.2.2
FIXED-AMOUNT SHIFT OPERATIONS 422 XVIII CONTENTS A. 2.3 ROUTING WITH
CONCURRENT STATEMENTS 422 A.2.4 ROUTING WITH IF AND CASE STATEMENTS 423
A.2.5 COMBINATIONAL CIRCUIT USING PROCESS 424 A.3 MEMORY COMPONENTS 425
A.3.1 REGISTER TEMPLATE 425 A.3.2 REGISTER FILE 426 A.4 REGULAR
SEQUENTIAL CIRCUITS 427 A.5 FSM 428 A.6 FSMD 430 A.7 S3 BOARD CONSTRAINT
FILE (S3. UCF) 433 REFERENCES 437 TOPIC INDEX 439 |
| any_adam_object | 1 |
| any_adam_object_boolean | 1 |
| author | Chu, Pong P. |
| author_facet | Chu, Pong P. |
| author_role | aut |
| author_sort | Chu, Pong P. |
| author_variant | p p c pp ppc |
| building | Verbundindex |
| bvnumber | BV023071027 |
| callnumber-first | T - Technology |
| callnumber-label | TK7895 |
| callnumber-raw | TK7895.G36 |
| callnumber-search | TK7895.G36 |
| callnumber-sort | TK 47895 G36 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ST 250 ZN 4904 ZN 4940 |
| classification_tum | ELT 453f |
| ctrlnum | (OCoLC)836659178 (DE-599)GBV537760342 |
| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| discipline_str_mv | Informatik Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| genre | (DE-588)4173536-5 Patentschrift gnd-content |
| genre_facet | Patentschrift |
| id | DE-604.BV023071027 |
| illustrated | Illustrated |
| index_date | 2024-07-02T19:33:02Z |
| indexdate | 2024-09-06T00:15:00Z |
| institution | BVB |
| isbn | 0470185317 9780470185315 |
| language | English |
| lccn | 007029063 |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-016274175 |
| oclc_num | 836659178 |
| open_access_boolean | |
| owner | DE-573 DE-859 DE-Aug4 DE-29T DE-83 DE-M347 DE-898 DE-BY-UBR DE-706 DE-19 DE-BY-UBM DE-522 |
| owner_facet | DE-573 DE-859 DE-Aug4 DE-29T DE-83 DE-M347 DE-898 DE-BY-UBR DE-706 DE-19 DE-BY-UBM DE-522 |
| physical | XXV, 440 S. Ill., graph. Darst. |
| publishDate | 2008 |
| publishDateSearch | 2008 |
| publishDateSort | 2008 |
| publisher | Wiley-Interscience |
| record_format | marc |
| spelling | Chu, Pong P. Verfasser aut FPGA prototyping by VHDL examples Xilinx Spartan-3 version Pong P. Chu Hoboken, NJ Wiley-Interscience 2008 XXV, 440 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Field programmable gate arrays / Design and construction Prototypes, Engineering VHDL (Computer hardware description language) Field programmable gate arrays Design and construction Field programmable gate array (DE-588)4347749-5 gnd rswk-swf VHDL (DE-588)4254792-1 gnd rswk-swf (DE-588)4173536-5 Patentschrift gnd-content Field programmable gate array (DE-588)4347749-5 s VHDL (DE-588)4254792-1 s DE-604 GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016274175&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Chu, Pong P. FPGA prototyping by VHDL examples Xilinx Spartan-3 version Field programmable gate arrays / Design and construction Prototypes, Engineering VHDL (Computer hardware description language) Field programmable gate arrays Design and construction Field programmable gate array (DE-588)4347749-5 gnd VHDL (DE-588)4254792-1 gnd |
| subject_GND | (DE-588)4347749-5 (DE-588)4254792-1 (DE-588)4173536-5 |
| title | FPGA prototyping by VHDL examples Xilinx Spartan-3 version |
| title_auth | FPGA prototyping by VHDL examples Xilinx Spartan-3 version |
| title_exact_search | FPGA prototyping by VHDL examples Xilinx Spartan-3 version |
| title_exact_search_txtP | FPGA prototyping by VHDL examples Xilinx Spartan-3 version |
| title_full | FPGA prototyping by VHDL examples Xilinx Spartan-3 version Pong P. Chu |
| title_fullStr | FPGA prototyping by VHDL examples Xilinx Spartan-3 version Pong P. Chu |
| title_full_unstemmed | FPGA prototyping by VHDL examples Xilinx Spartan-3 version Pong P. Chu |
| title_short | FPGA prototyping by VHDL examples |
| title_sort | fpga prototyping by vhdl examples xilinx spartan 3 version |
| title_sub | Xilinx Spartan-3 version |
| topic | Field programmable gate arrays / Design and construction Prototypes, Engineering VHDL (Computer hardware description language) Field programmable gate arrays Design and construction Field programmable gate array (DE-588)4347749-5 gnd VHDL (DE-588)4254792-1 gnd |
| topic_facet | Field programmable gate arrays / Design and construction Prototypes, Engineering VHDL (Computer hardware description language) Field programmable gate arrays Design and construction Field programmable gate array VHDL Patentschrift |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016274175&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT chupongp fpgaprototypingbyvhdlexamplesxilinxspartan3version |