Holdings: Digital signal processing with field programmable gate arrays

Digital signal processing with field programmable gate arrays: with ... 98 tables

Saved in:

Bibliographic Details
Main Author:	Meyer-Baese, Uwe 1964- (Author)
Format:	Book
Language:	English
Published:	Berlin [u.a.] Springer 2007
Edition:	3. ed.
Series:	Signals and communication technology
Subjects:	Digitale Signalverarbeitung - Field programmable gate array - Lehrbuch aSignal processing > xDigital techniques aField programmable gate arrays Field programmable gate array Digitale Signalverarbeitung Lehrbuch
Online Access:	Beschreibung für Leser Inhaltsverzeichnis Inhaltsverzeichnis
Item Description:	Includes bibliographical references (p. [423]-434) and index
Physical Description:	XX, 774 S. graph. Darst. 1 CD-ROM (12 cm)
ISBN:	9783540726128

Staff View

MARC


LEADER	00000nam a2200000zc 4500
001	BV023020936
003	DE-604
005	20090602
007	t
008	071126s2007 gw d\|\|\| \|\|\|\| 00\|\|\| eng d
020			\|a 9783540726128 \|c alk. paper \|9 978-3-540-72612-8
035			\|a (OCoLC)255668731
035			\|a (DE-599)BVBBV023020936
040			\|a DE-604 \|b ger \|e aacr
041	0		\|a eng
044			\|a gw \|c DE
049			\|a DE-706 \|a DE-859 \|a DE-92 \|a DE-91 \|a DE-523 \|a DE-634 \|a DE-83 \|a DE-B768
050		0	\|a TK5102.9
082	0		\|a 620
084			\|a ZN 6040 \|0 (DE-625)157496: \|2 rvk
084			\|a ELT 517f \|2 stub
100	1		\|a Meyer-Baese, Uwe \|d 1964- \|e Verfasser \|0 (DE-588)14179514X \|4 aut
245	1	0	\|a Digital signal processing with field programmable gate arrays \|b with ... 98 tables \|c Uwe Meyer-Baese
250			\|a 3. ed.
264		1	\|a Berlin [u.a.] \|b Springer \|c 2007
300			\|a XX, 774 S. \|b graph. Darst. \|e 1 CD-ROM (12 cm)
336			\|b txt \|2 rdacontent
337			\|b n \|2 rdamedia
338			\|b nc \|2 rdacarrier
490	0		\|a Signals and communication technology
500			\|a Includes bibliographical references (p. [423]-434) and index
650		4	\|a Digitale Signalverarbeitung - Field programmable gate array - Lehrbuch
650		4	\|a aSignal processing \|a xDigital techniques
650		4	\|a aField programmable gate arrays
650	0	7	\|a Field programmable gate array \|0 (DE-588)4347749-5 \|2 gnd \|9 rswk-swf
650	0	7	\|a Digitale Signalverarbeitung \|0 (DE-588)4113314-6 \|2 gnd \|9 rswk-swf
655		7	\|0 (DE-588)4123623-3 \|a Lehrbuch \|2 gnd-content
689	0	0	\|a Digitale Signalverarbeitung \|0 (DE-588)4113314-6 \|D s
689	0	1	\|a Field programmable gate array \|0 (DE-588)4347749-5 \|D s
689	0		\|5 DE-604
856	4		\|u http://deposit.dnb.de/cgi-bin/dokserv?id=2944556&prov=M&dok_var=1&dok_ext=htm \|3 Beschreibung für Leser
856	4		\|u http://www.ulb.tu-darmstadt.de/tocs/193884038.pdf \|3 Inhaltsverzeichnis
856	4	2	\|m HEBIS Datenaustausch Darmstadt \|q application/pdf \|u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016224997&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA \|3 Inhaltsverzeichnis
943	1		\|a oai:aleph.bib-bvb.de:BVB01-016224997

Record in the Search Index

_version_	1805089677781237760
adam_text	UWE MEYER-BAESE DIGITAL SIGNAL PROCESSING WITH FIELD PROGRAMMABLE GATE ARRAYS THIRD EDITION WITH 359 FIGURES AND 98 TABLES BOOK WITH CD-ROM 4Y SPRINGER CONTENTS PREFACE VII PREFACE TO SECOND EDITION XI PREFACE TO THIRD EDITION XIII 1. INTRODUCTION 1 1.1 OVERVIEW OF DIGITAL SIGNAL PROCESSING (DSP) 1 1.2 FPGA TECHNOLOGY 3 1.2.1 CLASSIFICATION BY GRANULARITY 3 1.2.2 CLASSIFICATION BY TECHNOLOGY 6 1.2.3 BENCHMARK FOR FPLS 7 1.3 DSP TECHNOLOGY REQUIREMENTS 10 1.3.1 FPGA AND PROGRAMMABLE SIGNAL PROCESSORS 12 1.4 DESIGN IMPLEMENTATION 13 1.4.1 FPGA STRUCTURE 18 1.4.2 THE ALTERA EP2C35F672C6 22 1.4.3 CASE STUDY: FREQUENCY SYNTHESIZER 29 1.4.4 DESIGN WITH INTELLECTUAL PROPERTY CORES 35 EXERCISES 42 2. COMPUTER ARITHMETIC 53 2.1 INTRODUCTION 53 2.2 NUMBER REPRESENTATION 54 2.2.1 FIXED-POINT NUMBERS 54 2.2.2 UNCONVENTIONAL FIXED-POINT NUMBERS 57 2.2.3 FLOATING-POINT NUMBERS P. 71 2.3 BINARY ADDERS 74 2.3.1 PIPELINED ADDERS 76 2.3.2 MODULO ADDERS 80 2.4 BINARY MULTIPLIERS 82 2.4.1 MULTIPLIER BLOCKS 87 2.5 BINARY DIVIDERS 91 2.5.1 LINEAR CONVERGENCE DIVISION ALGORITHMS 93 XVI CONTENTS 2.5.2 FAST DIVIDER DESIGN 98 2.5.3 ARRAY DIVIDER 103 2.6 FLOATING-POINT ARITHMETIC IMPLEMENTATION 104 2.6.1 FIXED-POINT TO FLOATING-POINT FORMAT CONVERSION 105 2.6.2 FLOATING-POINT TO FIXED-POINT FORMAT CONVERSION 106 2.6.3 FLOATING-POINT MULTIPLICATION 107 2.6.4 FLOATING-POINT ADDITION 108 2.6.5 FLOATING-POINT DIVISION 110 2.6.6 FLOATING-POINT RECIPROCAL 112 2.6.7 FLOATING-POINT SYNTHESIS RESULTS 114 2.7 MULTIPLY-ACCUMULATOR (MAC) AND SUM OF PRODUCT (SOP) . 114 2.7.1 DISTRIBUTED ARITHMETIC FUNDAMENTALS 115 2.7.2 SIGNED DA SYSTEMS 118 2.7.3 MODIFIED DA SOLUTIONS 120 2.8 COMPUTATION OF SPECIAL FUNCTIONS USING CORDIC 120 2.8.1 CORDIC ARCHITECTURES 125 2.9 COMPUTATION OF SPECIAL FUNCTIONS USING MAC CALLS 130 2.9.1 CHEBYSHEV APPROXIMATIONS 131 2.9.2 TRIGONOMETRIC FUNCTION APPROXIMATION 132 2.9.3 EXPONENTIAL AND LOGARITHMIC FUNCTION APPROXIMATION 141 2.9.4 SQUARE ROOT FUNCTION APPROXIMATION 148 EXERCISES 154 3. FINITE IMPULSE RESPONSE (FIR) DIGITAL FILTERS 165 3.1 DIGITAL FILTERS 165 3.2 FIR THEORY 166 3.2.1 FIR FILTER WITH TRANSPOSED STRUCTURE 167 3.2.2 SYMMETRY IN FIR FILTERS 170 3.2.3 LINEAR-PHASE FIR FILTERS 171 3.3 DESIGNING FIR FILTERS 172 3.3.1 DIRECT WINDOW DESIGN METHOD 173 3.3.2 EQUIRIPPLE DESIGN METHOD 175 3.4 CONSTANT COEFFICIENT FIR DESIGN 177 3.4.1 DIRECT FIR DESIGN 178 3.4.2 FIR FILTER WITH TRANSPOSED STRUCTURE 182 3.4.3 FIR FILTERS USING DISTRIBUTED ARITHMETIC 189 3.4.4 IP CORE FIR FILTER DESIGN F. 204 3.4.5 COMPARISON OF DA- AND RAG-BASED FIR FILTERS 207 EXERCISES 209 4. INFINITE IMPULSE RESPONSE (IIR) DIGITAL FILTERS 215 4.1 IIR THEORY 218 4.2 IIR COEFFICIENT COMPUTATION 221 4.2.1 SUMMARY OF IMPORTANT IIR DESIGN ATTRIBUTES 223 4.3 IIR FILTER IMPLEMENTATION 224 CONTENTS XVII 4.3.1 FINITE WORDLENGTH EFFECTS 228 4.3.2 OPTIMIZATION OF THE FILTER GAIN FACTOR 229 4.4 FAST IIR FILTER , 230 4.4.1 TIME-DOMAIN INTERLEAVING 230 4.4.2 CLUSTERED AND SCATTERED LOOK-AHEAD PIPELINING 233 4.4.3 IIR DECIMATOR DESIGN 235 4.4.4 PARALLEL PROCESSING 236 4.4.5 IIR DESIGN USING RNS 239 EXERCISES 240 5. MULTIRATE SIGNAL PROCESSING 245 5.1 DECIMATION AND INTERPOLATION 245 5.1.1 NOBLE IDENTITIES 246 5.1.2 SAMPLING RATE CONVERSION BY RATIONAL FACTOR 248 5.2 POLYPHASE DECOMPOSITION 249 5.2.1 RECURSIVE IIR DECIMATOR 254 5.2.2 FAST-RUNNING FIR FILTER 254 5.3 HOGENAUER CIC FILTERS 256 5.3.1 SINGLE-STAGE CIC CASE STUDY 257 5.3.2 MULTISTAGE CIC FILTER THEORY 259 5.3.3 AMPLITUDE AND ALIASING DISTORTION 264 5.3.4 HOGENAUER PRUNING THEORY 266 5.3.5 CIC RNS DESIGN 272 5.4 MULTISTAGE DECIMATOR 273 5.4.1 MULTISTAGE DECIMATOR DESIGN USING GOODMAN-CAREY HALF-BAND FILTERS 274 5.5 FREQUENCY-SAMPLING FILTERS AS BANDPASS DECIMATORS 277 5.6 DESIGN OF ARBITRARY SAMPLING RATE CONVERTERS 280 5.6.1 FRACTIONAL DELAY RATE CHANGE 284 5.6.2 POLYNOMIAL FRACTIONAL DELAY DESIGN 290 5.6.3 B-SPLINE-BASED FRACTIONAL RATE CHANGER 296 5.6.4 MOMS FRACTIONAL RATE CHANGER 301 5.7 FILTER BANKS 308 5.7.1 UNIFORM DFT FILTER BANK 309 5.7.2 TWO-CHANNEL FILTER BANKS 313 5.8 WAVELETS 328 5.8.1 THE DISCRETE WAVELET TRANSFORMATION 332 EXERCISES 335 6. FOURIER TRANSFORMS 343 6.1 THE DISCRETE FOURIER TRANSFORM ALGORITHMS 344 6.1.1 FOURIER TRANSFORM APPROXIMATIONS USING THE DFT . 344 6.1.2 PROPERTIES OF THE DFT 346 6.1.3 THE GOERTZEL ALGORITHM 349 6.1.4 THE BLUESTEIN CHIRP-Z TRANSFORM 350 XVIII CONTENTS 6.1.5 THE RADER ALGORITHM 353 6.1.6 THE WINOGRAD DFT ALGORITHM 359 6.2 THE FAST FOURIER TRANSFORM (FFT) ALGORITHMS 361 6.2.1 THE COOLEY-TUKEY FFT ALGORITHM 363 6.2.2 THE GOOD-THOMAS FFT ALGORITHM 373 6.2.3 THE WINOGRAD FFT ALGORITHM 375 6.2.4 COMPARISON OF DFT AND FFT ALGORITHMS 379 6.2.5 IP CORE FFT DESIGN 381 6.3 FOURIER-RELATED TRANSFORMS 385 6.3.1 COMPUTING THE DCT USING THE DFT 387 6.3.2 FAST DIRECT DCT IMPLEMENTATION 388 EXERCISES 391 7. ADVANCED TOPICS 401 7.1 RECTANGULAR AND NUMBER THEORETIC TRANSFORMS (NTTS) 401 7.1.1 ARITHMETIC MODULO 2 B 1 403 7.1.2 EFFICIENT CONVOLUTIONS USING NTTS 405 7.1.3 FAST CONVOLUTION USING NTTS 405 7.1.4 MULTIDIMENSIONAL INDEX MAPS 409 7.1.5 COMPUTING THE DFT MATRIX WITH NTTS 411 7.1.6 INDEX MAPS FOR NTTS 413 7.1.7 USING RECTANGULAR TRANSFORMS TO COMPUTE THE DFT . 416 7.2 ERROR CONTROL AND CRYPTOGRAPHY 418 7.2.1 BASIC CONCEPTS FROM CODING THEORY 419 7.2.2 BLOCK CODES 424 7.2.3 CONVOLUTIONAL CODES 428 7.2.4 CRYPTOGRAPHY ALGORITHMS FOR FPGAS 436 7.3 MODULATION AND DEMODULATION 453 7.3.1 BASIC MODULATION CONCEPTS 453 7.3.2 INCOHERENT DEMODULATION 457 7.3.3 COHERENT DEMODULATION 463 EXERCISES 472 8. ADAPTIVE FILTERS 477 8.1 APPLICATION OF ADAPTIVE FILTER 478 8.1.1 INTERFERENCE CANCELLATION 478 8.1.2 PREDICTION » 479 8.1.3 INVERSE MODELING 479 8.1.4 IDENTIFICATION 480 8.2 OPTIMUM ESTIMATION TECHNIQUES 481 8.2.1 THE OPTIMUM WIENER ESTIMATION 482 8.3 THE WIDROW-HOFF LEAST MEAN SQUARE ALGORITHM 486 8.3.1 LEARNING CURVES 493 8.3.2 NORMALIZED LMS (NLMS) 496 8.4 TRANSFORM DOMAIN LMS ALGORITHMS 498 CONTENTS XIX 8.4.1 FAST-CONVOLUTION TECHNIQUES 498 8.4.2 USING ORTHOGONAL TRANSFORMS 500 8.5 IMPLEMENTATION OF THE LMS ALGORITHM 503 8.5.1 QUANTIZATION EFFECTS 504 8.5.2 FPGA DESIGN OF THE LMS ALGORITHM 504 8.5.3 PIPELINED LMS FILTERS 507 8.5.4 TRANSPOSED FORM LMS FILTER 510 8.5.5 DESIGN OF DLMS ALGORITHMS 511 8.5.6 LMS DESIGNS USING SIGNUM FUNCTION 515 8.6 RECURSIVE LEAST SQUARE ALGORITHMS 518 8.6.1 RLS WITH FINITE MEMORY 521 8.6.2 FAST RLS KALMAN IMPLEMENTATION 524 8.6.3 THE FAST A POSTERIORI KALMAN RLS ALGORITHM 529 8.7 COMPARISON OF LMS AND RLS PARAMETERS 530 EXERCISES 532 9. MICROPROCESSOR DESIGN 537 9.1 HISTORY OF MICROPROCESSORS 537 9.1.1 BRIEF HISTORY OF GENERAL-PURPOSE MICROPROCESSORS . 538 9.1.2 BRIEF HISTORY OF RISC MICROPROCESSORS 540 9.1.3 BRIEF HISTORY OF PDSPS 541 9.2 INSTRUCTION SET DESIGN 544 9.2.1 ADDRESSING MODES 544 9.2.2 DATA FLOW: ZERO-,ONE-, TWO- OR THREE-ADDRESS DESIGN 552 9.2.3 REGISTER FILE AND MEMORY ARCHITECTURE 558 9.2.4 OPERATION SUPPORT 562 9.2.5 NEXT OPERATION LOCATION 565 9.3 SOFTWARE TOOLS 566 9.3.1 LEXICAL ANALYSIS 567 9.3.2 PARSER DEVELOPMENT 578 9.4 FPGA MICROPROCESSOR CORES 588 9.4.1 HARDCORE MICROPROCESSORS 589 9.4.2 SOFTCORE MICROPROCESSORS 594 9.5 CASE STUDIES 605 9.5.1 T-RISC STACK MICROPROCESSORS 605 9.5.2 LISA WAVELET PROCESSOR DESIGN 610 9.5.3 NIOS FFT DESIGN T 625 EXERCISES 634 REFERENCES 645 A. VERILOG SOURCE CODE 2001 66 1 XX CONTENTS B. VHDL AND VERILOG CODING 729 B.I LIST OF EXAMPLES 731 B.2 LIBRARY OF PARAMETERIZED MODULES (LPM) 733 B.2.1 THE PARAMETERIZED FLIP-FLOP MEGAFUNCTION (LPM_FF) . 733 B.2.2 THE ADDER/SUBTRACTOR MEGAFUNCTION 737 B.2.3 THE PARAMETERIZED MULTIPLIER MEGAFUNCTION (LPM-MULT) 741 B.2.4 THE PARAMETERIZED ROM MEGAFUNCTION (LPM_ROM) . 746 B.2.5 THE PARAMETERIZED DIVIDER MEGAFUNCTION (LPM-DIVIDE) 749 B.2.6 THE PARAMETERIZED RAM MEGAFUNCTION (LPM_RAM_DQ) 751 C. GLOSSARY 755 D. CD-ROM FILE: "LREADME.PS" 761 INDEX 769
adam_txt	UWE MEYER-BAESE DIGITAL SIGNAL PROCESSING WITH FIELD PROGRAMMABLE GATE ARRAYS THIRD EDITION WITH 359 FIGURES AND 98 TABLES BOOK WITH CD-ROM 4Y SPRINGER CONTENTS PREFACE VII PREFACE TO SECOND EDITION XI PREFACE TO THIRD EDITION XIII 1. INTRODUCTION 1 1.1 OVERVIEW OF DIGITAL SIGNAL PROCESSING (DSP) 1 1.2 FPGA TECHNOLOGY 3 1.2.1 CLASSIFICATION BY GRANULARITY 3 1.2.2 CLASSIFICATION BY TECHNOLOGY 6 1.2.3 BENCHMARK FOR FPLS 7 1.3 DSP TECHNOLOGY REQUIREMENTS 10 1.3.1 FPGA AND PROGRAMMABLE SIGNAL PROCESSORS 12 1.4 DESIGN IMPLEMENTATION 13 1.4.1 FPGA STRUCTURE 18 1.4.2 THE ALTERA EP2C35F672C6 22 1.4.3 CASE STUDY: FREQUENCY SYNTHESIZER 29 1.4.4 DESIGN WITH INTELLECTUAL PROPERTY CORES 35 EXERCISES 42 2. COMPUTER ARITHMETIC 53 2.1 INTRODUCTION 53 2.2 NUMBER REPRESENTATION 54 2.2.1 FIXED-POINT NUMBERS 54 2.2.2 UNCONVENTIONAL FIXED-POINT NUMBERS 57 2.2.3 FLOATING-POINT NUMBERS P. 71 2.3 BINARY ADDERS 74 2.3.1 PIPELINED ADDERS 76 2.3.2 MODULO ADDERS 80 2.4 BINARY MULTIPLIERS 82 2.4.1 MULTIPLIER BLOCKS 87 2.5 BINARY DIVIDERS 91 2.5.1 LINEAR CONVERGENCE DIVISION ALGORITHMS 93 XVI CONTENTS 2.5.2 FAST DIVIDER DESIGN 98 2.5.3 ARRAY DIVIDER 103 2.6 FLOATING-POINT ARITHMETIC IMPLEMENTATION 104 2.6.1 FIXED-POINT TO FLOATING-POINT FORMAT CONVERSION 105 2.6.2 FLOATING-POINT TO FIXED-POINT FORMAT CONVERSION 106 2.6.3 FLOATING-POINT MULTIPLICATION 107 2.6.4 FLOATING-POINT ADDITION 108 2.6.5 FLOATING-POINT DIVISION 110 2.6.6 FLOATING-POINT RECIPROCAL 112 2.6.7 FLOATING-POINT SYNTHESIS RESULTS 114 2.7 MULTIPLY-ACCUMULATOR (MAC) AND SUM OF PRODUCT (SOP) . 114 2.7.1 DISTRIBUTED ARITHMETIC FUNDAMENTALS 115 2.7.2 SIGNED DA SYSTEMS 118 2.7.3 MODIFIED DA SOLUTIONS 120 2.8 COMPUTATION OF SPECIAL FUNCTIONS USING CORDIC 120 2.8.1 CORDIC ARCHITECTURES 125 2.9 COMPUTATION OF SPECIAL FUNCTIONS USING MAC CALLS 130 2.9.1 CHEBYSHEV APPROXIMATIONS 131 2.9.2 TRIGONOMETRIC FUNCTION APPROXIMATION 132 2.9.3 EXPONENTIAL AND LOGARITHMIC FUNCTION APPROXIMATION 141 2.9.4 SQUARE ROOT FUNCTION APPROXIMATION 148 EXERCISES 154 3. FINITE IMPULSE RESPONSE (FIR) DIGITAL FILTERS 165 3.1 DIGITAL FILTERS 165 3.2 FIR THEORY 166 3.2.1 FIR FILTER WITH TRANSPOSED STRUCTURE 167 3.2.2 SYMMETRY IN FIR FILTERS 170 3.2.3 LINEAR-PHASE FIR FILTERS 171 3.3 DESIGNING FIR FILTERS 172 3.3.1 DIRECT WINDOW DESIGN METHOD 173 3.3.2 EQUIRIPPLE DESIGN METHOD 175 3.4 CONSTANT COEFFICIENT FIR DESIGN 177 3.4.1 DIRECT FIR DESIGN 178 3.4.2 FIR FILTER WITH TRANSPOSED STRUCTURE 182 3.4.3 FIR FILTERS USING DISTRIBUTED ARITHMETIC 189 3.4.4 IP CORE FIR FILTER DESIGN F. 204 3.4.5 COMPARISON OF DA- AND RAG-BASED FIR FILTERS 207 EXERCISES 209 4. INFINITE IMPULSE RESPONSE (IIR) DIGITAL FILTERS 215 4.1 IIR THEORY 218 4.2 IIR COEFFICIENT COMPUTATION 221 4.2.1 SUMMARY OF IMPORTANT IIR DESIGN ATTRIBUTES 223 4.3 IIR FILTER IMPLEMENTATION 224 CONTENTS XVII 4.3.1 FINITE WORDLENGTH EFFECTS 228 4.3.2 OPTIMIZATION OF THE FILTER GAIN FACTOR 229 4.4 FAST IIR FILTER , 230 4.4.1 TIME-DOMAIN INTERLEAVING 230 4.4.2 CLUSTERED AND SCATTERED LOOK-AHEAD PIPELINING 233 4.4.3 IIR DECIMATOR DESIGN 235 4.4.4 PARALLEL PROCESSING 236 4.4.5 IIR DESIGN USING RNS 239 EXERCISES 240 5. MULTIRATE SIGNAL PROCESSING 245 5.1 DECIMATION AND INTERPOLATION 245 5.1.1 NOBLE IDENTITIES 246 5.1.2 SAMPLING RATE CONVERSION BY RATIONAL FACTOR 248 5.2 POLYPHASE DECOMPOSITION 249 5.2.1 RECURSIVE IIR DECIMATOR 254 5.2.2 FAST-RUNNING FIR FILTER 254 5.3 HOGENAUER CIC FILTERS 256 5.3.1 SINGLE-STAGE CIC CASE STUDY 257 5.3.2 MULTISTAGE CIC FILTER THEORY 259 5.3.3 AMPLITUDE AND ALIASING DISTORTION 264 5.3.4 HOGENAUER PRUNING THEORY 266 5.3.5 CIC RNS DESIGN 272 5.4 MULTISTAGE DECIMATOR 273 5.4.1 MULTISTAGE DECIMATOR DESIGN USING GOODMAN-CAREY HALF-BAND FILTERS 274 5.5 FREQUENCY-SAMPLING FILTERS AS BANDPASS DECIMATORS 277 5.6 DESIGN OF ARBITRARY SAMPLING RATE CONVERTERS 280 5.6.1 FRACTIONAL DELAY RATE CHANGE 284 5.6.2 POLYNOMIAL FRACTIONAL DELAY DESIGN 290 5.6.3 B-SPLINE-BASED FRACTIONAL RATE CHANGER 296 5.6.4 MOMS FRACTIONAL RATE CHANGER 301 5.7 FILTER BANKS 308 5.7.1 UNIFORM DFT FILTER BANK 309 5.7.2 TWO-CHANNEL FILTER BANKS 313 5.8 WAVELETS 328 5.8.1 THE DISCRETE WAVELET TRANSFORMATION 332 EXERCISES 335 6. FOURIER TRANSFORMS 343 6.1 THE DISCRETE FOURIER TRANSFORM ALGORITHMS 344 6.1.1 FOURIER TRANSFORM APPROXIMATIONS USING THE DFT . 344 6.1.2 PROPERTIES OF THE DFT 346 6.1.3 THE GOERTZEL ALGORITHM 349 6.1.4 THE BLUESTEIN CHIRP-Z TRANSFORM 350 XVIII CONTENTS 6.1.5 THE RADER ALGORITHM 353 6.1.6 THE WINOGRAD DFT ALGORITHM 359 6.2 THE FAST FOURIER TRANSFORM (FFT) ALGORITHMS 361 6.2.1 THE COOLEY-TUKEY FFT ALGORITHM 363 6.2.2 THE GOOD-THOMAS FFT ALGORITHM 373 6.2.3 THE WINOGRAD FFT ALGORITHM 375 6.2.4 COMPARISON OF DFT AND FFT ALGORITHMS 379 6.2.5 IP CORE FFT DESIGN 381 6.3 FOURIER-RELATED TRANSFORMS 385 6.3.1 COMPUTING THE DCT USING THE DFT 387 6.3.2 FAST DIRECT DCT IMPLEMENTATION 388 EXERCISES 391 7. ADVANCED TOPICS 401 7.1 RECTANGULAR AND NUMBER THEORETIC TRANSFORMS (NTTS) 401 7.1.1 ARITHMETIC MODULO 2 B 1 403 7.1.2 EFFICIENT CONVOLUTIONS USING NTTS 405 7.1.3 FAST CONVOLUTION USING NTTS 405 7.1.4 MULTIDIMENSIONAL INDEX MAPS 409 7.1.5 COMPUTING THE DFT MATRIX WITH NTTS 411 7.1.6 INDEX MAPS FOR NTTS 413 7.1.7 USING RECTANGULAR TRANSFORMS TO COMPUTE THE DFT . 416 7.2 ERROR CONTROL AND CRYPTOGRAPHY 418 7.2.1 BASIC CONCEPTS FROM CODING THEORY 419 7.2.2 BLOCK CODES 424 7.2.3 CONVOLUTIONAL CODES 428 7.2.4 CRYPTOGRAPHY ALGORITHMS FOR FPGAS 436 7.3 MODULATION AND DEMODULATION 453 7.3.1 BASIC MODULATION CONCEPTS 453 7.3.2 INCOHERENT DEMODULATION 457 7.3.3 COHERENT DEMODULATION 463 EXERCISES 472 8. ADAPTIVE FILTERS 477 8.1 APPLICATION OF ADAPTIVE FILTER 478 8.1.1 INTERFERENCE CANCELLATION 478 8.1.2 PREDICTION » 479 8.1.3 INVERSE MODELING 479 8.1.4 IDENTIFICATION 480 8.2 OPTIMUM ESTIMATION TECHNIQUES 481 8.2.1 THE OPTIMUM WIENER ESTIMATION 482 8.3 THE WIDROW-HOFF LEAST MEAN SQUARE ALGORITHM 486 8.3.1 LEARNING CURVES 493 8.3.2 NORMALIZED LMS (NLMS) 496 8.4 TRANSFORM DOMAIN LMS ALGORITHMS 498 CONTENTS XIX 8.4.1 FAST-CONVOLUTION TECHNIQUES 498 8.4.2 USING ORTHOGONAL TRANSFORMS 500 8.5 IMPLEMENTATION OF THE LMS ALGORITHM 503 8.5.1 QUANTIZATION EFFECTS 504 8.5.2 FPGA DESIGN OF THE LMS ALGORITHM 504 8.5.3 PIPELINED LMS FILTERS 507 8.5.4 TRANSPOSED FORM LMS FILTER 510 8.5.5 DESIGN OF DLMS ALGORITHMS 511 8.5.6 LMS DESIGNS USING SIGNUM FUNCTION 515 8.6 RECURSIVE LEAST SQUARE ALGORITHMS 518 8.6.1 RLS WITH FINITE MEMORY 521 8.6.2 FAST RLS KALMAN IMPLEMENTATION 524 8.6.3 THE FAST A POSTERIORI KALMAN RLS ALGORITHM 529 8.7 COMPARISON OF LMS AND RLS PARAMETERS 530 EXERCISES 532 9. MICROPROCESSOR DESIGN 537 9.1 HISTORY OF MICROPROCESSORS 537 9.1.1 BRIEF HISTORY OF GENERAL-PURPOSE MICROPROCESSORS . 538 9.1.2 BRIEF HISTORY OF RISC MICROPROCESSORS 540 9.1.3 BRIEF HISTORY OF PDSPS 541 9.2 INSTRUCTION SET DESIGN 544 9.2.1 ADDRESSING MODES 544 9.2.2 DATA FLOW: ZERO-,ONE-, TWO- OR THREE-ADDRESS DESIGN 552 9.2.3 REGISTER FILE AND MEMORY ARCHITECTURE 558 9.2.4 OPERATION SUPPORT 562 9.2.5 NEXT OPERATION LOCATION 565 9.3 SOFTWARE TOOLS 566 9.3.1 LEXICAL ANALYSIS 567 9.3.2 PARSER DEVELOPMENT 578 9.4 FPGA MICROPROCESSOR CORES 588 9.4.1 HARDCORE MICROPROCESSORS 589 9.4.2 SOFTCORE MICROPROCESSORS 594 9.5 CASE STUDIES 605 9.5.1 T-RISC STACK MICROPROCESSORS 605 9.5.2 LISA WAVELET PROCESSOR DESIGN 610 9.5.3 NIOS FFT DESIGN T 625 EXERCISES 634 REFERENCES 645 A. VERILOG SOURCE CODE 2001 66 1 XX CONTENTS B. VHDL AND VERILOG CODING 729 B.I LIST OF EXAMPLES 731 B.2 LIBRARY OF PARAMETERIZED MODULES (LPM) 733 B.2.1 THE PARAMETERIZED FLIP-FLOP MEGAFUNCTION (LPM_FF) . 733 B.2.2 THE ADDER/SUBTRACTOR MEGAFUNCTION 737 B.2.3 THE PARAMETERIZED MULTIPLIER MEGAFUNCTION (LPM-MULT) 741 B.2.4 THE PARAMETERIZED ROM MEGAFUNCTION (LPM_ROM) . 746 B.2.5 THE PARAMETERIZED DIVIDER MEGAFUNCTION (LPM-DIVIDE) 749 B.2.6 THE PARAMETERIZED RAM MEGAFUNCTION (LPM_RAM_DQ) 751 C. GLOSSARY 755 D. CD-ROM FILE: "LREADME.PS" 761 INDEX 769
any_adam_object	1
any_adam_object_boolean	1
author	Meyer-Baese, Uwe 1964-
author_GND	(DE-588)14179514X
author_facet	Meyer-Baese, Uwe 1964-
author_role	aut
author_sort	Meyer-Baese, Uwe 1964-
author_variant	u m b umb
building	Verbundindex
bvnumber	BV023020936
callnumber-first	T - Technology
callnumber-label	TK5102
callnumber-raw	TK5102.9
callnumber-search	TK5102.9
callnumber-sort	TK 45102.9
callnumber-subject	TK - Electrical and Nuclear Engineering
classification_rvk	ZN 6040
classification_tum	ELT 517f
ctrlnum	(OCoLC)255668731 (DE-599)BVBBV023020936
dewey-full	620
dewey-hundreds	600 - Technology (Applied sciences)
dewey-ones	620 - Engineering and allied operations
dewey-raw	620
dewey-search	620
dewey-sort	3620
dewey-tens	620 - Engineering and allied operations
discipline	Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik
discipline_str_mv	Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik
edition	3. ed.
format	Book
fullrecord	<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>00000nam a2200000zc 4500</leader><controlfield tag="001">BV023020936</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20090602</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">071126s2007 gw d\|\|\| \|\|\|\| 00\|\|\| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9783540726128</subfield><subfield code="c">alk. paper</subfield><subfield code="9">978-3-540-72612-8</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)255668731</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV023020936</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="044" ind1=" " ind2=" "><subfield code="a">gw</subfield><subfield code="c">DE</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-706</subfield><subfield code="a">DE-859</subfield><subfield code="a">DE-92</subfield><subfield code="a">DE-91</subfield><subfield code="a">DE-523</subfield><subfield code="a">DE-634</subfield><subfield code="a">DE-83</subfield><subfield code="a">DE-B768</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK5102.9</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">620</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 6040</subfield><subfield code="0">(DE-625)157496:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ELT 517f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Meyer-Baese, Uwe</subfield><subfield code="d">1964-</subfield><subfield code="e">Verfasser</subfield><subfield code="0">(DE-588)14179514X</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Digital signal processing with field programmable gate arrays</subfield><subfield code="b">with ... 98 tables</subfield><subfield code="c">Uwe Meyer-Baese</subfield></datafield><datafield tag="250" ind1=" " ind2=" "><subfield code="a">3. ed.</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Berlin [u.a.]</subfield><subfield code="b">Springer</subfield><subfield code="c">2007</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XX, 774 S.</subfield><subfield code="b">graph. Darst.</subfield><subfield code="e">1 CD-ROM (12 cm)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="0" ind2=" "><subfield code="a">Signals and communication technology</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Includes bibliographical references (p. [423]-434) and index</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Digitale Signalverarbeitung - Field programmable gate array - Lehrbuch</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">aSignal processing</subfield><subfield code="a">xDigital techniques</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">aField programmable gate arrays</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Field programmable gate array</subfield><subfield code="0">(DE-588)4347749-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Digitale Signalverarbeitung</subfield><subfield code="0">(DE-588)4113314-6</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="0">(DE-588)4123623-3</subfield><subfield code="a">Lehrbuch</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Digitale Signalverarbeitung</subfield><subfield code="0">(DE-588)4113314-6</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Field programmable gate array</subfield><subfield code="0">(DE-588)4347749-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="856" ind1="4" ind2=" "><subfield code="u">http://deposit.dnb.de/cgi-bin/dokserv?id=2944556&prov=M&dok_var=1&dok_ext=htm</subfield><subfield code="3">Beschreibung für Leser</subfield></datafield><datafield tag="856" ind1="4" ind2=" "><subfield code="u">http://www.ulb.tu-darmstadt.de/tocs/193884038.pdf</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">HEBIS Datenaustausch Darmstadt</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016224997&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-016224997</subfield></datafield></record></collection>
genre	(DE-588)4123623-3 Lehrbuch gnd-content
genre_facet	Lehrbuch
id	DE-604.BV023020936
illustrated	Illustrated
index_date	2024-07-02T19:13:07Z
indexdate	2024-07-20T09:27:43Z
institution	BVB
isbn	9783540726128
language	English
oai_aleph_id	oai:aleph.bib-bvb.de:BVB01-016224997
oclc_num	255668731
open_access_boolean
owner	DE-706 DE-859 DE-92 DE-91 DE-BY-TUM DE-523 DE-634 DE-83 DE-B768
owner_facet	DE-706 DE-859 DE-92 DE-91 DE-BY-TUM DE-523 DE-634 DE-83 DE-B768
physical	XX, 774 S. graph. Darst. 1 CD-ROM (12 cm)
publishDate	2007
publishDateSearch	2007
publishDateSort	2007
publisher	Springer
record_format	marc
series2	Signals and communication technology
spelling	Meyer-Baese, Uwe 1964- Verfasser (DE-588)14179514X aut Digital signal processing with field programmable gate arrays with ... 98 tables Uwe Meyer-Baese 3. ed. Berlin [u.a.] Springer 2007 XX, 774 S. graph. Darst. 1 CD-ROM (12 cm) txt rdacontent n rdamedia nc rdacarrier Signals and communication technology Includes bibliographical references (p. [423]-434) and index Digitale Signalverarbeitung - Field programmable gate array - Lehrbuch aSignal processing xDigital techniques aField programmable gate arrays Field programmable gate array (DE-588)4347749-5 gnd rswk-swf Digitale Signalverarbeitung (DE-588)4113314-6 gnd rswk-swf (DE-588)4123623-3 Lehrbuch gnd-content Digitale Signalverarbeitung (DE-588)4113314-6 s Field programmable gate array (DE-588)4347749-5 s DE-604 http://deposit.dnb.de/cgi-bin/dokserv?id=2944556&prov=M&dok_var=1&dok_ext=htm Beschreibung für Leser http://www.ulb.tu-darmstadt.de/tocs/193884038.pdf Inhaltsverzeichnis HEBIS Datenaustausch Darmstadt application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016224997&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis
spellingShingle	Meyer-Baese, Uwe 1964- Digital signal processing with field programmable gate arrays with ... 98 tables Digitale Signalverarbeitung - Field programmable gate array - Lehrbuch aSignal processing xDigital techniques aField programmable gate arrays Field programmable gate array (DE-588)4347749-5 gnd Digitale Signalverarbeitung (DE-588)4113314-6 gnd
subject_GND	(DE-588)4347749-5 (DE-588)4113314-6 (DE-588)4123623-3
title	Digital signal processing with field programmable gate arrays with ... 98 tables
title_auth	Digital signal processing with field programmable gate arrays with ... 98 tables
title_exact_search	Digital signal processing with field programmable gate arrays with ... 98 tables
title_exact_search_txtP	Digital signal processing with field programmable gate arrays with ... 98 tables
title_full	Digital signal processing with field programmable gate arrays with ... 98 tables Uwe Meyer-Baese
title_fullStr	Digital signal processing with field programmable gate arrays with ... 98 tables Uwe Meyer-Baese
title_full_unstemmed	Digital signal processing with field programmable gate arrays with ... 98 tables Uwe Meyer-Baese
title_short	Digital signal processing with field programmable gate arrays
title_sort	digital signal processing with field programmable gate arrays with 98 tables
title_sub	with ... 98 tables
topic	Digitale Signalverarbeitung - Field programmable gate array - Lehrbuch aSignal processing xDigital techniques aField programmable gate arrays Field programmable gate array (DE-588)4347749-5 gnd Digitale Signalverarbeitung (DE-588)4113314-6 gnd
topic_facet	Digitale Signalverarbeitung - Field programmable gate array - Lehrbuch aSignal processing xDigital techniques aField programmable gate arrays Field programmable gate array Digitale Signalverarbeitung Lehrbuch
url	http://deposit.dnb.de/cgi-bin/dokserv?id=2944556&prov=M&dok_var=1&dok_ext=htm http://www.ulb.tu-darmstadt.de/tocs/193884038.pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016224997&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
work_keys_str_mv	AT meyerbaeseuwe digitalsignalprocessingwithfieldprogrammablegatearrayswith98tables

Holdings

There is no print copy available.

Interlibrary loan Place Request Caution: Not in THWS collection! Indexes
Indexes

MARC

Record in the Search Index

There is no print copy available.

Similar Items