Microelectronic circuit design:
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
New York, NY
McGraw-Hill
2008
|
| Ausgabe: | 3. ed., internat. ed. |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis Inhaltsverzeichnis |
| Beschreibung: | Includes index |
| Beschreibung: | XXIV, 1190 S. Ill., graph. Darst. |
| ISBN: | 9780071102032 0071102035 |
Internformat
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| 100 | 1 | |a Jaeger, Richard C. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Microelectronic circuit design |c Richard C. Jaeger ; Travis N. Blalock |
| 250 | |a 3. ed., internat. ed. | ||
| 264 | 1 | |a New York, NY |b McGraw-Hill |c 2008 | |
| 300 | |a XXIV, 1190 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 500 | |a Includes index | ||
| 650 | 4 | |a Circuits intégrés - Conception et construction | |
| 650 | 7 | |a Circuits intégrés numériques - Conception et construction |2 ram | |
| 650 | 4 | |a Circuits électroniques - Calcul - Manuels d'enseignement supérieur | |
| 650 | 4 | |a Elektronik devre tasarımı | |
| 650 | 4 | |a Entegre devreler - Tasarım ve yapım | |
| 650 | 4 | |a Semiconducteurs - Conception et construction | |
| 650 | 4 | |a Yarı iletkenler - Tasarım ve yapım | |
| 650 | 4 | |a Électronique de l'état solide | |
| 650 | 4 | |a Électronique numérique | |
| 650 | 4 | |a Electronic circuit design | |
| 650 | 4 | |a Integrated circuits |x Design and construction | |
| 650 | 4 | |a Semiconductors |x Design and construction | |
| 650 | 0 | 7 | |a Logische Schaltung |0 (DE-588)4131023-8 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Entwurf |0 (DE-588)4121208-3 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Elektronische Schaltung |0 (DE-588)4113419-9 |2 gnd |9 rswk-swf |
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| 700 | 1 | |a Blalock, Travis N. |e Verfasser |4 aut | |
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Datensatz im Suchindex
| _version_ | 1804136725283340288 |
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| adam_text | THIRD EDITION CIRCUIT DESIGN * . * :, . ME GRAW HILL HIGHER EDUCATION
BOSTON BURR RIDGE, IL DUBUQUE, IA NEW YORK SAN FRANCISCO ST. LOUIS
BANGKOK BOGOTA CARACAS KUALA LUMPUR LISBON LONDON MADRID MEXICO CITY
MILAN MONTREAL NEW DELHI SANTIAGO SEOUL SINGAPORE SYDNEY TAIPEI TORONTO
CONTENTS PREFACE XIX PART ON E SOLID STATE ELECTRONIC AND DEVICES
CHAPTER 1 INTRODUCTION TO ELECTRONICS 3 1.1 A BRIEF HISTORY OF
ELECTRONICS: FROM VACUUM TUBES TO ULTRA-LARGE-SCALE INTEGRATION 5 1.2
CLASSIFICATION OF ELECTRONIC SIGNALS 8 1.2.1 DIGITAL SIGNALS 9 1.2.2
ANALOG SIGNALS 9 1.2.3 A/D AND D/A CONVERTERS- BRIDGING THE ANALOG AND
DIGITAL DOMAINS 10 1.3 NOTATIONAL CONVENTIONS 12 1.4 PROBLEM-SOLVING
APPROACH 13 1.5 IMPORTANT CONCEPTS FROM CIRCUIT THEORY 15 1.5.1 VOLTAGE
AND CURRENT DIVISION 15 1.5.2 THEVENIN AND NORTON CIRCUIT
REPRESENTATIONS 16 1.6 FREQUENCY SPECTRUM OF ELECTRONIC SIGNALS 21 1.7
AMPLIFIERS 22 1.7.1 IDEAL OPERATIONAL AMPLIFIERS 23 1.7.2 AMPLIFIER
FREQUENCY RESPONSE 25 1.8 ELEMENT VARIATIONS IN CIRCUIT DESIGN 26 1.8.1
MATHEMATICAL MODELING OF TOLERANCES 26 1.8.2 WORST-CASE ANALYSIS 27
1.8.3 JIAONTE CARLO ANALYSIS 29 1.8.4 TEMPERATURE COEFFICIENTS 32 1.9
NUMERIC PRECISION 34 SUMMARY 34 KEY TERMS 35 REFERENCES 36 ADDITIONAL
READING 36 PROBLEMS 37 CHAPTER 2 SOLID-STATE ELECTRONICS 41 2.1
SOLID-STATE ELECTRONIC MATERIALS 43 2.2 COVALENT BOND MODEL 44 2.3 DRIFT
CURRENTS AND MOBILITY IN SEMICONDUCTORS 47 2.3.1 DRIFT CURRENTS 47 2.3.2
MOBILITY 48 2.3.3 VELOCITY SATURATION 48 2.4 RESISTIVITY OF INTRINSIC
SILICON 49 2.5 IMPURITIES IN SEMICONDUCTORS 50 2.5.1 DONOR IMPURITIES IN
SILICON 51 2.5.2 ACCEPTOR IMPURITIES IN SILICON 51 2.6 ELECTRON AND HOLE
CONCENTRATIONS IN DOPED SEMICONDUCTORS 51 2.6.1 N-TYPE MATERIAL (A/ D
N A ) 52 2.6.2 P-TYPE MATERIAL {N A N D ) 53 2.7 MOBILITY AND
RESISTIVITY IN DOPED SEMICONDUCTORS 54 2.8 DIFFUSION CURRENTS 58 2.9
TOTAL CURRENT 59 2.10 ENERGY BAND MODEL 60 2.10.1 ELECTRON-HOLE PAIR
GENERATION IN AN INTRINSIC SEMICONDUCTOR 60 2.10.2 ENERGY BAND MODEL FOR
A DOPED SEMICONDUCTOR 61 2.10.3 COMPENSATED SEMICONDUCTORS 61 2.11
OVERVIEW OF INTEGRATED CIRCUIT FABRICATION 63 SUMMARY 66 KEY TERMS 67
REFERENCE 68 ADDITIONAL READING 68 IMPORTANT EQUATIONS 68 PROBLEMS 69
CHAPTER 3 SOLID-STATE DIODES AND DIODE CIRCUITS 73 3.1 THE PN JUNCTION
DIODE 74 3.1.1 PN JUNCTION ELECTROSTATICS 74 3.1.2 INTERNAL DIODE
CURRENTS 78 VII VIII CONTENTS 3.2 THE /-V CHARACTERISTICS OF THE DIODE
79 3.3 THE DIODE EQUATION: A MATHEMATICAL MODEL FOR THE DIODE 81 3.4
DIODE CHARACTERISTICS UNDER REVERSE, ZERO, AND FORWARD BIAS 84 3.4.1
REVERSE BIAS 84 3.4.2 ZERO BIAS 84 3.4.3 FORWARD BIAS 85 3.5 DIODE
TEMPERATURE COEFFICIENT 88 3.6 DIODES UNDER REVERSE BIAS 88 3.6.1
SATURATION CURRENT IN REAL DIODES 89 3.6.2 REVERSE BREAKDOWN 90 3.6.3
DIODE MODEL FOR THE BREAKDOWN REGION 91 3.7 PN JUNCTION CAPACITANCE 91
3.7.1 REVERSE BIAS 91 3.7.2 FORWARD BIAS 92 3.8 SCHOTTKY BARRIER DIODE
92 3.9 DIODE SPICE MODEL AND LAYOUT 93 3.10 DIODE CIRCUIT ANALYSIS 95
3.10.1 LOAD-LINE ANALYSIS 95 3.10.2 ANALYSIS USING THE MATHEMATICAL
MODEL FOR THE DIODE 97 3.10.3 THE IDEAL DIODE MODEL 101 3.10.4 CONSTANT
VOLTAGE DROP MODEL 103 3.10.5 MODEL COMPARISON AND DISCUSSION 104 3.11
MULTIPLE-DIODE CIRCUITS 105 3.12 ANALYSIS OF DIODES OPERATING IN THE
BREAKDOWN REGION 108 3.12.1 LOAD-LINE ANALYSIS 108 3.12.2 ANALYSIS WITH
THE PIECEWISE LINEAR MODEL 109 3.12.3 VOLTAGE REGULATION 109 3.12.4
ANALYSIS INCLUDING ZENER RESISTANCE 110 3.12.5 LINE AND LOAD REGULATION
111 3.13 HALF-WAVE RECTIFIER CIRCUITS 112 3.13.1 HALF-WAVE RECTIFIER
WITH RESISTOR LOAD 112 3.13.2 RECTIFIER FILTER CAPACITOR 114 3.13.3
HALF-WAVE RECTIFIER WITH RC LOAD 114 3.13.4 RIPPLE VOLTAGE AND
CONDUCTION INTERVAL 115 3.13.5 DIODE CURRENT 118 3.13.6 SURGE CURRENT
119 3.13.7 PEAK-LNVERSE-VO LTAGE (PIV) RATING 119 3.13.8 DIODE POWER
DISSIPATION 120 3.13.9 HALF-WAVE RECTIFIER WITH NEGATIVE OUTPUT VOLTAGE
120 &14 FULL-WAVE RECTIFIER CIRCUITS 121 3.14.1 FULL-WAVE RECTIFIER WITH
NEGATIVE,-^-I OUTPUT VOLTAGE 122 FE 3.15 FULL-WAVE BRIDGE RECTIFICATION
122 3.16 RECTIFIER COMPARISON AND DESIGN TRADEOFFS 123 3.17 DYNAMIC
SWITCHING BEHAVIOR OF THE DIODE 127 3.18 PHOTO DIODES, SOLAR CELLS, AND
LIGHT-EMITTING DIODES 128 3.18.1 PHOTO DIODES AND PHOTODETECTORS 128
3.18.2 POWER GENERATION FROM SOLAR CELLS 129 3.18.3 LIGHT-EMITTING
DIODES (LEDS) 130 SUMMARY 131 KEY TERMS 132 REFERENCE 133 ADDITIONAL
READING 133 PROBLEMS 133 CHAPTER 4 FIELD-EFFECT TRANSISTORS 143 4.1
CHARACTERISTICS OF THE MOS CAPACITOR 144 4.1.1 ACCUMULATION REGION 145
4.1.2 DEPLETION REGION 146 4.1.3 INVERSION REGION 146 4.2 THE NMOS
TRANSISTOR 146 4.2.1 QUALITATIVE I-V BEHAVIOR OF THE NMOS TRANSISTOR 147
4.2.2 TRIODE 1 REGION CHARACTERISTICS OF THE NMOS TRANSISTOR 148 4.2.3
ON RESISTANCE 151 4.2.4 SATURATION OF THE I-V CHARACTERISTICS 152 4.2.5
MATHEMATICAL MODEL IN THE SATURATION (PINCH-OFF) REGION 153 4.2.6
TRANSCONDUCTANCE 155 4.2.7 CHANNEL-LENGTH MODULATION 155 4.2.8 TRANSFER
CHARACTERISTICS AND DEPLETION-MODE MOSFETS 156 4.2.9 BODY EFFECT OR
SUBSTRATE SENSITIVITY 157 4.3 PMOS TRANSISTORS 159 4.4 MOSFET CIRCUIT
SYMBOLS 160 4.5 MOS TRANSISTOR FABRICATION AND LAYOUT DESIGN RULES 2 163
4.5.1 MINIMUM FEATURE SIZE AND ALIGNMENT TOLERANCE 163 4.5.2 MOS
TRANSISTOR LAYOUT 164 4.6 CAPACITANCES IN MOS TRANSISTORS 165 4.6.1 NMOS
TRANSISTOR CAPACITANCES IN THE TRIODE REGION 166 4.6.2 CAPACITANCES IN
THE SATURATION W REGION 167 4.6.3 CAPACITANCES IN CUTOFF 167 CONTENTS IX
4.7 MOSFET MODELING IN SPICE 167 4.8 BIASING THE NMOS FIELD-EFFECT
TRANSISTOR 169 4.8.1 WHY DO WE NEED BIAS? 169 4.9 BIASING THE PMOS
FIELD-EFFECT TRANSISTOR 187 4.10 MOS TRANSISTOR SCALING 189 4.10.1 DRAIN
CURRENT 189 4.10.2 GATE CAPACITANCE 191 4.10.3 CIRCUIT AND POWER
DENSITIES 191 4.10.4 POWER-DELAY PRODUCT 191 4.10.5 CUTOFF FREQUENCY 192
4.10.6 HIGH FIELD LIMITATIONS 192 4.10.7 SUBTHRESHOLD CONDUCTION 193
SUMMARY 194 KEY TERMS 195 REFERENCES 196 PROBLEMS 197 CHAPTER 5 BIPOLAR
JUNCTION TRANSISTORS 207 5.1 PHYSICAL STRUCTURE OF THE BIPOLAR
TRANSISTOR 208 5.2 THE TRANSPORT MODEL FOR THE NPN TRANSISTOR 209 5.2.1
FORWARD CHARACTERISTICS 210 5.2.2 REVERSE CHARACTERISTICS 212 5.2.3 THE
COMPLETE TRANSPORT MODEL EQUATIONS FOR ARBITRARY BIAS CONDITIONS 213 5.3
THE PNP TRANSISTOR 215 5.4 EQUIVALENT CIRCUIT REPRESENTATIONS FOR THE
TRANSPORT MODELS 217 5.5 THE I-V CHARACTERISTICS OF THE BIPOLAR
TRANSISTOR 218 5.5.1 OUTPUT CHARACTERISTICS 218 5.5.2 TRANSFER
CHARACTERISTICS 219 5.6 THE OPERATING REGIONS OF THE BIPOLAR TRANSISTOR
220 5.7 TRANSPORT MODEL SIMPLIFICATIONS 221 5.7.1 SIMPLIFIED MODEL FOR
THE CUTOFF REGION 221 5.7.2 MODEL SIMPLIFICATIONS FOR THE FORWARD-ACTIVE
REGION 223 5.7.3 DIODES IN BIPOLAR INTEGRATED /CIRCUITS 229 5.7.4
SIMPLIFIED MODEL FOR THE REVERSE-ACTIVE REGION 230 5.7.5 MODELING
OPERATION IN THE SATURATION REGION 232 5.8 NONIDEAL BEHAVIOR OF THE
BIPOLAR TRANSISTOR 235 - 5.8.1 JUNCTION BREAKDOW^ VTT^ES 236 5.8.2
MINORITY-CARRIER TRANSPORT IN THE BASE REGION 236 5.8.3 BASE TRANSIT
TIME 237 5.8.4 DIFFUSION CAPACITANCE 239 5.8.5 FREQUENCY DEPENDENCE OF
THE COMMON-EMITTER CURRENT GAIN 240 5.8.6 THE EARLY EFFECT AND EARLY
VOLTAGE 240 5.8.7 MODELING THE EARLY EFFECT 241 5.8.8 ORIGIN OF THE
EARLY EFFECT 241 5.9 TRANSCONDUCTANCE 242 5.10 BIPOLAR TECHNOLOGY AND
SPICE MODEL 243 5.10.1 QUALITATIVE DESCRIPTION 243 5.10.2 SPICE MODEL
EQUATIONS 244 5.10.3 HIGH-PERFORMANCE BIPOLAR TRANSISTORS 245 5.11
PRACTICAL BIAS CIRCUITS FOR THE BJT 246 5.11.1 FOUR-RESISTOR BIAS
NETWORK 248 5.11.2 DESIGN OBJECTIVES FOR THE FOUR-RESISTOR BIAS NETWORK
249 5.12 TOLERANCES IN BIAS CIRCUITS 254 5.12.1 WORST-CASE ANALYSIS 255
5.12.2 MONTE CARLO ANALYSIS 257 SUMMARY 260 KEY TERMS 262 REFERENCES 262
PROBLEMS 263 PART TWO DIGITAL ELECTRONICS CHAPTER 6 INTRODUCTION TO
DIGITAL ELECTRONICS 275 6.1 IDEAL LOGIC GATES 277 6.2 LOGIC LEVEL
DEFINITIONS AND NOISE MARGINS 277 6.2.1 LOGIC VOLTAGE LEVELS 279 6.2.2
NEISE MARGINS 279 6.2.3 LOGIC GATE DESIGN GOALS 280 6.3 DYNAMIC RESPONSE
OF LOGIC GATES 281 6.3.1 RISE TIME AND FALL TIMES 281 6.3.2 PROPAGATION
DELAY 282 6.3.3 POWER-DELAY PRODUCT 282 6.4 REVIEW OF BOOLEAN ALGEBRA
283 6.5 NMOS LOGIC DESIGN 285 6.5.1 NMOS INVERTER WITH RESISTIVE LOAD
286 6.5.2 DESIGN OF THE W/L RATIO OF M S 287 6.5.3 LOAD RESISTOR DESIGN
288 6.5.4 LOAD-LINE VISUALIZATION 288 6.5.5 ON-RESISTANCE OF THE
SWITCHING DEVICE 290 CONTENTS 6.5.6 NOISE MARGIN ANALYSIS 291 6.5.7
CALCULATION OF V, L AND V O H 291 6.5.8 CALCULATION OF V TH AND V 0L 292
6.5.9 LOAD RESISTOR PROBLEMS 293 6.6 TRANSISTOR ALTERNATIVES TO THE LOAD
RESISTOR 294 6.6.1 THE NMOS SATURATED LOAD INVERTER 295 6.6.2 NMOS
INVERTER WITH A LINEAR LOAD DEVICE 303 6.6.3 NMOS INVERTER WITH A
DEPLETION-MODE LOAD 304 6.6.4 STATIC DESIGN OF THE PSEUDO NMOS INVERTER
307 6.7 NMOS INVERTER SUMMARY AND COMPARISON 311 6.8 NMOS NAND AND NOR
GATES 312 6.8.1 NOR GATES 313 6.8.2 NAND GATES 314 6.8.3 NOR AND NAND
GATE LAYOUTS IN NMOS DEPLETION-MODE TECHNOLOGY 315 6.9 COMPLEX NMOS
LOGIC DESIGN 316 6.9.1 SELECTING BETWEEN THE TWO DESIGNS 319 6.10 POWER
DISSIPATION 321 6.10.1 STATIC POWER DISSIPATION 321 6.10.2 DYNAMIC POWER
DISSIPATION 322 6.10.3 POWER SCALING IN MOS LOGIC GATES 323 6.11 DYNAMIC
BEHAVIOR OF MOS LOGIC GATES 325 6.11.1 CAPACITANCES IN LOGIC CIRCUITS
325 6.11.2 DYNAMIC RESPONSE OF THE NMOS INVERTER WITH A RESISTIVE LOAD
326 6.11.3 PSEUDO NMOS INVERTER 331 6.11.4 A FINAL COMPARISON OF NMOS
INVERTER DELAYS 332 6.12 PMOS LOGIC 335 6.12.1 PMOS INVERTERS 335 6.12.2
NOR AND NAND GATES 338 SUMMARY 338 KEY TERMS 340 REFERENCES 341
ADDITIONAL READING 341 PROBLEMS 341 CHAPTER 7 /* COMPLEMENTARY MOS
(CMOS) LOGIC DESIGN 352 7.1 CMOS INVERTER TECHNOLOGY 353 7.1.1 CMOS
INVERTER LAYOUT 355 7.2 STATIC CHARACTERISTICS OF THE CMOS INVERTER 355
7.2.1 CMOS VOLTAGE TRANSFER CHARACTERISTICS 356 7.2.2 NOISE MARGINS FOR
THE CMOS INVERTER 358 7.3 DYNAMIC BEHAVIOR OF THE CMOS INVERTER 360
7.3.1 PROPAGATION DELAY ESTIMATE 360 7.3.2 RISE AND FALL TIMES 362 7.3.3
DELAY OF CASCADED INVERTERS 364 7.4 POWER DISSIPATION AND POWER DELAY
PRODUCT IN CMOS 365 7.4.1 STATIC POWER DISSIPATION 365 7.4.2 DYNAMIC
POWER DISSIPATION 365 7.4.3 POWER-DELAY PRODUCT 366 7.5 CMOS NOR AND
NAND GATES 367 7.5.1 CMOS NOR GATE 367 7.5.2 CMOS NAND GATES 370 7.6
DESIGN OF COMPLEX GATES IN CMOS 372 7.7 MINIMUM SIZE GATE DESIGN AND
PERFORMANCE 376 7.8 DYNAMIC DOMINO CMOS LOGIC 379 7.9 CASCADE BUFFERS
380 7.9.1 CASCADE BUFFER DELAY MODEL 381 7.9.2 OPTIMUM NUMBER OF STAGES
381 7.10 THE CMOS TRANSMISSION GATE 384 7.11 CMOSLATCHUP 384 SUMMARY 387
KEY TERMS 388 REFERENCES 389 PROBLEMS 389 CHAPTER 8 MOS MEMORY AND
STORAGE CIRCUITS 398 8.1 RANDOM ACCESS MEMORY 399 8.1.1 RANDOM ACCESS
MEMORY (RAM) ARCHITECTURE 399 8.1.2 A 256-MB MEMORY CHIP 400 8.2 STATIC
MEMORY CELLS 401 8.2.1 MEMORY CELL ISOLATION AND ACCESS-THE6-TCELL 402
8.2.2 THE READ OPERATION 403 8.2.3 WRITING DATA INTO THE 6-T CELL 406
8.3 DYNAMIC MEMORY CELLS 408 8.3.1 THE ONE-TRANSISTOR CELL 410 8.3.2
DATA STORAGE IN THE I-T CELL 410 8.3.3 READING DATA FROM THE I-T CELL
412 8.3.4 THE FOUR-TRANSISTOR CELL 413 8.4 SENSE AMPLIFIERS 414 8.4.1 A
SENSE AMPLIFIER FOR THE 6-T CELL 414 8.4.2 A SENSE AMPLIFIER FOR THE I-T
CELL 416 8.4.3 THE BOOSTED WORDLINE CIRCUIT 418 8.4.4 CLOCKED CMOS SENSE
AMPLIFIERS 418 CONTENTS XI 8.5 ADDRESS DECODERS 420 8.5.1 NOR DECODER
420 8.5.2 NAND DECODER 420 8.5.3 DECODERS IN DOMINO CMOS LOGIC 422 8.5.4
PASS-TRANSISTOR COLUMN DECODER 422 8.6 READ-ONLY MEMORY (ROM) 424 8.7
FLIP-FLOPS 427 8.7.1 RS FLIP-FLOP 429 8.7.2 THE D-LATCH USING
TRANSMISSION GATES 430 8.7.3 A MASTER-SLAVE D FLIP-FLOP 430 SUMMARY 431
KEY TERMS 432 REFERENCES 432 PROBLEMS 433 CHAPTER 9 BIPOLAR LOGIC
CIRCUITS 440 9.1 THE CURRENT SWITCH (EMITTER-COUPLED PAIR) 441 9.1.1
MATHEMATICAL MODEL FOR STATIC BEHAVIOR OF THE CURRENT SWITCH 442 9.1.2
CURRENT SWITCH ANALYSIS FOR V, V REF 443 9.1.3 CURRENT SWITCH ANALYSIS
FOR VI L/ RE F 444 9.2 THE EMITTER-COUPLED LOGIC (ECL) GATE 444 9.2.1
ECL GATE WITH V, = V H 445 9.2.2 ECL GATE WITH V, - V L 446 9.2.3 INPUT
CURRENT OF THE ECL GATE 446 9.2.4 ECL SUMMARY 446 9.3 NOISE MARGIN
ANALYSIS FOR THE ECL GATE 447 9.3.1 V IL ,V 0 H,V IHF ANDV 0 L 447 9.3.2
NOISE MARGINS 448 9.4 CURRENT SOURCE IMPLEMENTATION 449 9.5 THE ECL
OR-NOR GATE 451 9.6 THE EMITTER FOLLOWER 453 9.6.1 EMITTER FOLLOWER WITH
A LOAD RESISTOR 454 9.7 EMITTER DOTTING OR WIRED-OR LOGIC 456 9.7.1
PARALLEL CONNECTION OF EMITTER-FOLLOWER OUTPUTS 457 9.7.2 THE WIRED-OR
LOGIC FUNCTION 457 9.8 ECL POJ/VER-DELAY CHARACTERISTICS 457 9.8.1 POWER
DISSIPATION 467 9.8.2 GATE DELAY 459 9.8.3 POWER-DELAY PRODUCT 489 9.9
THE SATURATING BIPOLAR INVEFJTEF 4#1 9.9.1 STATIC INVERTER
CHARACTERISTICS 464 9.9.2 SATURATION VOLTAGE OF THE BIPOLAR TRANSISTOR
484 *.** $$!;-*& ;* * 9.9.3 LOAD-LINE VISUALIZATION 466 9.9.4 SWITCHING
CHARACTERISTICS OF THE SATURATED BJT 467 9.10 A TRANSISTOR-TRANSISTOR
LOGIC (TTL) PROTOTYPE 469 9.10.1 TTL INVERTER FOR V, = V L 470 9.10.2
TTL INVERTER FOR V, = V H 471 9.10.3 POWER IN THE PROTOTYPE TTL GATE 471
9.10.4 VIH, VIL, AND NOISE MARGINS FOR THE TTL PROTOTYPE 472 9.10.5
PROTOTYPE INVERTER SUMMARY 474 9.10.6 FANOUT LIMITATIONS OF THE TTL
PROTOTYPE 474 9.11 THE STANDARD 7400 SERIES TTL INVERTER 477 9.11.1
ANALYSIS FOR V, = V L 478 9.11.2 ANALYSIS FOR V, = V H 479 9.11.3 POWER
CONSUMPTION 480 9.11.4 TTL PROPAGATION DELAY AND POWER-DELAY PRODUCT 480
9.11.5 TTL VOLTAGE TRANSFER CHARACTERISTIC AND NOISE MARGINS 481 9.11.6
FANOUT LIMITATIONS OF STANDARD TTL 481 9.12 LOGIC FUNCTIONS IN TTL 482
9.12.1 MULTI-EMITTER INPUT TRANSISTORS 482 9.12.2 TTL NAND GATES 482
9.12.3 INPUT CLAMPING DIODES 483 9.13 SCHOTTKY-CLAMPED TTL 484 9.14
COMPARISON OF THE POWER-DELAY PRODUCTS OF ECL AND TTL 485 9.15 BICMOS
LOGIC 486 9.15.1 BICMOS BUFFERS 487 9.15.2 BINMOS INVERTERS 488 9.15.3
BICMOS LOGIC GATES 490 SUMMARY 491 KEY TERMS 492 REFERENCE 493
ADDITIONAL READING 493 PROBLEMS 493 PART THREE ANALOG CIRCUIT DESIGN
CHAPTER 10 ANALOG SYSTEMS 505 10.1 - AN EXAMPLE OF AN ANALOG ELECTRONIC
SYSTEM 506 10.2 AMPLIFICATION 507 10.2.1 VOLTAGE GAIN 508 10.2.2 CURRENT
GAIN 508 10.2.3 POWER GAIN 509 10.2.4 THE DECIBEL SCALE 509 XII CONTENTS
10.3 AMPLIFIER BIASING FOR LINEAR OPERATION 510 10.4 DISTORTION IN
AMPLIFIERS 512 10.5 TWD-PORT MODELS FOR AMPLIFIERS 513 10.5.1 THE
G-PARAMETERS 515 10.6 MISMATCHED SOURCE AND LOAD RESISTANCES 519 10.7
AMPLIFIER TRANSFER FUNCTIONS AND FREQUENCY RESPONSE 520 10.7.1 BODE
PLOTS 521 10.7.2 THE LOW-PASS AMPLIFIER 521 10.7.3 THE HIGH-PASS
AMPLIFIER 526 10.7.4 BAND-PASS AMPLIFIERS 528 10.7.5 NARROW-BAND OR
HIGH-Q BAND-PASS AMPLIFIERS 530 10.7.6 BAND-REJECTION AMPLIFIERS 531
10.7.7 THE ALL-PASS FUNCTION 532 10.7.8 MORE COMPLEX TRANSFER FUNCTIONS
532 SUMMARY 534 KEY TERMS 535 REFERENCES 536 PROBLEMS 536 CHAPTER 11
IDEAL OPERATIONAL AMPLIFIERS 541 11.1 THE DIFFERENTIAL AMPLIFIER 542
11.1.1 DIFFERENTIAL AMPLIFIER MODEL 542 11.1.2 THE IDEAL DIFFERENTIAL
AMPLIFIER 544 11.2 THE IDEAL OPERATIONAL AMPLIFIER 545 11.2.1
ASSUMPTIONS FOR IDEAL OPERATIONAL AMPLIFIER ANALYSIS 545 11.3 ANALYSIS
OF CIRCUITS CONTAINING IDEAL OPERATIONAL AMPLIFIERS 546 11.3.1 THE
INVERTING AMPLIFIER 546 11.3.2 THE NONINVERTING AMPLIFIER 550 11.3.3 THE
UNITY-GAIN BUFFER, OR VOLTAGE FOLLOWER 552 11.3.4 THE SUMMING AMPLIFIER
554 11.3.5 THE DIFFERENCE AMPLIFIER 556 11.3.6 THE INSTRUMENTATION
AMPLIFIER 559 11.3.7 AN ACTIVE LOW-PASS FILTER 561 11.3.8 THE INTEGRATOR
564 11.3.9 THE DIFFERENTIATOR 567 11.3.10 CASCADED AMPLIFIERS 568
11.3.11 AMPLIFIER TERMINOLOGY REVIEW 570 11.4 ACTIVE FILTERS 570 11.4.1
LOW-PASS FILTER 571 11.4.2 SENSITIVITY 575 11.4.3 A HIGH-PASS FILTER
WITH GAIN 575 11.4.4 BAND-PASS FILTER 577 11.4.5 THE TOW-THOMAS BIQUAD
579 11.4.6 MAGNITUDE AND FREQUENCY SCALING 582 11.5 NONLINEAR CIRCUIT
APPLICATIONS 584 11.5.1 A PRECISION HALF-WAVE RECTIFIER 585 11.5.2
NONSATURATING PRECISION-RECTIFIER CIRCUIT 586 11.5.3 AN AC VOLTMETER 587
11.6 CIRCUITS USING POSITIVE FEEDBACK 587 11.6.1 THE COMPARATOR AND
SCHMITT TRIGGER 588 11.6.2 THE ASTABLE MULTIVIBRATOR 589 11.6.3 THE
MONOSTABLE MULTIVIBRATOR OR ONE SHOT 593 SUMMARY 594 KEY TERMS 595
REFERENCES 596 ADDITIONAL READING 597 PROBLEMS 597 CHAPTER 12
CHARACTERISTICS AND LIMITATIONS OF OPERATIONAL AMPLIFIERS 610 12.1 GAIN,
INPUT RESISTANCE, AND OUTPUT RESISTANCE 611 12.1.1 FINITE OPEN-LOOP GAIN
611 12.1.2 GAIN ERROR 612 12.1.3 NONZERO OUTPUT RESISTANCE 614 12.1.4
FINITE INPUT RESISTANCE 618 12.1.5 SUMMARY OF NONIDEAL INVERTING AND
NONINVERFING AMPLIFIERS 622 12.2 COMMON-MODE REJECTION AND INPUT
RESISTANCE 622 12.2.1 FINITE COMMON-MODE REJECTION RATIO 622 12.2.2 WHY
IS CMRR IMPORTANT? 623 12.2.3 VOLTAGE-FOLLOWER GAIN ERROR DUE TO CMRR
626 12.2.4 COMMON-MODE INPUT RESISTANCE 628 12.3 DC ERROR SOURCES AND
OUTPUT RANGE LIMITATIONS 629 * 12.3.1 INPUT-OFFSET VOLTAGE 629 12.3.2
OFFSET-VOLTAGE ADJUSTMENT 631 12.3.3 AN ALTERNATE INTERPRETATION OF CMRR
631 12.3.4 INPUT-BIAS AND OFFSET CURRENTS 631 12.3.5 OUTPUT VOLTAGE AND
CURRENT LIMITS 634 12.4 FREQUENCY RESPONSE AND BANDWIDTH OF OPERATIONAL
AMPLIFIERS 638 12.4.1 FREQUENCY RESPONSE OF THE NONINVERTING AMPLIFIER
641 12.4.2 INVERTING AMPLIFIER FREQUENCY RESPONSE 643 12.4.3 FREQUENCY
RESPONSE OF CASCADED AMPLIFIERS 645 CONTENTS XIII 12.4.4 LARGE-SIGNAL
LIMITATIONS*SLEW RATE AND FULL-POWER BANDWIDTH 652 12.4.5 MACRO MODEL
FOR OPERATIONAL AMPLIFIER FREQUENCY RESPONSE 653 12.4.6 COMPLETE OP AMP
MACRO MODELS IN SPICE 654 12.4.7 EXAMPLES OF COMMERCIAL GENERAL-PURPOSE
OPERATIONAL AMPLIFIERS 654 SUMMARY 657 KEY TERMS 658 REFERENCES 658
ADDITIONAL READING 658 PROBLEMS 658 CHAPTER 13 SMALL-SIGNAL MODELING AND
LINEAR AMPLIFICATION*INVERTING AMPLIFIERS 668 13.1 THE TRANSISTOR AS AN
AMPLIFIER 669 13.1.1 THE BJT AMPLIFIER 670 13.1.2 THE MOSFET AMPLIFIER
671 13.2 COUPLING AND BYPASS CAPACITORS 672 13.3 CIRCUIT ANALYSIS USING
DC AND AC EQUIVALENT CIRCUITS 673 13.3.1 MENU FOR DC AND AC ANALYSIS 674
13.4 INTRODUCTION TO SMALL-SIGNAL MODELING 677 13.4.1 GRAPHICAL
INTERPRETATION OF THE SMALL-SIGNAL BEHAVIOR OF THE DIODE 678 13.4.2
SMALL-SIGNAL MODELING OF THE DIODE 679 13.5 SMALL-SIGNAL MODELS FOR
BIPOLAR JUNCTION TRANSISTORS 680 13.5.1 THE HYBRID-PI MODEL 682 13.5.2
GRAPHICAL INTERPRETATION OF THE TRANSCONDUCTANCE 683 13.5.3 SMALL-SIGNAL
CURRENT GAIN 683 13.5.4 THE INTRINSIC VOLTAGE GAIN OF THE BJT 684 13.5.5
EQUIVALENT FORMS OF THE SMALL-SIGNAL MODEL 685 13.5.6 SIMPLIFIED HYBRID
PI MODEL 686 13.5.7 DEFINITION OF A SMALL SIGNAL FOR THE BIPOLAR
TRANSISTOR 686 13.5.8 ^SMALL-SIGNAL MODEL FOR THE PNP TRANSISTOR 687
13.5.9 AC ANALYSIS VERSUS TRANSIENT ANALYSIS IN SPICE 688 13.6 THE BJT
COMMON-EMITTER (C-E) AMPLIFIER 688 13.6.1 TERMINAL VOLTAGE GAIRI 600
13.6.2 INPUT RESISTANCE $38 13.6.3 SIGNAL SOURCE VOTTA^#LN 691 13.7
IMPORTANT LIMITS AND MODEL SIMPLIFICATIONS 691 13.7.1 ZERO RESISTANCE IN
THE EMITTER 691 13.7.2 A DESIGN GUIDE FOR THE COMMON-EMITTER AMPLIFIER
WITH R E =O 692 13.7.3 COMMON-EMITTER VOLTAGE GAIN FOR LARGE EMITTER
RESISTANCE 693 13.7.4 SMALL-SIGNAL LIMIT FOR THE COMMON-EMITTER
AMPLIFIER 693 13.7.5 RESISTANCE AT THE COLLECTOR OF THE BIPOLAR
TRANSISTOR 697 13.7.6 OUTPUT RESISTANCE OF THE OVERALL COMMON-EMITTER
AMPLIFIER 699 13.7.7 TERMINAL CURRENT GAIN FOR THE COMMON-EMITTER
AMPLIFIER 701 13.8 SMALL-SIGNAL MODELS FOR FIELD-EFFECT TRANSISTORS 701
13.8.1 SMALL-SIGNAL MODEL FOR THE MOSFET 701 13.8.2 INTRINSIC VOLTAGE
GAIN OF THE MOSFET 703 13.8.3 DEFINITION OF SMALL-SIGNAL OPERATION FOR
THE MOSFET 704 13.8.4 BODY EFFECT IN THE FOUR-TERMINAL MOSFET 704 13.8.5
SMALL-SIGNAL MODEL FOR THE PMOS TRANSISTOR 705 13.9 SUMMARY AND
COMPARISON OF THE SMALL-SIGNAL MODELS OF THE BJT AND FET 706 13.10 THE
COMMON-SOURCE AMPLIFIER 709 13.10.1 COMMON-SOURCE TERMINAL VOLTAGE GAIN
710 13.10.2 SIGNAL SOURCE VOLTAGE GAIN FOR THE COMMON-SOURCE AMPLIFIER
711 13.10.3 COMMON-SOURCE VOLTAGE GAIN FOR LARGE VALUES OF R S 711
13.10.4 ZERO RESISTANCE IN THE SOURCE 711 13.10.5 A DESIGN GUIDE FOR THE
CO/NMON-SOURCE AMPLIFIER WITH R S - O 714 13.10.6 SMALL-SIGNAL LIMIT FOR
THE COMMON-SOURCE AMPLIFIER 714 13.10.7 INPUT RESISTANCES OF THE
COMMON-EMITTER AND COMMON-SOURCE AMPLIFIERS 717 13.10.8 COMMON-EMITTER
AND COMMON-SOURCE OUTPUT RESISTANCES 720 13.11 EXAMPLES OF
COMMON-EMITTER AND COMMON-SOURCE AMPLIFIERS 721 13.11.1 A COMMON-EMITTER
AMPLIFIER 722 13.11.2 AC VERSUS TRANSIENT ANALYSIS IN SPICE-ANOTHER
VISIT 726 XIV CONTENTS 13.11.3 A MOSFET COMMON-SOURCE AMPLIFIER 726
13.11.4 COMPARISON OF THE TWO AMPLIFIER EXAMPLES 731 13.11.5
COMMON-EMITTER AND COMMON-SOURCE AMPLIFIER SUMMARY 731 13.11.6 FEEDBACK
IN THE INVERTING AMPLIFIERS 732 13.11.7 GUIDELINES FOR NEGLECTING THE
TRANSISTOR OUTPUT RESISTANCE 732 13.12 AMPLIFIER POWER AND SIGNAL RANGE
733 13.12.1 POWER DISSIPATION 733 13.12.2 SIGNAL RANGE 734 SUMMARY 737
KEY TERMS 738 PROBLEMS 738 CHAPTER 14 SINGLE-TRANSISTOR AND MULTISTAGE
AC-COUPLED AMPLIFIERS 750 14.1 AMPLIFIER CLASSIFICATION 751 14.1.1
SIGNAL INJECTION AND EXTRACTION-THE BJT 751 14.1.2 SIGNAL INJECTION AND
EXTRACTION-THE FET 752 14.1.3 COMMON-EMITTER (C-E) AND COMMON-SOURCE
(C-S) AMPLIFIERS 753 14.1.4 COMMON-COLLECTOR (C-C) AND COMMON-DRAIN
(C-D) TOPOLOGIES 754 14.1.5 COMMON-BASE (C-B) AND COMMON-GATE (C-G)
AMPLIFIERS 756 14.1.6 SMALL-SIGNAL MODEL REVIEW 757 14.2 INVERTING
AMPLIFIERS*COMMON-EMITTER AND COMMON-SOURCE CIRCUITS 757 14.2.1
COMMON-EMITTER AND COMMON-SOURCE AMPLIFIER CHARACTERISTICS 758 14.2.2
C-E/C-S AMPLIFIER SUMMARY 762 14.2.3 EQUIVALENT TRANSISTOR
REPRESENTATION OF THE GENERALIZED C-E/C-S TRANSISTOR 762 14.3 FOLLOWER
CIRCUITS*COMMON-COLLECTOR AND COMMON-DRAIN AMPLIFIERS 763 14.3.1
TERMINAL VOLTAGE GAIN 763 14.3.2 RESISTANCE 764 14.3.3 SIGNAL SOURCE
VOLTAGE GAIN 764 14.3.4 FOLLOWER SIGNAL RANGE 767 14.3.5 RESISTANCE AT
THE EMITTER TERMINAL 767 14.3.6 CURRENT GAIN 770 14.3.7 C-C/C-D
AMPLIFIER SUMMARY 770 14.4 NONINVERTING AMPLIFIERS*COMMON-BASE AND
COMMON-GATE CIRCUITS 771 14.4.1 TERMINAL VOLTAGE GAIN AND INPUT
RESISTANCE 771 14.4.2 SIGNAL SOURCE VOLTAGE GAIN 772 14.4.3 INPUT SIGNAL
RANGE 773 14.4.4 RESISTANCE AT THE COLLECTOR AND DRAIN TERMINALS 774
14.4.5 CURRENT GAIN 775 14.4.6 OVERALL INPUT AND OUTPUT RESISTANCES FOR
THE NONINVERTING AMPLIFIERS 775 14.4.7 C-B/C-G AMPLIFIER SUMMARY 778
14.5 AMPLIFIER PROTOTYPE REVIEW AND COMPARISON 778 14.5.1 THE BJT
AMPLIFIERS 779 14.5.2 THE FET AMPLIFIERS 781 14.6 COUPLING AND BYPASS
CAPACITOR DESIGN 786 14.6.1 COMMON-EMITTER AND COMMON-SOURCE AMPLIFIERS
786 14.6.2 COMMON-COLLECTOR AND COMMON-DRAIN AMPLIFIERS 790 14.6.3
COMMON-BASE AND COMMON-GATE AMPLIFIERS 793 14.6.4 SETTING LOWER CUTOFF
FREQUENCY F L 796 14.7 AMPLIFIER DESIGN EXAMPLES 797 14.7.1 MONTE CARLO
EVALUATION OF THE COMMON-BASE AMPLIFIER DESIGN 806- 14.8 MULTISTAGE
AC-COUPLED AMPLIFIERS 811 14.8.1 A THREE-STAGE AC-COUPLED AMPLIFIER 811
14.8.2 VOLTAGE GAIN 813 14.8.3 INPUT RESISTANCE 815 14.8.4 SIGNAL SOURCE
VOLTAGE GAIN 815 14.8.5 OUTPUT RESISTANCE 815 14.8.6 CURRENT AND POWER
GAIN 816 14.8.7 INPUT SIGNAL RANGE 817 14.8.8 IMPROVING AMPLIFIER
VOLTAGE GAIN 820 14.8.9 ESTIMATING THE LOWER CUTOFF FREQUENCY OF THE
MULTISTAGE AMPLIFIER 820 SUMMARY 822 KEY TERMS 823 ADDITIONAL READING
824 PROBLEMS 824 CHAPTER 15 DIFFERENTIAL AMPLIFIERS AND OPERATIONAL
AMPLIFIER DESIGN 838 15.1 DIFFERENTIAL AMPLIFIERS 839 15.1.1 BIPOLAR AND
MOS DIFFERENTIAL AMPLIFIERS 840 CONTENTS XV 15.1.2 DC ANALYSIS OF THE
BIPOLAR DIFFERENTIAL AMPLIFIER 840 15.1.3 TRANSFER CHARACTERISTIC FOR
THE BIPOLAR DIFFERENTIAL AMPLIFIER 842 15.1.4 AC ANALYSIS OF THE BIPOLAR
DIFFERENTIAL AMPLIFIER 843 15.1.5 DIFFERENTIAL-MODE GAIN AND INPUT
RESISTANCE 844 15.1.6 COMMON-MODE GAIN AND INPUT RESISTANCE 846 15.1.7
COMMON-MODE REJECTION RATIO (CMRR) 848 15.1.8 ANALYSIS USING
DIFFERENTIAL- AND COMMON-MODE HALF-CIRCUITS 849 15.1.9 BIASING WITH
ELECTRONIC CURRENT SOURCES 852 15.1.10 MODELING THE ELECTRONIC CURRENT
SOURCE IN SPICE 853 15.1.11 DC ANALYSIS OF THE MOSFET DIFFERENTIAL
AMPLIFIER 853 15.1.12 DIFFERENTIAL-MODE INPUT SIGNALS 855 15.1.13
SMALL-SIGNAL TRANSFER CHARACTERISTIC FOR THE MOS DIFFERENTIAL AMPLIFIER
856 15.1.14 COMMON-MODE INPUT SIGNALS 856 15.1.15 TWO-PORT MODEL FOR
DIFFERENTIAL PAIRS 857 15.2 EVOLUTION TO BASIC OPERATIONAL AMPLIFIERS
861 15.2.1 A TWO-STAGE PROTOTYPE FOR AN OPERATIONAL AMPLIFIER 861 15.2.2
IMPROVING THE OP AMP VOLTAGE GAIN 867 15.2.3 OUTPUT RESISTANCE REDUCTION
868 15.2.4 A CMOS OPERATIONAL AMPLIFIER PROTOTYPE 872 15.2.5 BICMOS
AMPLIFIERS 873 15.3 OUTPUT STAGES 874 15.3.1 THE SOURCE FOLLOWER*A
CLASS-A OUTPUT STAGE 874 15.3.2 EFFICIENCY OF CLASS-A AMPLIFIERS 876
15.3.3 CLASS-B PUSH-PULL OUTPUT STAGE 876 15.3.4 CLASS-AB AMPLIFIERS 878
15.3.5 CLASS-AB OUTPUT STAGES FOR ,. OPERATIONAL AMPLIFIERS 880 15.3.6
SHORT-CIRCUIT PROTECTION 880 15.3.7 TRANSFORMER COUPLING 881 15.4
ELECTRONIC CURRENT SOURCES 884 15.4.1 SINGLE-TRANSISTOR CURRENT SOURCES
885 15.4.2 FIGURE OF MERIT FOR CURRENT SOURCES 885 15.4.3 HIGHER OUTPUT
RESISTANCE SOURCES 886 15.4.4 CURRENT SOURCE DESIGN EXAMPLES 886 15.5
CIRCUIT ELEMENT MATCHING 893 15.6 CURRENT MIRRORS 894 15.6.1 DC ANALYSIS
OF THE MOS TRANSISTOR CURRENT MIRROR 894 15.6.2 CHANGING THE MOS MIRROR
RATIO 897 15.6.3 DC ANALYSIS OF THE BIPOLAR TRANSISTOR CURRENT MIRROR
897 15.6.4 ALTERING THE BJT CURRENT MIRROR RATIO 899 15.6.5 MULTIPLE
CURRENT SOURCES 900 15.6.6 BUFFERED CURRENT MIRROR 902 15.6.7 OUTPUT
RESISTANCE OF THE CURRENT MIRRORS 902 15.6.8 TWO-PORT MODEL FOR THE
CURRENT MIRROR 903 15.6.9 THE WIDLAR CURRENT SOURCE 906 15.6.10 THE MOS
VERSION OF THE WIDLAR SOURCE 907 15.7 HIGH-OUTPUT-RESISTANCE CURRENT
MIRRORS 909 15.7.1 THE WILSON CURRENT SOURCES 909 15.7.2 OUTPUT
RESISTANCE OF THE WILSON SOURCE 911 15.7.3 CASCODE CURRENT SOURCES 912
15.7.4 OUTPUT RESISTANCE OF THE CASCODE SOURCES 913 15.7.5 CURRENT
MIRROR SUMMARY 914 15.8 REFERENCE CURRENT GENERATION 917 15.8.1
SUPPLY-INDEPENDENT BIASING 917 15.8.2 A SUPPLY-INDEPENDENT MOS REFERENCE
CELL 920 15.9 THE CURRENT MIRROR AS AN ACTIVE LOAD 924 15.9.1 CMOS
DIFFERENTIAL AMPLIFIER WITH ACTIVE LOAD 924 15.9.2 BIPOLAR DIFFERENTIAL
AMPLIFIER WITH ACTIVE LOAD 931 15.10 ACTIVE LOGDS IN OPERATIONAL
AMPLIFIERS 935 15.10.1 CMOS OP AMP VOLTAGE GAIN 935 15.10.2 DC DESIGN
CONSIDERATIONS 936 15.10.3 BIPOLAR OPERATIONAL AMPLIFIERS 938 15.10.4
INPUT STAGE BREAKDOWN 939 15.11 THE 1XA741 OPERATIONAL AMPLIFIER 940
15.11.1 BIAS CIRCUITRY 941 15.11.2 DC ANALYSIS OF THE 741 INPUT STAGE
942 15.11.3 AC ANALYSIS OF THE 741 INPUT STAGE 945 15.11.4 VOLTAGE GAIN
OF THE COMPLETE AMPLIFIER 946 15.11.5 THE 741 OUTPUT STAGE 950 15.11.6
OUTPUT RESISTANCE 952 XVI CONTENTS 15.11.7 SHORT CIRCUIT PROTECTION 952
15.11.8 SUMMARY OF THE 1XA741 OPERATIONAL AMPLIFIER CHARACTERISTICS 952
SUMMARY 955 KEY TERMS 957 REFERENCES 957 ADDITIONAL READING 958 PROBLEMS
958 CHAPTER 16 FREQUENCY RESPONSE 985 16.1 AMPLIFIER FREQUENCY RESPONSE
986 16.1.1 LOW-FREQUENCY RESPONSE 987 16.1.2 ESTIMATING CO L IN THE
ABSENCE OF A DOMINANT POLE 987 16.1.3 HIGH-FREQUENCY RESPONSE 990 16.1.4
ESTIMATING A) H IN THE ABSENCE OF A DOMINANT POLE 990 16.2 DIRECT
DETERMINATION OF THE LOW-FREQUENCY POLES AND ZEROS*THE COMMON-SOURCE
AMPLIFIER 991 16.3 ESTIMATION OF CO L USING THE SHORT-CIRCUIT
TIME-CONSTANT METHOD 996 16.3.1 ESTIMATE OF (O L FOR THE COMMON-EMITTER
AMPLIFIER 997 16.3.2 ESTIMATE OF CO L FOR THE COMMON-SOURCE AMPLIFIER
1001 16.3.3 ESTIMATE OF CO L FOR THE COMMON-BASE AMPLIFIER 1002 16.3.4
ESTIMATE OF CO L FOR THE COMMON-GATE AMPLIFIER 1003 16.3.5 ESTIMATE OF
A L FOR THE COMMON-COLLECTOR AMPLIFIER 1004 16.3.6 ESTIMATE OF CO L FOR
THE COMMON-DRAIN AMPLIFIER 1004 16.4 TRANSISTOR MODELS AT HIGH
FREQUENCIES 1005 16.4.1 FREQUENCY-DEPENDENT HYBRID-PI MODEL FOR THE
BIPOLAR TRANSISTOR 1005 16.4.2 MODELING C N AND C^ IN SPICE 1006 16.4.3
UNITY-GAIN FREQUENCY F T 1006 16.4.4 HIGH-FREQUENCY MODEL FOR THE FET
1009 16.4.5 MODELING C GS AND C GD IN SPICE 1010 16.4.6 CHANNEL
LENGTHJIEPENDENCE OF/R 1010 16.4.7 LIMITATIONS OF THE HIGH-FREQUENCY
MODELS 1012 16.5 BASE RESISTANCE IN THE HYBRID-PI MODEL 1012 16.5.1
EFFECT OF BASE RESISTANCE ON MIDBAND AMPLIFIERS 1013 16.6 HIGH-FREQUENCY
COMMON-EMITTER AND COMMON-SOURCE AMPLIFIER ANALYSIS 1015 16.6.1 THE
MILLER EFFECT 1016 16.6.2 COMMON-EMITTER AND COMMON-SOURCE AMPLIFIER
HIGH-FREQUENCY RESPONSE 1017 16.6.3 DIRECT ANALYSIS OF THE
COMMON-EMITTER TRANSFER CHARACTERISTIC 1019 16.6.4 POLES OF THE
COMMON-EMITTER AMPLIFIER 1020 16.6.5 DOMINANT POLE FOR THE COMMON-SOURCE
AMPLIFIER 1023 16.6.6 ESTIMATION OF (O H USING THE OPEN-CIRCUIT
TIME-CONSTANT METHOD 1024 16.6.7 COMMON-SOURCE AMPLIFIER WITH SOURCE
DEGENERATION RESISTANCE 1027 16.6.8 POLES OF THE COMMON-EMITTER WITH
EMITTER DEGENERATION RESISTANCE 1029 16.7 COMMON-BASE AND COMMON-GATE
AMPLIFIER HIGH-FREQUENCY RESPONSE 1031 16.8 COMMON-COLLECTOR AND
COMMON-DRAIN AMPLIFIER HIGH-FREQUENCY RESPONSE 1034 16.9 SINGLE-STAGE
AMPLIFIERHIGH-FREQUENCY RESPONSE SUMMARY 1036 16.9.1 AMPLIFIER
GAIN-BANDWIDTH LIMITATIONS 1036 16.10 FREQUENCY RESPONSE OF MULTISTAGE
AMPLIFIERS 1037 16.10.1 DIFFERENTIAL AMPLIFIER 1038 16.10.2 THE
COMMON-COLLECTOR/COMMON- BASE CASCADE 1039 16.10.3 HIGH-FREQUENCY
RESPONSE OF THE CASCODE AMPLIFIER 1041 16.10.4 CUTOFF FREQUENCY FOR THE
CURRENT MIRROR 1042 16.10.5 THREE-STAGE AMPLIFIER EXAMPLE 1043 16.11
TUNED AMPLIFIERS 1050 16.11.1 SINGLE-TUNED AMPLIFIER 1050 16.11.2 USE OF
A TAPPED INDUCTOR*THE AUTO TRANSFORMER 1053 16.11.3 MULTIPLE TUNED
CIRCUITS*SYNCHRONOUS AND STAGGER TUNING 1054 SUMMARY 1056 KEY TERMS 1057
REFERENCE 1058 PROBLEMS 1058 CONTENTS XVII CHAPTER 17 FEEDBACK,
STABILITY, AND OSCILLATORS 1068 17.1 CLASSIC FEEDBACK SYSTEMS 1069 17.2
FEEDBACK AMPLIFIER DESIGN USING TWO-PORT NETWORK THEORY 1070 17.3
VOLTAGE AMPLIFIERS*SERIES-SHUNT FEEDBACK 1071 17.3.1 VOLTAGE GAIN
CALCULATION 1072 17.3.2 INPUT RESISTANCE 1074 17.3.3 OUTPUT RESISTANCE
1074 17.4 TRANSRESISTANCE AMPLIFIERS*SHUNT-SHUNT FEEDBACK 1078 17.4.1
TRANSRESISTANCE ANALYSIS 1079 17.4.2 INPUT RESISTANCE 1081 17.4.3 OUTPUT
RESISTANCE 1081 17.5 CURRENT AMPLIFIERS*SHUNT-SERIES FEEDBACK 1086
17.5.1 CURRENT GAIN CALCULATION 1086 17.5.2 INPUT RESISTANCE 1088 17.5.3
OUTPUT RESISTANCE 1089 17.6 TRANSCONDUCTANCE AMPLIFIERS*SERIES-SERIES
FEEDBACK 1090 17.6.1 TRANSCONDUCTANCE ANALYSIS 1090 17.6.2 INPUT AND
OUTPUT RESISTANCES 1092 17.7 COMMON ERRORS IN APPLYING TWO-PORT FEEDBACK
THEORY 1092 17.8 FINDING THE LOOP GAIN 1100 17.8.1 DIRECT CALCULATION OF
THE LOOP GAIN 1100 17.8.2 FINDING THE LOOP GAIN USING SUCCESSIVE VOLTAGE
AND CURRENT INJECTION 1102 17.8.3 SIMPLIFICATIONS 1105 17.9 BLACKMAN S
THEOREM TO THE RESCUE 1107 17.10 USING FEEDBACK TO CONTROL FREQUENCY
RESPONSE 1114 17.11 STABILITY OF FEEDBACK AMPLIFIERS 1116 17.11.1 THE
NYQUIST PLOT 1116 17.11.2 FIRST-ORDER SYSTEMS 1117 17.11.3 SECOND-ORDER
SYSTEMS AND PHASE MARGIN 1118 17.11.4 THIRD-ORDER SYSTEMS AND GAIN
MARGIN 1119 17.11.5 DETERMINING STABILITY FROM THE BODE PLOT 1120 17.12
SINGLE-POLE OPERATIONAL AMPLIFIER COMPENSATION 1122 17.12.1 THREE-STAGE
OP AMP ANALYSIS 1123 17.12.2 TRANSMISSION ZEROS IN FET OP AMPS 1124
17.12.3 BIPOLAR AMPLIFIER COMPENSATION 1126 17.12.4 SLEW RATE OF THE
OPERATIONAL AMPLIFIER 1127 17.12.5 RELATIONSHIPS BETWEEN SLEW RATE AND
GAIN-BANDWIDTH PRODUCT 1128 17.13 OSCILLATORS 1137 17.13.1 THE
BARKHAUSEN CRITERIA FOR OSCILLATION 1137 17.13.2 OSCILLATORS EMPLOYING
FREQUENCY-SELECTIVE RC NETWORKS 1140 17.13.3 LC OSCILLATORS 1144 17.13.4
CRYSTAL OSCILLATORS 1146 SUMMARY 1151 KEY TERMS 1152 REFERENCES 1152
PROBLEMS 1153 APPENDIXES A STANDARD DISCRETE COMPONENT VALUES 1164 B
SOLID-STATE DEVICE MODELS AND SPICE SIMULATION PARAMETERS 1167 INDEX
1170
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THIRD EDITION CIRCUIT DESIGN *''.'* ':, . ME GRAW HILL HIGHER EDUCATION
BOSTON BURR RIDGE, IL DUBUQUE, IA NEW YORK SAN FRANCISCO ST. LOUIS
BANGKOK BOGOTA CARACAS KUALA LUMPUR LISBON LONDON MADRID MEXICO CITY
MILAN MONTREAL NEW DELHI SANTIAGO SEOUL SINGAPORE SYDNEY TAIPEI TORONTO
CONTENTS PREFACE XIX PART ON E SOLID STATE ELECTRONIC AND DEVICES
CHAPTER 1 INTRODUCTION TO ELECTRONICS 3 1.1 A BRIEF HISTORY OF
ELECTRONICS: FROM VACUUM TUBES TO ULTRA-LARGE-SCALE INTEGRATION 5 1.2
CLASSIFICATION OF ELECTRONIC SIGNALS 8 1.2.1 DIGITAL SIGNALS 9 1.2.2
ANALOG SIGNALS 9 1.2.3 A/D AND D/A CONVERTERS- BRIDGING THE ANALOG AND
DIGITAL DOMAINS 10 1.3 NOTATIONAL CONVENTIONS 12 1.4 PROBLEM-SOLVING
APPROACH 13 1.5 IMPORTANT CONCEPTS FROM CIRCUIT THEORY 15 1.5.1 VOLTAGE
AND CURRENT DIVISION 15 1.5.2 THEVENIN AND NORTON CIRCUIT
REPRESENTATIONS 16 1.6 FREQUENCY SPECTRUM OF ELECTRONIC SIGNALS 21 1.7
AMPLIFIERS 22 1.7.1 IDEAL OPERATIONAL AMPLIFIERS 23 1.7.2 AMPLIFIER
FREQUENCY RESPONSE 25 1.8 ELEMENT VARIATIONS IN CIRCUIT DESIGN 26 1.8.1
MATHEMATICAL MODELING OF TOLERANCES 26 1.8.2 WORST-CASE ANALYSIS 27
1.8.3 JIAONTE CARLO ANALYSIS 29 1.8.4 TEMPERATURE COEFFICIENTS 32 1.9
NUMERIC PRECISION 34 SUMMARY 34 KEY TERMS 35 REFERENCES 36 ADDITIONAL
READING 36 PROBLEMS 37 CHAPTER 2 SOLID-STATE ELECTRONICS 41 2.1
SOLID-STATE ELECTRONIC MATERIALS 43 2.2 COVALENT BOND MODEL 44 2.3 DRIFT
CURRENTS AND MOBILITY IN SEMICONDUCTORS 47 2.3.1 DRIFT CURRENTS 47 2.3.2
MOBILITY 48 2.3.3 VELOCITY SATURATION 48 2.4 RESISTIVITY OF INTRINSIC
SILICON 49 2.5 IMPURITIES IN SEMICONDUCTORS 50 2.5.1 DONOR IMPURITIES IN
SILICON 51 2.5.2 ACCEPTOR IMPURITIES IN SILICON 51 2.6 ELECTRON AND HOLE
CONCENTRATIONS IN DOPED SEMICONDUCTORS 51 2.6.1 N-TYPE MATERIAL (A/ D
N A ) 52 2.6.2 P-TYPE MATERIAL {N A N D ) 53 2.7 MOBILITY AND
RESISTIVITY IN DOPED SEMICONDUCTORS 54 2.8 DIFFUSION CURRENTS 58 2.9
TOTAL CURRENT 59 2.10 ENERGY BAND MODEL 60 2.10.1 ELECTRON-HOLE PAIR
GENERATION IN AN INTRINSIC SEMICONDUCTOR 60 2.10.2 ENERGY BAND MODEL FOR
A DOPED SEMICONDUCTOR 61 2.10.3 COMPENSATED SEMICONDUCTORS 61 2.11
OVERVIEW OF INTEGRATED CIRCUIT FABRICATION 63 SUMMARY 66 KEY TERMS 67
REFERENCE 68 ADDITIONAL READING 68 IMPORTANT EQUATIONS 68 PROBLEMS 69
CHAPTER 3 SOLID-STATE DIODES AND DIODE CIRCUITS 73 3.1 THE PN JUNCTION
DIODE 74 3.1.1 PN JUNCTION ELECTROSTATICS 74 3.1.2 INTERNAL DIODE
CURRENTS 78 VII VIII CONTENTS 3.2 THE /-V CHARACTERISTICS OF THE DIODE
79 3.3 THE DIODE EQUATION: A MATHEMATICAL MODEL FOR THE DIODE 81 3.4
DIODE CHARACTERISTICS UNDER REVERSE, ZERO, AND FORWARD BIAS 84 3.4.1
REVERSE BIAS 84 3.4.2 ZERO BIAS 84 3.4.3 FORWARD BIAS 85 3.5 DIODE
TEMPERATURE COEFFICIENT 88 3.6 DIODES UNDER REVERSE BIAS 88 3.6.1
SATURATION CURRENT IN REAL DIODES 89 3.6.2 REVERSE BREAKDOWN 90 3.6.3
DIODE MODEL FOR THE BREAKDOWN REGION 91 3.7 PN JUNCTION CAPACITANCE 91
3.7.1 REVERSE BIAS 91 3.7.2 FORWARD BIAS 92 3.8 SCHOTTKY BARRIER DIODE
92 3.9 DIODE SPICE MODEL AND LAYOUT 93 3.10 DIODE CIRCUIT ANALYSIS 95
3.10.1 LOAD-LINE ANALYSIS 95 3.10.2 ANALYSIS USING THE MATHEMATICAL
MODEL FOR THE DIODE 97 3.10.3 THE IDEAL DIODE MODEL 101 3.10.4 CONSTANT
VOLTAGE DROP MODEL 103 3.10.5 MODEL COMPARISON AND DISCUSSION 104 3.11
MULTIPLE-DIODE CIRCUITS 105 3.12 ANALYSIS OF DIODES OPERATING IN THE
BREAKDOWN REGION 108 3.12.1 LOAD-LINE ANALYSIS 108 3.12.2 ANALYSIS WITH
THE PIECEWISE LINEAR MODEL 109 3.12.3 VOLTAGE REGULATION 109 3.12.4
ANALYSIS INCLUDING ZENER RESISTANCE 110 3.12.5 LINE AND LOAD REGULATION
111 3.13 HALF-WAVE RECTIFIER CIRCUITS 112 3.13.1 HALF-WAVE RECTIFIER
WITH RESISTOR LOAD 112 3.13.2 RECTIFIER FILTER CAPACITOR 114 3.13.3
HALF-WAVE RECTIFIER WITH RC LOAD 114 3.13.4 RIPPLE VOLTAGE AND
CONDUCTION INTERVAL 115 3.13.5 DIODE CURRENT 118 3.13.6 SURGE CURRENT
119 3.13.7 PEAK-LNVERSE-VO'LTAGE (PIV) RATING 119 3.13.8 DIODE POWER
DISSIPATION 120 3.13.9 HALF-WAVE RECTIFIER WITH NEGATIVE OUTPUT VOLTAGE
120 &14 FULL-WAVE RECTIFIER CIRCUITS 121 3.14.1 FULL-WAVE RECTIFIER WITH
NEGATIVE,-^-I OUTPUT VOLTAGE 122 FE 3.15 FULL-WAVE BRIDGE RECTIFICATION
122 3.16 RECTIFIER COMPARISON AND DESIGN TRADEOFFS 123 3.17 DYNAMIC
SWITCHING BEHAVIOR OF THE DIODE 127 3.18 PHOTO DIODES, SOLAR CELLS, AND
LIGHT-EMITTING DIODES 128 3.18.1 PHOTO DIODES AND PHOTODETECTORS 128
3.18.2 POWER GENERATION FROM SOLAR CELLS 129 3.18.3 LIGHT-EMITTING
DIODES (LEDS) 130 SUMMARY 131 KEY TERMS 132 REFERENCE 133 ADDITIONAL
READING 133 PROBLEMS 133 CHAPTER 4 FIELD-EFFECT TRANSISTORS 143 4.1
CHARACTERISTICS OF THE MOS CAPACITOR 144 4.1.1 ACCUMULATION REGION 145
4.1.2 DEPLETION REGION 146 4.1.3 INVERSION REGION 146 4.2 THE NMOS
TRANSISTOR 146 4.2.1 QUALITATIVE I-V BEHAVIOR OF THE NMOS TRANSISTOR 147
4.2.2 TRIODE 1 REGION CHARACTERISTICS OF THE NMOS TRANSISTOR 148 4.2.3
ON RESISTANCE 151 4.2.4 SATURATION OF THE I-V CHARACTERISTICS 152 4.2.5
MATHEMATICAL MODEL IN THE SATURATION (PINCH-OFF) REGION 153 4.2.6
TRANSCONDUCTANCE 155 4.2.7 CHANNEL-LENGTH MODULATION 155 4.2.8 TRANSFER
CHARACTERISTICS AND DEPLETION-MODE MOSFETS 156 4.2.9 BODY EFFECT OR
SUBSTRATE SENSITIVITY 157 4.3 PMOS TRANSISTORS 159 4.4 MOSFET CIRCUIT
SYMBOLS 160 4.5 MOS TRANSISTOR FABRICATION AND LAYOUT DESIGN RULES 2 163
4.5.1 MINIMUM FEATURE SIZE AND ALIGNMENT TOLERANCE 163 4.5.2 MOS
TRANSISTOR LAYOUT 164 4.6 CAPACITANCES IN MOS TRANSISTORS 165 4.6.1 NMOS
TRANSISTOR CAPACITANCES IN THE TRIODE REGION 166 4.6.2 CAPACITANCES IN
THE SATURATION W REGION 167 4.6.3 CAPACITANCES IN CUTOFF 167 CONTENTS IX
4.7 MOSFET MODELING IN SPICE 167 4.8 BIASING THE NMOS FIELD-EFFECT
TRANSISTOR 169 4.8.1 WHY DO WE NEED BIAS? 169 4.9 BIASING THE PMOS
FIELD-EFFECT TRANSISTOR 187 4.10 MOS TRANSISTOR SCALING 189 4.10.1 DRAIN
CURRENT 189 4.10.2 GATE CAPACITANCE 191 4.10.3 CIRCUIT AND POWER
DENSITIES 191 4.10.4 POWER-DELAY PRODUCT 191 4.10.5 CUTOFF FREQUENCY 192
4.10.6 HIGH FIELD LIMITATIONS 192 4.10.7 SUBTHRESHOLD CONDUCTION 193
SUMMARY 194 KEY TERMS 195 REFERENCES 196 PROBLEMS 197 CHAPTER 5 BIPOLAR
JUNCTION TRANSISTORS 207 5.1 PHYSICAL STRUCTURE OF THE BIPOLAR
TRANSISTOR 208 5.2 THE TRANSPORT MODEL FOR THE NPN TRANSISTOR 209 5.2.1
FORWARD CHARACTERISTICS 210 5.2.2 REVERSE CHARACTERISTICS 212 5.2.3 THE
COMPLETE TRANSPORT MODEL EQUATIONS FOR ARBITRARY BIAS CONDITIONS 213 5.3
THE PNP TRANSISTOR 215 5.4 EQUIVALENT CIRCUIT REPRESENTATIONS FOR THE
TRANSPORT MODELS 217 5.5 THE I-V CHARACTERISTICS OF THE BIPOLAR
TRANSISTOR 218 5.5.1 OUTPUT CHARACTERISTICS 218 5.5.2 TRANSFER
CHARACTERISTICS 219 5.6 THE OPERATING REGIONS OF THE BIPOLAR TRANSISTOR
220 5.7 TRANSPORT MODEL SIMPLIFICATIONS 221 5.7.1 SIMPLIFIED MODEL FOR
THE CUTOFF REGION 221 5.7.2 MODEL SIMPLIFICATIONS FOR THE FORWARD-ACTIVE
REGION 223 5.7.3 DIODES IN BIPOLAR INTEGRATED /CIRCUITS 229 5.7.4
SIMPLIFIED MODEL FOR THE REVERSE-ACTIVE REGION 230 5.7.5 MODELING
OPERATION IN THE SATURATION REGION 232 5.8 NONIDEAL BEHAVIOR OF THE
BIPOLAR TRANSISTOR 235 - " 5.8.1 JUNCTION BREAKDOW^'VTT^ES 236 5.8.2
MINORITY-CARRIER TRANSPORT IN THE BASE REGION 236 5.8.3 BASE TRANSIT
TIME 237 5.8.4 DIFFUSION CAPACITANCE 239 5.8.5 FREQUENCY DEPENDENCE OF
THE COMMON-EMITTER CURRENT GAIN 240 5.8.6 THE EARLY EFFECT AND EARLY
VOLTAGE 240 5.8.7 MODELING THE EARLY EFFECT 241 5.8.8 ORIGIN OF THE
EARLY EFFECT 241 5.9 TRANSCONDUCTANCE 242 5.10 BIPOLAR TECHNOLOGY AND
SPICE MODEL 243 5.10.1 QUALITATIVE DESCRIPTION 243 5.10.2 SPICE MODEL
EQUATIONS 244 5.10.3 HIGH-PERFORMANCE BIPOLAR TRANSISTORS 245 5.11
PRACTICAL BIAS CIRCUITS FOR THE BJT 246 5.11.1 FOUR-RESISTOR BIAS
NETWORK 248 5.11.2 DESIGN OBJECTIVES FOR THE FOUR-RESISTOR BIAS NETWORK
249 5.12 TOLERANCES IN BIAS CIRCUITS 254 5.12.1 WORST-CASE ANALYSIS 255
5.12.2 MONTE CARLO ANALYSIS 257 SUMMARY 260 KEY TERMS 262 REFERENCES 262
PROBLEMS 263 PART TWO DIGITAL ELECTRONICS CHAPTER 6 INTRODUCTION TO
DIGITAL ELECTRONICS 275 6.1 IDEAL LOGIC GATES 277 6.2 LOGIC LEVEL
DEFINITIONS AND NOISE MARGINS 277 6.2.1 LOGIC VOLTAGE LEVELS 279 6.2.2
NEISE MARGINS 279 6.2.3 LOGIC GATE DESIGN GOALS 280 6.3 DYNAMIC RESPONSE
OF LOGIC GATES 281 6.3.1 RISE TIME AND FALL TIMES 281 6.3.2 PROPAGATION
DELAY 282 6.3.3 POWER-DELAY PRODUCT 282 6.4 REVIEW OF BOOLEAN ALGEBRA
283 6.5 NMOS LOGIC DESIGN 285 6.5.1 NMOS INVERTER WITH RESISTIVE LOAD
286 6.5.2 DESIGN OF THE W/L RATIO OF M S 287 6.5.3 LOAD RESISTOR DESIGN
288 6.5.4 LOAD-LINE VISUALIZATION 288 6.5.5 ON-RESISTANCE OF THE
SWITCHING DEVICE 290 CONTENTS 6.5.6 NOISE MARGIN ANALYSIS 291 6.5.7
CALCULATION OF V, L AND V O H 291 6.5.8 CALCULATION OF V TH AND V 0L 292
6.5.9 LOAD RESISTOR PROBLEMS 293 6.6 TRANSISTOR ALTERNATIVES TO THE LOAD
RESISTOR 294 6.6.1 THE NMOS SATURATED LOAD INVERTER 295 6.6.2 NMOS
INVERTER WITH A LINEAR LOAD DEVICE 303 6.6.3 NMOS INVERTER WITH A
DEPLETION-MODE LOAD 304 6.6.4 STATIC DESIGN OF THE PSEUDO NMOS INVERTER
307 6.7 NMOS INVERTER SUMMARY AND COMPARISON 311 6.8 NMOS NAND AND NOR
GATES 312 6.8.1 NOR GATES 313 6.8.2 NAND GATES 314 6.8.3 NOR AND NAND
GATE LAYOUTS IN NMOS DEPLETION-MODE TECHNOLOGY 315 6.9 COMPLEX NMOS
LOGIC DESIGN 316 6.9.1 SELECTING BETWEEN THE TWO DESIGNS 319 6.10 POWER
DISSIPATION 321 6.10.1 STATIC POWER DISSIPATION 321 6.10.2 DYNAMIC POWER
DISSIPATION 322 6.10.3 POWER SCALING IN MOS LOGIC GATES 323 6.11 DYNAMIC
BEHAVIOR OF MOS LOGIC GATES 325 6.11.1 CAPACITANCES IN LOGIC CIRCUITS
325 6.11.2 DYNAMIC RESPONSE OF THE NMOS INVERTER WITH A RESISTIVE LOAD
326 6.11.3 PSEUDO NMOS INVERTER 331 6.11.4 A FINAL COMPARISON OF NMOS
INVERTER DELAYS 332 6.12 PMOS LOGIC 335 6.12.1 PMOS INVERTERS 335 6.12.2
NOR AND NAND GATES 338 SUMMARY 338 KEY TERMS 340 REFERENCES 341
ADDITIONAL READING 341 PROBLEMS 341 CHAPTER 7 /*' COMPLEMENTARY MOS
(CMOS) LOGIC DESIGN 352 7.1 CMOS INVERTER TECHNOLOGY 353 7.1.1 CMOS
INVERTER LAYOUT 355 7.2 STATIC CHARACTERISTICS OF THE CMOS INVERTER 355
7.2.1 CMOS VOLTAGE TRANSFER CHARACTERISTICS 356 7.2.2 NOISE MARGINS FOR
THE CMOS INVERTER 358 7.3 DYNAMIC BEHAVIOR OF THE CMOS INVERTER 360
7.3.1 PROPAGATION DELAY ESTIMATE 360 7.3.2 RISE AND FALL TIMES 362 7.3.3
DELAY OF CASCADED INVERTERS 364 7.4 POWER DISSIPATION AND POWER DELAY
PRODUCT IN CMOS 365 7.4.1 STATIC POWER DISSIPATION 365 7.4.2 DYNAMIC
POWER DISSIPATION 365 7.4.3 POWER-DELAY PRODUCT 366 7.5 CMOS NOR AND
NAND GATES 367 7.5.1 CMOS NOR GATE 367 7.5.2 CMOS NAND GATES 370 7.6
DESIGN OF COMPLEX GATES IN CMOS 372 7.7 MINIMUM SIZE GATE DESIGN AND
PERFORMANCE 376 7.8 DYNAMIC DOMINO CMOS LOGIC 379 7.9 CASCADE BUFFERS
380 7.9.1 CASCADE BUFFER DELAY MODEL 381 7.9.2 OPTIMUM NUMBER OF STAGES
381 7.10 THE CMOS TRANSMISSION GATE 384 7.11 CMOSLATCHUP 384 SUMMARY 387
KEY TERMS 388 REFERENCES 389 PROBLEMS 389 CHAPTER 8 MOS MEMORY AND
STORAGE CIRCUITS 398 8.1 RANDOM ACCESS MEMORY 399 8.1.1 RANDOM ACCESS
MEMORY (RAM) ARCHITECTURE 399 8.1.2 A 256-MB MEMORY CHIP 400 8.2 STATIC
MEMORY CELLS 401 8.2.1 MEMORY CELL ISOLATION AND ACCESS-THE6-TCELL 402
8.2.2 THE READ OPERATION 403 8.2.3 WRITING DATA INTO THE 6-T CELL 406
8.3 DYNAMIC MEMORY CELLS 408 8.3.1 THE ONE-TRANSISTOR CELL 410 8.3.2
DATA STORAGE IN THE I-T CELL 410 8.3.3 READING DATA FROM THE I-T CELL
412 8.3.4 THE FOUR-TRANSISTOR CELL 413 8.4 SENSE AMPLIFIERS 414 8.4.1 A
SENSE AMPLIFIER FOR THE 6-T CELL 414 8.4.2 A SENSE AMPLIFIER FOR THE I-T
CELL 416 8.4.3 THE BOOSTED WORDLINE CIRCUIT 418 8.4.4 CLOCKED CMOS SENSE
AMPLIFIERS 418 CONTENTS XI 8.5 ADDRESS DECODERS 420 8.5.1 NOR DECODER
420 8.5.2 NAND DECODER 420 8.5.3 DECODERS IN DOMINO CMOS LOGIC 422 8.5.4
PASS-TRANSISTOR COLUMN DECODER 422 8.6 READ-ONLY MEMORY (ROM) 424 8.7
FLIP-FLOPS 427 8.7.1 RS FLIP-FLOP 429 8.7.2 THE D-LATCH USING
TRANSMISSION GATES 430 8.7.3 A MASTER-SLAVE D FLIP-FLOP 430 SUMMARY 431
KEY TERMS 432 REFERENCES 432 PROBLEMS 433 CHAPTER 9 BIPOLAR LOGIC
CIRCUITS 440 9.1 THE CURRENT SWITCH (EMITTER-COUPLED PAIR) 441 9.1.1
MATHEMATICAL MODEL FOR STATIC BEHAVIOR OF THE CURRENT SWITCH 442 9.1.2
CURRENT SWITCH ANALYSIS FOR V, V REF 443 9.1.3 CURRENT SWITCH ANALYSIS
FOR VI L/ RE F 444 9.2 THE EMITTER-COUPLED LOGIC (ECL) GATE 444 9.2.1
ECL GATE WITH V, = V H 445 9.2.2 ECL GATE WITH V, - V L 446 9.2.3 INPUT
CURRENT OF THE ECL GATE 446 9.2.4 ECL SUMMARY 446 9.3 NOISE MARGIN
ANALYSIS FOR THE ECL GATE 447 9.3.1 V IL ,V 0 H,V IHF ANDV 0 L 447 9.3.2
NOISE MARGINS 448 9.4 CURRENT SOURCE IMPLEMENTATION 449 9.5 THE ECL
OR-NOR GATE 451 9.6 THE EMITTER FOLLOWER 453 9.6.1 EMITTER FOLLOWER WITH
A LOAD RESISTOR 454 9.7 "EMITTER DOTTING" OR "WIRED-OR" LOGIC 456 9.7.1
PARALLEL CONNECTION OF EMITTER-FOLLOWER OUTPUTS 457 9.7.2 THE WIRED-OR
LOGIC FUNCTION 457 9.8 ECL POJ/VER-DELAY CHARACTERISTICS 457 9.8.1 POWER
DISSIPATION 467 9.8.2 GATE DELAY 459 9.8.3 POWER-DELAY PRODUCT 489 9.9
THE SATURATING BIPOLAR INVEFJTEF 4#1 9.9.1 STATIC INVERTER
CHARACTERISTICS 464 9.9.2 SATURATION VOLTAGE OF THE BIPOLAR TRANSISTOR
484 *.**'$$!;-*&';* * 9.9.3 LOAD-LINE VISUALIZATION 466 9.9.4 SWITCHING
CHARACTERISTICS OF THE SATURATED BJT 467 9.10 A TRANSISTOR-TRANSISTOR
LOGIC (TTL) PROTOTYPE 469 9.10.1 TTL INVERTER FOR V, = V L 470 9.10.2
TTL INVERTER FOR V, = V H 471 9.10.3 POWER IN THE PROTOTYPE TTL GATE 471
9.10.4 VIH, VIL, AND NOISE MARGINS FOR THE TTL PROTOTYPE 472 9.10.5
PROTOTYPE INVERTER SUMMARY 474 9.10.6 FANOUT LIMITATIONS OF THE TTL
PROTOTYPE 474 9.11 THE STANDARD 7400 SERIES TTL INVERTER 477 9.11.1
ANALYSIS FOR V, = V L 478 9.11.2 ANALYSIS FOR V, = V H 479 9.11.3 POWER
CONSUMPTION 480 9.11.4 TTL PROPAGATION DELAY AND POWER-DELAY PRODUCT 480
9.11.5 TTL VOLTAGE TRANSFER CHARACTERISTIC AND NOISE MARGINS 481 9.11.6
FANOUT LIMITATIONS OF STANDARD TTL 481 9.12 LOGIC FUNCTIONS IN TTL 482
9.12.1 MULTI-EMITTER INPUT TRANSISTORS 482 9.12.2 TTL NAND GATES 482
9.12.3 INPUT CLAMPING DIODES 483 9.13 SCHOTTKY-CLAMPED TTL 484 9.14
COMPARISON OF THE POWER-DELAY PRODUCTS OF ECL AND TTL 485 9.15 BICMOS
LOGIC 486 9.15.1 BICMOS BUFFERS 487 9.15.2 BINMOS INVERTERS 488 9.15.3
BICMOS LOGIC GATES 490 SUMMARY 491 KEY TERMS 492 REFERENCE 493
ADDITIONAL READING 493 PROBLEMS 493 PART THREE ANALOG CIRCUIT DESIGN
CHAPTER 10 ANALOG SYSTEMS 505 10.1 - AN EXAMPLE OF AN ANALOG ELECTRONIC
SYSTEM 506 10.2 AMPLIFICATION 507 10.2.1 VOLTAGE GAIN 508 10.2.2 CURRENT
GAIN 508 10.2.3 POWER GAIN 509 10.2.4 THE DECIBEL SCALE 509 XII CONTENTS
10.3 AMPLIFIER BIASING FOR LINEAR OPERATION 510 10.4 DISTORTION IN
AMPLIFIERS 512 10.5 TWD-PORT MODELS FOR AMPLIFIERS 513 10.5.1 THE
G-PARAMETERS 515 10.6 MISMATCHED SOURCE AND LOAD RESISTANCES 519 10.7
AMPLIFIER TRANSFER FUNCTIONS AND FREQUENCY RESPONSE 520 10.7.1 BODE
PLOTS 521 10.7.2 THE LOW-PASS AMPLIFIER 521 10.7.3 THE HIGH-PASS
AMPLIFIER 526 10.7.4 BAND-PASS AMPLIFIERS 528 10.7.5 NARROW-BAND OR
HIGH-Q BAND-PASS AMPLIFIERS 530 10.7.6 BAND-REJECTION AMPLIFIERS 531
10.7.7 THE ALL-PASS FUNCTION 532 10.7.8 MORE COMPLEX TRANSFER FUNCTIONS
532 SUMMARY 534 KEY TERMS 535 REFERENCES 536 PROBLEMS 536 CHAPTER 11
IDEAL OPERATIONAL AMPLIFIERS 541 11.1 THE DIFFERENTIAL AMPLIFIER 542
11.1.1 DIFFERENTIAL AMPLIFIER MODEL 542 11.1.2 THE IDEAL DIFFERENTIAL
AMPLIFIER 544 11.2 THE IDEAL OPERATIONAL AMPLIFIER 545 11.2.1
ASSUMPTIONS FOR IDEAL OPERATIONAL AMPLIFIER ANALYSIS 545 11.3 ANALYSIS
OF CIRCUITS CONTAINING IDEAL OPERATIONAL AMPLIFIERS 546 11.3.1 THE
INVERTING AMPLIFIER 546 11.3.2 THE NONINVERTING AMPLIFIER 550 11.3.3 THE
UNITY-GAIN BUFFER, OR VOLTAGE FOLLOWER 552 11.3.4 THE SUMMING AMPLIFIER
554 11.3.5 THE DIFFERENCE AMPLIFIER 556 11.3.6 THE INSTRUMENTATION
AMPLIFIER 559 11.3.7 AN ACTIVE LOW-PASS FILTER 561 11.3.8 THE INTEGRATOR
564 11.3.9 THE DIFFERENTIATOR 567 11.3.10 CASCADED AMPLIFIERS 568
11.3.11 AMPLIFIER TERMINOLOGY REVIEW 570 11.4 ACTIVE FILTERS 570 11.4.1
LOW-PASS FILTER 571 11.4.2 SENSITIVITY 575 11.4.3 A HIGH-PASS FILTER
WITH GAIN 575 11.4.4 BAND-PASS FILTER 577 11.4.5 THE TOW-THOMAS BIQUAD
579 11.4.6 MAGNITUDE AND FREQUENCY SCALING 582 11.5 NONLINEAR CIRCUIT
APPLICATIONS 584 11.5.1 A PRECISION HALF-WAVE RECTIFIER 585 11.5.2
NONSATURATING PRECISION-RECTIFIER CIRCUIT 586 11.5.3 AN AC VOLTMETER 587
11.6 CIRCUITS USING POSITIVE FEEDBACK 587 11.6.1 THE COMPARATOR AND
SCHMITT TRIGGER 588 11.6.2 THE ASTABLE MULTIVIBRATOR 589 11.6.3 THE
MONOSTABLE MULTIVIBRATOR OR ONE SHOT 593 SUMMARY 594 KEY TERMS 595
REFERENCES 596 ADDITIONAL READING 597 PROBLEMS 597 CHAPTER 12
CHARACTERISTICS AND LIMITATIONS OF OPERATIONAL AMPLIFIERS 610 12.1 GAIN,
INPUT RESISTANCE, AND OUTPUT RESISTANCE 611 12.1.1 FINITE OPEN-LOOP GAIN
611 12.1.2 GAIN ERROR 612 12.1.3 NONZERO OUTPUT RESISTANCE 614 12.1.4
FINITE INPUT RESISTANCE 618 12.1.5 SUMMARY OF NONIDEAL INVERTING AND
NONINVERFING AMPLIFIERS 622 12.2 COMMON-MODE REJECTION AND INPUT
RESISTANCE 622 12.2.1 FINITE COMMON-MODE REJECTION RATIO 622 12.2.2 WHY
IS CMRR IMPORTANT? 623 12.2.3 VOLTAGE-FOLLOWER GAIN ERROR DUE TO CMRR
626 12.2.4 COMMON-MODE INPUT RESISTANCE 628 12.3 DC ERROR SOURCES AND
OUTPUT RANGE LIMITATIONS 629 * 12.3.1 INPUT-OFFSET VOLTAGE 629 12.3.2
OFFSET-VOLTAGE ADJUSTMENT 631 12.3.3 AN ALTERNATE INTERPRETATION OF CMRR
631 12.3.4 INPUT-BIAS AND OFFSET CURRENTS 631 12.3.5 OUTPUT VOLTAGE AND
CURRENT LIMITS 634 12.4 FREQUENCY RESPONSE AND BANDWIDTH OF OPERATIONAL
AMPLIFIERS 638 12.4.1 FREQUENCY RESPONSE OF THE NONINVERTING AMPLIFIER
641 12.4.2 INVERTING AMPLIFIER FREQUENCY RESPONSE 643 12.4.3 FREQUENCY
RESPONSE OF CASCADED AMPLIFIERS 645 CONTENTS XIII 12.4.4 LARGE-SIGNAL
LIMITATIONS*SLEW RATE AND FULL-POWER BANDWIDTH 652 12.4.5 MACRO MODEL
FOR OPERATIONAL AMPLIFIER FREQUENCY RESPONSE 653 12.4.6 COMPLETE OP AMP
MACRO MODELS IN SPICE 654 12.4.7 EXAMPLES OF COMMERCIAL GENERAL-PURPOSE
OPERATIONAL AMPLIFIERS 654 SUMMARY 657 KEY TERMS 658 REFERENCES 658
ADDITIONAL READING 658 PROBLEMS 658 CHAPTER 13 SMALL-SIGNAL MODELING AND
LINEAR AMPLIFICATION*INVERTING AMPLIFIERS 668 13.1 THE TRANSISTOR AS AN
AMPLIFIER 669 13.1.1 THE BJT AMPLIFIER 670 13.1.2 THE MOSFET AMPLIFIER
671 13.2 COUPLING AND BYPASS CAPACITORS 672 13.3 CIRCUIT ANALYSIS USING
DC AND AC EQUIVALENT CIRCUITS 673 13.3.1 MENU FOR DC AND AC ANALYSIS 674
13.4 INTRODUCTION TO SMALL-SIGNAL MODELING 677 13.4.1 GRAPHICAL
INTERPRETATION OF THE SMALL-SIGNAL BEHAVIOR OF THE DIODE 678 13.4.2
SMALL-SIGNAL MODELING OF THE DIODE 679 13.5 SMALL-SIGNAL MODELS FOR
BIPOLAR JUNCTION TRANSISTORS 680 13.5.1 THE HYBRID-PI MODEL 682 13.5.2
GRAPHICAL INTERPRETATION OF THE TRANSCONDUCTANCE 683 13.5.3 SMALL-SIGNAL
CURRENT GAIN 683 13.5.4 THE INTRINSIC VOLTAGE GAIN OF THE BJT 684 13.5.5
EQUIVALENT FORMS OF THE SMALL-SIGNAL MODEL 685 13.5.6 SIMPLIFIED HYBRID
PI MODEL 686 13.5.7 DEFINITION OF A SMALL SIGNAL FOR THE BIPOLAR
TRANSISTOR 686 13.5.8 ^SMALL-SIGNAL MODEL FOR THE PNP TRANSISTOR 687
13.5.9 AC ANALYSIS VERSUS TRANSIENT ANALYSIS IN SPICE 688 13.6 THE BJT
COMMON-EMITTER (C-E) AMPLIFIER 688 13.6.1 TERMINAL VOLTAGE GAIRI 600
13.6.2 INPUT RESISTANCE $38 13.6.3 SIGNAL SOURCE VOTTA^#LN 691 13.7
IMPORTANT LIMITS AND MODEL SIMPLIFICATIONS 691 13.7.1 ZERO RESISTANCE IN
THE EMITTER 691 13.7.2 A DESIGN GUIDE FOR THE COMMON-EMITTER AMPLIFIER
WITH R E =O 692 13.7.3 COMMON-EMITTER VOLTAGE GAIN FOR LARGE EMITTER
RESISTANCE 693 13.7.4 SMALL-SIGNAL LIMIT FOR THE COMMON-EMITTER
AMPLIFIER 693 13.7.5 RESISTANCE AT THE COLLECTOR OF THE BIPOLAR
TRANSISTOR 697 13.7.6 OUTPUT RESISTANCE OF THE OVERALL COMMON-EMITTER
AMPLIFIER 699 13.7.7 TERMINAL CURRENT GAIN FOR THE COMMON-EMITTER
AMPLIFIER 701 13.8 SMALL-SIGNAL MODELS FOR FIELD-EFFECT TRANSISTORS 701
13.8.1 SMALL-SIGNAL MODEL FOR THE MOSFET 701 13.8.2 INTRINSIC VOLTAGE
GAIN OF THE MOSFET 703 13.8.3 DEFINITION OF SMALL-SIGNAL OPERATION FOR
THE MOSFET 704 13.8.4 BODY EFFECT IN THE FOUR-TERMINAL MOSFET 704 13.8.5
SMALL-SIGNAL MODEL FOR THE PMOS TRANSISTOR 705 13.9 SUMMARY AND
COMPARISON OF THE SMALL-SIGNAL MODELS OF THE BJT AND FET 706 13.10 THE
COMMON-SOURCE AMPLIFIER 709 13.10.1 COMMON-SOURCE TERMINAL VOLTAGE GAIN
710 13.10.2 SIGNAL SOURCE VOLTAGE GAIN FOR THE COMMON-SOURCE AMPLIFIER
711 13.10.3 COMMON-SOURCE VOLTAGE GAIN FOR LARGE VALUES OF R S 711
13.10.4 ZERO RESISTANCE IN THE SOURCE 711 13.10.5 A DESIGN GUIDE FOR THE
CO/NMON-SOURCE AMPLIFIER WITH R S - O 714 13.10.6 SMALL-SIGNAL LIMIT FOR
THE COMMON-SOURCE AMPLIFIER 714 13.10.7 INPUT RESISTANCES OF THE
COMMON-EMITTER AND COMMON-SOURCE AMPLIFIERS 717 13.10.8 COMMON-EMITTER
AND COMMON-SOURCE OUTPUT RESISTANCES 720 13.11 EXAMPLES OF
COMMON-EMITTER AND COMMON-SOURCE AMPLIFIERS 721 13.11.1 A COMMON-EMITTER
AMPLIFIER 722 13.11.2 AC VERSUS TRANSIENT ANALYSIS IN SPICE-ANOTHER
VISIT 726 XIV CONTENTS 13.11.3 A MOSFET COMMON-SOURCE AMPLIFIER 726
13.11.4 COMPARISON OF THE TWO AMPLIFIER EXAMPLES 731 13.11.5
COMMON-EMITTER AND COMMON-SOURCE AMPLIFIER SUMMARY 731 13.11.6 FEEDBACK
IN THE INVERTING AMPLIFIERS 732 13.11.7 GUIDELINES FOR NEGLECTING THE
TRANSISTOR OUTPUT RESISTANCE 732 13.12 AMPLIFIER POWER AND SIGNAL RANGE
733 13.12.1 POWER DISSIPATION 733 13.12.2 SIGNAL RANGE 734 SUMMARY 737
KEY TERMS 738 PROBLEMS 738 CHAPTER 14 SINGLE-TRANSISTOR AND MULTISTAGE
AC-COUPLED AMPLIFIERS 750 14.1 AMPLIFIER CLASSIFICATION 751 14.1.1
SIGNAL INJECTION AND EXTRACTION-THE BJT 751 14.1.2 SIGNAL INJECTION AND
EXTRACTION-THE FET 752 14.1.3 COMMON-EMITTER (C-E) AND COMMON-SOURCE
(C-S) AMPLIFIERS 753 14.1.4 COMMON-COLLECTOR (C-C) AND COMMON-DRAIN
(C-D) TOPOLOGIES 754 14.1.5 COMMON-BASE (C-B) AND COMMON-GATE (C-G)
AMPLIFIERS 756 14.1.6 SMALL-SIGNAL MODEL REVIEW 757 14.2 INVERTING
AMPLIFIERS*COMMON-EMITTER AND COMMON-SOURCE CIRCUITS 757 14.2.1
COMMON-EMITTER AND COMMON-SOURCE AMPLIFIER CHARACTERISTICS 758 14.2.2
C-E/C-S AMPLIFIER SUMMARY 762 14.2.3 EQUIVALENT TRANSISTOR
REPRESENTATION OF THE GENERALIZED C-E/C-S TRANSISTOR 762 14.3 FOLLOWER
CIRCUITS*COMMON-COLLECTOR AND COMMON-DRAIN AMPLIFIERS 763 14.3.1
TERMINAL VOLTAGE GAIN 763 14.3.2 RESISTANCE 764 14.3.3 SIGNAL SOURCE
VOLTAGE GAIN 764 14.3.4 FOLLOWER SIGNAL RANGE 767 14.3.5 RESISTANCE AT
THE EMITTER TERMINAL 767 14.3.6 CURRENT GAIN 770 14.3.7 C-C/C-D
AMPLIFIER SUMMARY 770 14.4 NONINVERTING AMPLIFIERS*COMMON-BASE AND
COMMON-GATE CIRCUITS 771 14.4.1 TERMINAL VOLTAGE GAIN AND INPUT
RESISTANCE 771 14.4.2 SIGNAL SOURCE VOLTAGE GAIN 772 14.4.3 INPUT SIGNAL
RANGE 773 14.4.4 RESISTANCE AT THE COLLECTOR AND DRAIN TERMINALS 774
14.4.5 CURRENT GAIN 775 14.4.6 OVERALL INPUT AND OUTPUT RESISTANCES FOR
THE NONINVERTING AMPLIFIERS 775 14.4.7 C-B/C-G AMPLIFIER SUMMARY 778
14.5 AMPLIFIER PROTOTYPE REVIEW AND COMPARISON 778 14.5.1 THE BJT
AMPLIFIERS 779 14.5.2 THE FET AMPLIFIERS 781 14.6 COUPLING AND BYPASS
CAPACITOR DESIGN 786 14.6.1 COMMON-EMITTER AND COMMON-SOURCE AMPLIFIERS
786 14.6.2 COMMON-COLLECTOR AND COMMON-DRAIN AMPLIFIERS 790 14.6.3
COMMON-BASE AND COMMON-GATE AMPLIFIERS 793 14.6.4 SETTING LOWER CUTOFF
FREQUENCY F L 796 14.7 AMPLIFIER DESIGN EXAMPLES 797 14.7.1 MONTE CARLO
EVALUATION OF THE COMMON-BASE AMPLIFIER DESIGN 806- 14.8 MULTISTAGE
AC-COUPLED AMPLIFIERS 811 14.8.1 A THREE-STAGE AC-COUPLED AMPLIFIER 811
14.8.2 VOLTAGE GAIN 813 14.8.3 INPUT RESISTANCE 815 14.8.4 SIGNAL SOURCE
VOLTAGE GAIN 815 14.8.5 OUTPUT RESISTANCE 815 14.8.6 CURRENT AND POWER
GAIN 816 14.8.7 INPUT SIGNAL RANGE 817 14.8.8 IMPROVING AMPLIFIER
VOLTAGE GAIN 820 14.8.9 ESTIMATING THE LOWER CUTOFF FREQUENCY OF THE
MULTISTAGE AMPLIFIER 820 SUMMARY 822 KEY TERMS 823 ADDITIONAL READING
824 PROBLEMS 824 CHAPTER 15 DIFFERENTIAL AMPLIFIERS AND OPERATIONAL
AMPLIFIER DESIGN 838 15.1 DIFFERENTIAL AMPLIFIERS 839 15.1.1 BIPOLAR AND
MOS DIFFERENTIAL AMPLIFIERS 840 CONTENTS XV 15.1.2 DC ANALYSIS OF THE
BIPOLAR DIFFERENTIAL AMPLIFIER 840 15.1.3 TRANSFER CHARACTERISTIC FOR
THE BIPOLAR DIFFERENTIAL AMPLIFIER 842 15.1.4 AC ANALYSIS OF THE BIPOLAR
DIFFERENTIAL AMPLIFIER 843 15.1.5 DIFFERENTIAL-MODE GAIN AND INPUT
RESISTANCE 844 15.1.6 COMMON-MODE GAIN AND INPUT RESISTANCE 846 15.1.7
COMMON-MODE REJECTION RATIO (CMRR) 848 15.1.8 ANALYSIS USING
DIFFERENTIAL- AND COMMON-MODE HALF-CIRCUITS 849 15.1.9 BIASING WITH
ELECTRONIC CURRENT SOURCES 852 15.1.10 MODELING THE ELECTRONIC CURRENT
SOURCE IN SPICE 853 15.1.11 DC ANALYSIS OF THE MOSFET DIFFERENTIAL
AMPLIFIER 853 15.1.12 DIFFERENTIAL-MODE INPUT SIGNALS 855 15.1.13
SMALL-SIGNAL TRANSFER CHARACTERISTIC FOR THE MOS DIFFERENTIAL AMPLIFIER
856 15.1.14 COMMON-MODE INPUT SIGNALS 856 15.1.15 TWO-PORT MODEL FOR
DIFFERENTIAL PAIRS 857 15.2 EVOLUTION TO BASIC OPERATIONAL AMPLIFIERS
861 15.2.1 A TWO-STAGE PROTOTYPE FOR AN OPERATIONAL AMPLIFIER 861 15.2.2
IMPROVING THE OP AMP VOLTAGE GAIN 867 15.2.3 OUTPUT RESISTANCE REDUCTION
868 15.2.4 A CMOS OPERATIONAL AMPLIFIER PROTOTYPE 872 15.2.5 BICMOS
AMPLIFIERS 873 15.3 OUTPUT STAGES 874 15.3.1 THE SOURCE FOLLOWER*A
CLASS-A OUTPUT STAGE 874 15.3.2 EFFICIENCY OF CLASS-A AMPLIFIERS 876
15.3.3 CLASS-B PUSH-PULL OUTPUT STAGE 876 15.3.4 CLASS-AB AMPLIFIERS 878
15.3.5 CLASS-AB OUTPUT STAGES FOR ,. OPERATIONAL AMPLIFIERS 880 15.3.6'
SHORT-CIRCUIT PROTECTION 880 15.3.7 TRANSFORMER COUPLING 881 15.4
ELECTRONIC CURRENT SOURCES 884 15.4.1 SINGLE-TRANSISTOR CURRENT SOURCES
885 15.4.2 FIGURE OF MERIT FOR CURRENT SOURCES 885 15.4.3 HIGHER OUTPUT
RESISTANCE SOURCES 886 15.4.4 CURRENT SOURCE DESIGN EXAMPLES 886 15.5
CIRCUIT ELEMENT MATCHING 893 15.6 CURRENT MIRRORS 894 15.6.1 DC ANALYSIS
OF THE MOS TRANSISTOR CURRENT MIRROR 894 15.6.2 CHANGING THE MOS MIRROR
RATIO 897 15.6.3 DC ANALYSIS OF THE BIPOLAR TRANSISTOR CURRENT MIRROR
897 15.6.4 ALTERING THE BJT CURRENT MIRROR RATIO 899 15.6.5 MULTIPLE
CURRENT SOURCES 900 15.6.6 BUFFERED CURRENT MIRROR 902 15.6.7 OUTPUT
RESISTANCE OF THE CURRENT MIRRORS 902 15.6.8 TWO-PORT MODEL FOR THE
CURRENT MIRROR 903 15.6.9 THE WIDLAR CURRENT SOURCE 906 15.6.10 THE MOS
VERSION OF THE WIDLAR SOURCE 907 15.7 HIGH-OUTPUT-RESISTANCE CURRENT
MIRRORS 909 15.7.1 THE WILSON CURRENT SOURCES 909 15.7.2 OUTPUT
RESISTANCE OF THE WILSON SOURCE 911 15.7.3 CASCODE CURRENT SOURCES 912
15.7.4 OUTPUT RESISTANCE OF THE CASCODE SOURCES 913 15.7.5 CURRENT
MIRROR SUMMARY 914 15.8 REFERENCE CURRENT GENERATION 917 15.8.1
SUPPLY-INDEPENDENT BIASING 917 15.8.2 A SUPPLY-INDEPENDENT MOS REFERENCE
CELL 920 15.9 THE CURRENT MIRROR AS AN ACTIVE LOAD 924 15.9.1 CMOS
DIFFERENTIAL AMPLIFIER WITH ACTIVE LOAD 924 15.9.2 BIPOLAR DIFFERENTIAL
AMPLIFIER WITH ACTIVE LOAD 931 15.10 ACTIVE LOGDS IN OPERATIONAL
AMPLIFIERS 935 15.10.1 CMOS OP AMP VOLTAGE GAIN 935 15.10.2 DC DESIGN
CONSIDERATIONS 936 15.10.3 BIPOLAR OPERATIONAL AMPLIFIERS 938 15.10.4
INPUT STAGE BREAKDOWN 939 15.11 THE 1XA741 OPERATIONAL AMPLIFIER 940
15.11.1 BIAS CIRCUITRY 941 15.11.2 DC ANALYSIS OF THE 741 INPUT STAGE
942 15.11.3 AC ANALYSIS OF THE 741 INPUT STAGE 945 15.11.4 VOLTAGE GAIN
OF THE COMPLETE AMPLIFIER 946 15.11.5 THE 741 OUTPUT STAGE 950 15.11.6
OUTPUT RESISTANCE 952 XVI CONTENTS 15.11.7 SHORT CIRCUIT PROTECTION 952
15.11.8 SUMMARY OF THE 1XA741 OPERATIONAL AMPLIFIER CHARACTERISTICS 952
SUMMARY 955 KEY TERMS 957 REFERENCES 957 ADDITIONAL READING 958 PROBLEMS
958 CHAPTER 16 FREQUENCY RESPONSE 985 16.1 AMPLIFIER FREQUENCY RESPONSE
986 16.1.1 LOW-FREQUENCY RESPONSE 987 16.1.2 ESTIMATING CO L IN THE
ABSENCE OF A DOMINANT POLE 987 16.1.3 HIGH-FREQUENCY RESPONSE 990 16.1.4
ESTIMATING A) H IN THE ABSENCE OF A DOMINANT POLE 990 16.2 DIRECT
DETERMINATION OF THE LOW-FREQUENCY POLES AND ZEROS*THE COMMON-SOURCE
AMPLIFIER 991 16.3 ESTIMATION OF CO L USING THE SHORT-CIRCUIT
TIME-CONSTANT METHOD 996 16.3.1 ESTIMATE OF (O L FOR THE COMMON-EMITTER
AMPLIFIER 997 16.3.2 ESTIMATE OF CO L FOR THE COMMON-SOURCE AMPLIFIER
1001 16.3.3 ESTIMATE OF CO L FOR THE COMMON-BASE AMPLIFIER 1002 16.3.4
ESTIMATE OF CO L FOR THE COMMON-GATE AMPLIFIER 1003 16.3.5 ESTIMATE OF
A L FOR THE COMMON-COLLECTOR AMPLIFIER 1004 16.3.6 ESTIMATE OF CO L FOR
THE COMMON-DRAIN AMPLIFIER 1004 16.4 TRANSISTOR MODELS AT HIGH
FREQUENCIES 1005 16.4.1 FREQUENCY-DEPENDENT HYBRID-PI MODEL FOR THE
BIPOLAR TRANSISTOR 1005 16.4.2 MODELING C N AND C^ IN SPICE 1006 16.4.3
UNITY-GAIN FREQUENCY F T 1006 16.4.4 HIGH-FREQUENCY MODEL FOR THE FET
1009 16.4.5 MODELING C GS AND C GD IN SPICE 1010 16.4.6 CHANNEL
LENGTHJIEPENDENCE OF/R 1010 16.4.7 LIMITATIONS OF THE HIGH-FREQUENCY
MODELS 1012 16.5 BASE RESISTANCE IN THE HYBRID-PI MODEL 1012 16.5.1
EFFECT OF BASE RESISTANCE ON MIDBAND AMPLIFIERS 1013 16.6 HIGH-FREQUENCY
COMMON-EMITTER AND COMMON-SOURCE AMPLIFIER ANALYSIS 1015 16.6.1 THE
MILLER EFFECT 1016 16.6.2 COMMON-EMITTER AND COMMON-SOURCE AMPLIFIER
HIGH-FREQUENCY RESPONSE 1017 16.6.3 DIRECT ANALYSIS OF THE
COMMON-EMITTER TRANSFER CHARACTERISTIC 1019 16.6.4 POLES OF THE
COMMON-EMITTER AMPLIFIER 1020 16.6.5 DOMINANT POLE FOR THE COMMON-SOURCE
AMPLIFIER 1023 16.6.6 ESTIMATION OF (O H USING THE OPEN-CIRCUIT
TIME-CONSTANT METHOD 1024 16.6.7 COMMON-SOURCE AMPLIFIER WITH SOURCE
DEGENERATION RESISTANCE 1027 16.6.8 POLES OF THE COMMON-EMITTER WITH
EMITTER DEGENERATION RESISTANCE 1029 16.7 COMMON-BASE AND COMMON-GATE
AMPLIFIER HIGH-FREQUENCY RESPONSE 1031 16.8 COMMON-COLLECTOR AND
COMMON-DRAIN AMPLIFIER HIGH-FREQUENCY RESPONSE 1034 16.9 SINGLE-STAGE
AMPLIFIERHIGH-FREQUENCY RESPONSE SUMMARY 1036 16.9.1 AMPLIFIER
GAIN-BANDWIDTH LIMITATIONS 1036 16.10 FREQUENCY RESPONSE OF MULTISTAGE
AMPLIFIERS 1037 16.10.1 DIFFERENTIAL AMPLIFIER 1038 16.10.2 THE
COMMON-COLLECTOR/COMMON- BASE CASCADE 1039 16.10.3 HIGH-FREQUENCY
RESPONSE OF THE CASCODE AMPLIFIER 1041 16.10.4 CUTOFF FREQUENCY FOR THE
CURRENT MIRROR 1042 16.10.5 THREE-STAGE AMPLIFIER EXAMPLE 1043 16.11
TUNED AMPLIFIERS 1050 16.11.1 SINGLE-TUNED AMPLIFIER 1050 16.11.2 USE OF
A TAPPED INDUCTOR*THE AUTO TRANSFORMER 1053 16.11.3 MULTIPLE TUNED
CIRCUITS*SYNCHRONOUS AND STAGGER TUNING 1054 SUMMARY 1056 KEY TERMS 1057
REFERENCE 1058 PROBLEMS 1058 CONTENTS XVII CHAPTER 17 FEEDBACK,
STABILITY, AND OSCILLATORS 1068 17.1 CLASSIC FEEDBACK SYSTEMS 1069 17.2
FEEDBACK AMPLIFIER DESIGN USING TWO-PORT NETWORK THEORY 1070 17.3
VOLTAGE AMPLIFIERS*SERIES-SHUNT FEEDBACK 1071 17.3.1 VOLTAGE GAIN
CALCULATION 1072 17.3.2 INPUT RESISTANCE 1074 17.3.3 OUTPUT RESISTANCE
1074 17.4 TRANSRESISTANCE AMPLIFIERS*SHUNT-SHUNT FEEDBACK 1078 17.4.1
TRANSRESISTANCE ANALYSIS 1079 17.4.2 INPUT RESISTANCE 1081 17.4.3 OUTPUT
RESISTANCE 1081 17.5 CURRENT AMPLIFIERS*SHUNT-SERIES FEEDBACK 1086
17.5.1 CURRENT GAIN CALCULATION 1086 17.5.2 INPUT RESISTANCE 1088 17.5.3
OUTPUT RESISTANCE 1089 17.6 TRANSCONDUCTANCE AMPLIFIERS*SERIES-SERIES
FEEDBACK 1090 17.6.1 TRANSCONDUCTANCE ANALYSIS 1090 17.6.2 INPUT AND
OUTPUT RESISTANCES 1092 17.7 COMMON ERRORS IN APPLYING TWO-PORT FEEDBACK
THEORY 1092 17.8 FINDING THE LOOP GAIN 1100 17.8.1 DIRECT CALCULATION OF
THE LOOP GAIN 1100 17.8.2 FINDING THE LOOP GAIN USING SUCCESSIVE VOLTAGE
AND CURRENT INJECTION 1102 17.8.3 SIMPLIFICATIONS 1105 17.9 BLACKMAN'S
THEOREM TO THE RESCUE 1107 17.10 USING FEEDBACK TO CONTROL FREQUENCY
RESPONSE 1114 17.11 STABILITY OF FEEDBACK AMPLIFIERS 1116 17.11.1 THE
NYQUIST PLOT 1116 17.11.2 FIRST-ORDER SYSTEMS 1117 17.11.3 SECOND-ORDER
SYSTEMS AND PHASE MARGIN 1118 17.11.4 THIRD-ORDER SYSTEMS AND GAIN
MARGIN 1119 17.11.5 DETERMINING STABILITY FROM THE BODE PLOT 1120 17.12
SINGLE-POLE OPERATIONAL AMPLIFIER COMPENSATION 1122 17.12.1 THREE-STAGE
OP AMP ANALYSIS 1123 17.12.2 TRANSMISSION ZEROS IN FET OP AMPS 1124
17.12.3 BIPOLAR AMPLIFIER COMPENSATION 1126 17.12.4 SLEW RATE OF THE
OPERATIONAL AMPLIFIER 1127 17.12.5 RELATIONSHIPS BETWEEN SLEW RATE AND
GAIN-BANDWIDTH PRODUCT 1128 17.13 OSCILLATORS 1137 17.13.1 THE
BARKHAUSEN CRITERIA FOR OSCILLATION 1137 17.13.2 OSCILLATORS EMPLOYING
FREQUENCY-SELECTIVE RC NETWORKS 1140 17.13.3 LC OSCILLATORS 1144 17.13.4
CRYSTAL OSCILLATORS 1146 SUMMARY 1151 KEY TERMS 1152 REFERENCES 1152
PROBLEMS 1153 APPENDIXES A STANDARD DISCRETE COMPONENT VALUES 1164 B
SOLID-STATE DEVICE MODELS AND SPICE SIMULATION PARAMETERS 1167 INDEX
1170 |
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| any_adam_object_boolean | 1 |
| author | Jaeger, Richard C. Blalock, Travis N. |
| author_facet | Jaeger, Richard C. Blalock, Travis N. |
| author_role | aut aut |
| author_sort | Jaeger, Richard C. |
| author_variant | r c j rc rcj t n b tn tnb |
| building | Verbundindex |
| bvnumber | BV022585156 |
| callnumber-first | T - Technology |
| callnumber-label | TK7874 |
| callnumber-raw | TK7874 |
| callnumber-search | TK7874 |
| callnumber-sort | TK 47874 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ZN 4900 |
| ctrlnum | (OCoLC)72353958 (DE-599)BVBBV022585156 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| discipline_str_mv | Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | 3. ed., internat. ed. |
| format | Book |
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| id | DE-604.BV022585156 |
| illustrated | Illustrated |
| index_date | 2024-07-02T18:16:25Z |
| indexdate | 2024-07-09T21:00:58Z |
| institution | BVB |
| isbn | 9780071102032 0071102035 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-015791352 |
| oclc_num | 72353958 |
| open_access_boolean | |
| owner | DE-634 DE-859 |
| owner_facet | DE-634 DE-859 |
| physical | XXIV, 1190 S. Ill., graph. Darst. |
| publishDate | 2008 |
| publishDateSearch | 2008 |
| publishDateSort | 2008 |
| publisher | McGraw-Hill |
| record_format | marc |
| spelling | Jaeger, Richard C. Verfasser aut Microelectronic circuit design Richard C. Jaeger ; Travis N. Blalock 3. ed., internat. ed. New York, NY McGraw-Hill 2008 XXIV, 1190 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Includes index Circuits intégrés - Conception et construction Circuits intégrés numériques - Conception et construction ram Circuits électroniques - Calcul - Manuels d'enseignement supérieur Elektronik devre tasarımı Entegre devreler - Tasarım ve yapım Semiconducteurs - Conception et construction Yarı iletkenler - Tasarım ve yapım Électronique de l'état solide Électronique numérique Electronic circuit design Integrated circuits Design and construction Semiconductors Design and construction Logische Schaltung (DE-588)4131023-8 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf Elektronische Schaltung (DE-588)4113419-9 gnd rswk-swf Mikroelektronik (DE-588)4039207-7 gnd rswk-swf Elektronische Schaltung (DE-588)4113419-9 s DE-604 Logische Schaltung (DE-588)4131023-8 s Entwurf (DE-588)4121208-3 s Mikroelektronik (DE-588)4039207-7 s 1\p DE-604 Blalock, Travis N. Verfasser aut http://www.ulb.tu-darmstadt.de/tocs/189035277.pdf Inhaltsverzeichnis OEBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=015791352&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Jaeger, Richard C. Blalock, Travis N. Microelectronic circuit design Circuits intégrés - Conception et construction Circuits intégrés numériques - Conception et construction ram Circuits électroniques - Calcul - Manuels d'enseignement supérieur Elektronik devre tasarımı Entegre devreler - Tasarım ve yapım Semiconducteurs - Conception et construction Yarı iletkenler - Tasarım ve yapım Électronique de l'état solide Électronique numérique Electronic circuit design Integrated circuits Design and construction Semiconductors Design and construction Logische Schaltung (DE-588)4131023-8 gnd Entwurf (DE-588)4121208-3 gnd Elektronische Schaltung (DE-588)4113419-9 gnd Mikroelektronik (DE-588)4039207-7 gnd |
| subject_GND | (DE-588)4131023-8 (DE-588)4121208-3 (DE-588)4113419-9 (DE-588)4039207-7 |
| title | Microelectronic circuit design |
| title_auth | Microelectronic circuit design |
| title_exact_search | Microelectronic circuit design |
| title_exact_search_txtP | Microelectronic circuit design |
| title_full | Microelectronic circuit design Richard C. Jaeger ; Travis N. Blalock |
| title_fullStr | Microelectronic circuit design Richard C. Jaeger ; Travis N. Blalock |
| title_full_unstemmed | Microelectronic circuit design Richard C. Jaeger ; Travis N. Blalock |
| title_short | Microelectronic circuit design |
| title_sort | microelectronic circuit design |
| topic | Circuits intégrés - Conception et construction Circuits intégrés numériques - Conception et construction ram Circuits électroniques - Calcul - Manuels d'enseignement supérieur Elektronik devre tasarımı Entegre devreler - Tasarım ve yapım Semiconducteurs - Conception et construction Yarı iletkenler - Tasarım ve yapım Électronique de l'état solide Électronique numérique Electronic circuit design Integrated circuits Design and construction Semiconductors Design and construction Logische Schaltung (DE-588)4131023-8 gnd Entwurf (DE-588)4121208-3 gnd Elektronische Schaltung (DE-588)4113419-9 gnd Mikroelektronik (DE-588)4039207-7 gnd |
| topic_facet | Circuits intégrés - Conception et construction Circuits intégrés numériques - Conception et construction Circuits électroniques - Calcul - Manuels d'enseignement supérieur Elektronik devre tasarımı Entegre devreler - Tasarım ve yapım Semiconducteurs - Conception et construction Yarı iletkenler - Tasarım ve yapım Électronique de l'état solide Électronique numérique Electronic circuit design Integrated circuits Design and construction Semiconductors Design and construction Logische Schaltung Entwurf Elektronische Schaltung Mikroelektronik |
| url | http://www.ulb.tu-darmstadt.de/tocs/189035277.pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=015791352&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT jaegerrichardc microelectroniccircuitdesign AT blalocktravisn microelectroniccircuitdesign |
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