CMOS RFIC design principles:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Boston [u.a.]
Artech House
2007
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| Schriftenreihe: | Artech House microwave library
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| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XV, 435 S. Ill., graph. Darst. 1 CD-ROM (12 cm) |
| ISBN: | 9781596931329 |
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Datensatz im Suchindex
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| adam_text | CMOS RFIC DESIGN PRINCIPLES ROBERT CAVERLY BOSTON|LONDON ARTECHHOUSE.COM
CONTENTS PREFACE ACKNOWLEDGMENTS CHAPTER 1 INTRODUCTION 1.1 HISTORICAL
PERSPECTIVE AND BACKGROUND 1.1.1 A (VERY) BRIEF HISTORY 1.1.2 BASIC
COMMUNICATION SYSTEM ARCHITECTURES 1.1.4 MULTIPLE USERS 1.2 REVIEW OF
SYSTEM FUNDAMENTALS 1.2.1 SYSTEM GAIN 1.2.2 SYSTEM NOISE FIGURE 1.2.3
SYSTEM NONLINEARITIES 1.2.4 LINK BUDGET 1.3 INTRODUCTION TO THE BOOK
REFERENCES SELECTED BIBLIOGRAPHY CHAPTER 2 CMOS INTEGRATED CIRCUIT
FUNDAMENTALS 2.1 REVIEW OF CMOS TECHNOLOGY 2.1.1 THE CMOS PHYSICAL
STRUCTURE 2.1.2 TECHNOLOGY SCALING 2.2 THE MOSFET 2.2.1 THE BASIC
-CHANNEL MOSFET 2.2.2 THE BASIC P-CHANNEL MOSFET 2.2.3 DESIGN NOTE: DE
CHARACTERISTICS 2.2.4 BASIC MOSFET RF EQUIVALENT CIRCUIT MODEL 2.2.5
ADVANCED MOSFET RF EQUIVALENT CIRCUIT MODEL 2.2.6 LINEAR OPERATION OF
THE MOSFET 2.3 MOSFET WEAK INVERSION AND ACCUMULATION OPERATION 2.3.1
ACCUMULATION MODE 2.3.2 WEAK INVERSION-SUBTHRESHOLD OPERATION 2.3.3
MOSFET VARIABLE-VOLTAGE CAPACITORS 2.4 REVIEW OF S-PARAMETERS 2.5 SPICE
MODELING OF CMOS RF CIRCUITS 2.5.1 SPICE LEVEL 3 XM XIV 1 1 1 8 16 17 17
18 30 39 43 46 47 49 49 49 51 52 52 55 58 58 61 70 74 74 76 79 81 85 85
V/7 2.5.2 BSIM PARAMETERS REFERENCES SELECTED BIBLIOGRAPHY CHAPTER 3 THE
PASSIVE COMPONENTS 3.1 CAPACITORS 3.1.1 METAL-INSULATOR-METAL CAPACITORS
3.1.2 RFIC CAPACITANCE RF EQUIVALENT CIRCUIT MODEL 3.1.3 CONCEPT OF
TOP/BOTTOM PLATE 3.1.4 MODELING EXAMPLE 3.2 INDUCTORS 3.2.1 ON-CHIP
INDUCTOR TYPES 3.2.2 PLANAR SPIRAL INDUCTOR RF EQUIVALENT CIRCUIT MODEL
3.2.3 REDUCTION OF INDUCTOR PARASITICS 3.2.4 MODELING EXAMPLE 3.2.5
TRANSFORMERS 3.2.6 TRANSMISSION LINES AND EQUIVALENTS 3.3
INTERCONNECTIONS 3.3.1 SIMPLE RC MODELS 3.3.2 TRANSMISSION LINE MODELS
3.4 RF MICROELECTRICAL MECHANICAL SYSTEMS 3.4.1 BASIC TYPES AND
OPERATION 3.4.2 ACTUATION VOLTAGE 3.4.3 MEMS SWITCHES 3.4.4 MEMS
RESONATORS 3.4.5 MEMS RELIABILITY AND PACKAGING 3.5 BASIC PACKAGING
3.5.1 ANATOMY OF AN RF PACKAGE 3.5.2 BOND WIRE INDUCTANCE 3.5.3 PACKAGE
AND PAED CAPACITANCE 3.5.4 THERMAL PROPERTIES*THERMAL RESISTANCE 3.6 RFIC
GROUNDING AND SIGNAL ISOLATION 3.6.1 THE GROUNDING PROBLEM 3.6.2 GROUND
AND ISOLATION IMPROVEMENTS REFERENCES SELECTED BIBLIOGRAPHY CHAPTER 4
SMALL-SIGNAL MOS AMPLIFIERS FOR RF 4.1 BASIC AMPLIFYING STRUCTURE 4.1.1
SINGLE FET WITH GENERALIZED LOAD 4.1.2 AMPLIFIER LOADING 4.1.3 EFFECT OF
PARASITICS 4.1.4 BASIC BEHAVIORAL MODEL 4.2 IMPROVEMENTS TO THE BASIC
AMPLIFYING STRUCTURE 4.2.1 CASCODE CIRCUITS IX 4.2.2 MULTIGATE FINGER
LAYOUTS 158 4.2.3 DIFFERENTIAL AMPLIFIERS 160 4.2.4 CURRENT REUSE 163
4.2.5 INPUT/OUTPUT IMPEDANCE MODELING EXAMPLE 165 4.3 AMPLIFIER AND
ON-CHIP BIASING 168 4.3.1 CURRENT MIRROR STRUCTURES 169 4.4 AMPLIFIER
MATCHING 179 4.4.1 CLASSIC LC 179 4.4.2 INDUCTIVE MATCHING: SOURCE
DEGENERATION 180 4.4.3 EXAMPLE OF LC MATCHING 183 4.4.4 FREQUENCY AGILE
MATCHING 184 4.5 LOW-NOISE AMPLIFIERS 190 4.5.1 NOISE MODELING FOR LNAS:
COMMON SOURCE LNA 190 4.5.2 NOISE MODELING FOR LNAS: COMMON GATE LNA 194
4.5.3 MODELING EXAMPLE 198 4.5.4 STABILITY CONSIDERATIONS IN MOS RFIC
AMPLIFIERS 200 REFERENCES 201 SELECTED BIBLIOGRAPHY 202 CHAPTER 5
ANCILLARY CMOS CIRCUITS AND MEASUREMENTS 203 5.1 ANCILLARY CMOS RFIC
CIRCUITS 203 5.1.1 NEGATIVE G M CIRCUITS (Q-ENHANCEMENT) 203 5.1.2
SOURCE FOLLOWER 206 5.1.3 SIMPLE AUTOMATIC GAIN CONTROL CIRCUITS 207 5.2
ANCILLARY PASSIVE CMOS RFIC CIRCUITS 213 5.2.1 GENERATION OF DE FROM
APPLIED RF POWER 213 5.2.2 ACTIVE INDUCTOR CIRCUITS 216 5.3 TUNED
AMPLIFIERS 218 5.3.1 LC TUNED FILTERS 219 5.3.2 SAW FILTERING 227 5.3.3
POLYPHASE FILTERS 227 5.4 MEASUREMENT CONCEPTS 230 REFERENCES 232
SELECTED BIBLIOGRAPHY 234 CHAPTER 6 CMOS OSCILLATOR CIRCUITS 235 6.1
REVIEW OF GENERAL FEEDBACK PRINCIPLES 236 6.1.1 GENERAL FEEDBACK SYSTEMS
236 6.1.2 GAIN/PHASE MARGINS 237 6.1.3 REACTANCE OSCILLATORS 238 6.1.4
CLASSIC REACTANCE OSCILLATOR CIRCUITS 243 6.2 FIXED-FREQUENCY
OSCILLATORS 245 6.2.1 SINGLE-STAGE AMPLIFIER WITH LC TANK LOAD 245 6.2.2
FEEDBACK CASCADE OF TWO AMPLIFIERS 247 6.2.3 NEGATIVE G M PERSPECTIVE
250 CONTENTS 6.2.4 COARSE FREQUENCY CONTROL 251 6.2.5 OSCILLATOR DESIGN
SPECIFICATIONS: VOLTAGE SWING AND Q 252 6.2.6 MODELING/DESIGN EXAMPLE
253 6.2.7 MECHANICAL-BASED OSCILLATORS 257 6.3 RING OSCILLATOR 261 6.3.1
BASIC CMOS INVERTER AND RING OSCILLATOR 261 6.3.2 SINGLE/DIFFERENTIAL
RING OSCILLATORS 263 6.4 VOLTAGE CONTROL OF OSCILLATORS 264 6.4.1
LOCATION IN THE TANK CIRCUIT 264 6.4.2 VARIABLE CAPACITANCE DEVICES 267
6.4.3 VOLTAGE CONTROL OF RING OSCILLATORS 268 6.4.4 VCO DESIGN EXAMPLE
269 6.5 OSCILLATOR PHASE NOISE AND ESTIMATION 270 6.5.1 LC TANK PHASE
NOISE 272 6.5.2 RING OSCILLATOR PHASE NOISE 275 6.5.3 VCO CONTROL LINE
PHASE NOISE 276 6.5.4 PN EXAMPLE CALCULATION 276 REFERENCES 278 SELECTED
BIBLIOGRAPHY 279 CHAPTER 7 CMOS MIXER CIRCUITS 281 7.1 GENERAL MIXER
CONCEPTS 281 7.1.1 TERMINOLOGY 281 7.1.2 IDEAL PASSIVE MIXERS*WEAK
NONLINEARITY 284 7.1.3 IDEAL ACTIVE MIXERS*SWITCHING OR MULTIPLYING
MIXERS 285 7.1.4 SINGLE- AND DOUBLE-BALANCED MIXERS: GENERAL DEFINITIONS
287 7.2 SINGLE MOS MIXER TOPOLOGIES 288 7.2.1 CONCEPTUAL MOSFET MIXER (V
GS - V R ) 288 7.2.2 TRANSCONDUCTANCE MIXER 290 7.2.3 RESISTIVE MIXER
293 7.2.4 DESIGN EXAMPLE: TRANSCONDUCTANCE MIXER 295 7.3 BALANCED MOSFET
MIXERS 297 7.3.1 SINGLE BALANCED MIXER 300 7.3.2 DOUBLE BALANCED MIXER
301 7.3.3 MIXER NOISE 304 7.3.4 DESIGN EXAMPLE: SINGLE BALANCED MIXER
307 7.3.5 MIXER NONLINEARITIES 310 7.3.6 MIXER SUMMARY 311 7.4 IMAGE
REJECTION CIRCUIT TOPOLOGIES 311 7.4.1 ARCHITECTURES 312 7.5 I/Q MIXER
TOPOLOGIES 318 7.5.1 ARCHITECTURES 318 REFERENCES 320 SELECTED
BIBLIOGRAPHY 321 CONTENTS XI CHAPTER 8 CMOS PLLS AND FREQUENCY
SYNTHESIZERS 323 8.1 INTRODUCTION TO THE PHASE LOCK LOOP 323 8.1.1
DEFINITIONS AND BASIC OPERATION 323 8.1.2 PHASE DETECTION AND
PHASE-FREQUENCY DETECTION 326 8.1.3 LOOP FILTERS 334 8.1.4 PLL NOISE
BEHAVIOR 346 8.1.5 PLL BEHAVIORAL MODELING 349 8.2 FREQUENCY SYNTHESIS
352 8.2.1 PLL-BASED SYNTHESIZERS 352 8.2.2 DIRECT DIGITAL SYNTHESIS 360
REFERENCES 366 SELECTED BIBLIOGRAPHY 367 CHAPTER 9 CMOS POWER AMPLIFIERS
369 9.1 REVIEW OF AMPLIFIER TERMS 369 9.1.1 LINEAR 370 9.1.2 NONLINEAR
371 9.2 TRANSCONDUCTANCE AMPLIFIERS 373 9.2.1 CONDUCTION ANGLE 375 9.2.2
CLASS A AND B DESIGN EXAMPLES 383 9.3 SWITCHING AMPLIFIERS 388 9.3.1
CLASS E AMPLIFIERS 389 9.3.2 CLASS F AMPLIFIERS 397 9.4 OTHER AMPLIFIERS
401 9.4.1 DISTRIBUTED AMPLIFIERS 401 9.4.2 KAHN AND DOHERTY STRUCTURES
406 9.5 AMPLIFIER LINEARIZERS 409 9.5.1 BASIC AMPLIFIER LINEARIZATION
410 9.5.2 PREDISTORTION LINEARIZERS 411 9.5.3 FEED-FORWARD LINEARIZERS
412 REFERENCES 414 SELECTED BIBLIOGRAPHY 415 APPENDIX A SAMPLE SPICE-3
PARAMETERS 417 SAMPLE SPICE BSIM PARAMETERS 419 V-PARAMETERS OF THE
MOSFET MODEL 421 PARAMETER CONVERSION EQUATIONS FOR TWO-PORT NETWORKS
423 XII CONTENTS APPENDIX E CONSTANTS AND SOME PROPERTIES OF SILICON AND
CMOS-RELATED MATERIALS 425 ABOUT THE AUTHOR 427 INDEX 429
|
| adam_txt |
CMOS RFIC DESIGN PRINCIPLES ROBERT CAVERLY BOSTON|LONDON ARTECHHOUSE.COM
CONTENTS PREFACE ACKNOWLEDGMENTS CHAPTER 1 INTRODUCTION 1.1 HISTORICAL
PERSPECTIVE AND BACKGROUND 1.1.1 A (VERY) BRIEF HISTORY 1.1.2 BASIC
COMMUNICATION SYSTEM ARCHITECTURES 1.1.4 MULTIPLE USERS 1.2 REVIEW OF
SYSTEM FUNDAMENTALS 1.2.1 SYSTEM GAIN 1.2.2 SYSTEM NOISE FIGURE 1.2.3
SYSTEM NONLINEARITIES 1.2.4 LINK BUDGET 1.3 INTRODUCTION TO THE BOOK
REFERENCES SELECTED BIBLIOGRAPHY CHAPTER 2 CMOS INTEGRATED CIRCUIT
FUNDAMENTALS 2.1 REVIEW OF CMOS TECHNOLOGY 2.1.1 THE CMOS PHYSICAL
STRUCTURE 2.1.2 TECHNOLOGY SCALING 2.2 THE MOSFET 2.2.1 THE BASIC
-CHANNEL MOSFET 2.2.2 THE BASIC P-CHANNEL MOSFET 2.2.3 DESIGN NOTE: DE
CHARACTERISTICS 2.2.4 BASIC MOSFET RF EQUIVALENT CIRCUIT MODEL 2.2.5
ADVANCED MOSFET RF EQUIVALENT CIRCUIT MODEL 2.2.6 LINEAR OPERATION OF
THE MOSFET 2.3 MOSFET WEAK INVERSION AND ACCUMULATION OPERATION 2.3.1
ACCUMULATION MODE 2.3.2 WEAK INVERSION-SUBTHRESHOLD OPERATION 2.3.3
MOSFET VARIABLE-VOLTAGE CAPACITORS 2.4 REVIEW OF S-PARAMETERS 2.5 SPICE
MODELING OF CMOS RF CIRCUITS 2.5.1 SPICE LEVEL 3 XM XIV 1 1 1 8 16 17 17
18 30 39 43 46 47 49 49 49 51 52 52 55 58 58 61 70 74 74 76 79 81 85 85
V/7 2.5.2 BSIM PARAMETERS REFERENCES SELECTED BIBLIOGRAPHY CHAPTER 3 THE
PASSIVE COMPONENTS 3.1 CAPACITORS 3.1.1 METAL-INSULATOR-METAL CAPACITORS
3.1.2 RFIC CAPACITANCE RF EQUIVALENT CIRCUIT MODEL 3.1.3 CONCEPT OF
TOP/BOTTOM PLATE 3.1.4 MODELING EXAMPLE 3.2 INDUCTORS 3.2.1 ON-CHIP
INDUCTOR TYPES 3.2.2 PLANAR SPIRAL INDUCTOR RF EQUIVALENT CIRCUIT MODEL
3.2.3 REDUCTION OF INDUCTOR PARASITICS 3.2.4 MODELING EXAMPLE 3.2.5
TRANSFORMERS 3.2.6 TRANSMISSION LINES AND EQUIVALENTS 3.3
INTERCONNECTIONS 3.3.1 SIMPLE RC MODELS 3.3.2 TRANSMISSION LINE MODELS
3.4 RF MICROELECTRICAL MECHANICAL SYSTEMS 3.4.1 BASIC TYPES AND
OPERATION 3.4.2 ACTUATION VOLTAGE 3.4.3 MEMS SWITCHES 3.4.4 MEMS
RESONATORS 3.4.5 MEMS RELIABILITY AND PACKAGING 3.5 BASIC PACKAGING
3.5.1 ANATOMY OF AN RF PACKAGE 3.5.2 BOND WIRE INDUCTANCE 3.5.3 PACKAGE
AND PAED CAPACITANCE 3.5.4 THERMAL PROPERTIES*THERMAL RESISTANCE 3.6 RFIC
GROUNDING AND SIGNAL ISOLATION 3.6.1 THE GROUNDING PROBLEM 3.6.2 GROUND
AND ISOLATION IMPROVEMENTS REFERENCES SELECTED BIBLIOGRAPHY CHAPTER 4
SMALL-SIGNAL MOS AMPLIFIERS FOR RF 4.1 BASIC AMPLIFYING STRUCTURE 4.1.1
SINGLE FET WITH GENERALIZED LOAD 4.1.2 AMPLIFIER LOADING 4.1.3 EFFECT OF
PARASITICS 4.1.4 BASIC BEHAVIORAL MODEL 4.2 IMPROVEMENTS TO THE BASIC
AMPLIFYING STRUCTURE 4.2.1 CASCODE CIRCUITS IX 4.2.2 MULTIGATE FINGER
LAYOUTS 158 4.2.3 DIFFERENTIAL AMPLIFIERS 160 4.2.4 CURRENT REUSE 163
4.2.5 INPUT/OUTPUT IMPEDANCE MODELING EXAMPLE 165 4.3 AMPLIFIER AND
ON-CHIP BIASING 168 4.3.1 CURRENT MIRROR STRUCTURES 169 4.4 AMPLIFIER
MATCHING 179 4.4.1 CLASSIC LC 179 4.4.2 INDUCTIVE MATCHING: SOURCE
DEGENERATION 180 4.4.3 EXAMPLE OF LC MATCHING 183 4.4.4 FREQUENCY AGILE
MATCHING 184 4.5 LOW-NOISE AMPLIFIERS 190 4.5.1 NOISE MODELING FOR LNAS:
COMMON SOURCE LNA 190 4.5.2 NOISE MODELING FOR LNAS: COMMON GATE LNA 194
4.5.3 MODELING EXAMPLE 198 4.5.4 STABILITY CONSIDERATIONS IN MOS RFIC
AMPLIFIERS 200 REFERENCES 201 SELECTED BIBLIOGRAPHY 202 CHAPTER 5
ANCILLARY CMOS CIRCUITS AND MEASUREMENTS 203 5.1 ANCILLARY CMOS RFIC
CIRCUITS 203 5.1.1 NEGATIVE G M CIRCUITS (Q-ENHANCEMENT) 203 5.1.2
SOURCE FOLLOWER 206 5.1.3 SIMPLE AUTOMATIC GAIN CONTROL CIRCUITS 207 5.2
ANCILLARY PASSIVE CMOS RFIC CIRCUITS 213 5.2.1 GENERATION OF DE FROM
APPLIED RF POWER 213 5.2.2 ACTIVE INDUCTOR CIRCUITS 216 5.3 TUNED
AMPLIFIERS 218 5.3.1 LC TUNED FILTERS 219 5.3.2 SAW FILTERING 227 5.3.3
POLYPHASE FILTERS 227 5.4 MEASUREMENT CONCEPTS 230 REFERENCES 232
SELECTED BIBLIOGRAPHY 234 CHAPTER 6 CMOS OSCILLATOR CIRCUITS 235 6.1
REVIEW OF GENERAL FEEDBACK PRINCIPLES 236 6.1.1 GENERAL FEEDBACK SYSTEMS
236 6.1.2 GAIN/PHASE MARGINS 237 6.1.3 REACTANCE OSCILLATORS 238 6.1.4
CLASSIC REACTANCE OSCILLATOR CIRCUITS 243 6.2 FIXED-FREQUENCY
OSCILLATORS 245 6.2.1 SINGLE-STAGE AMPLIFIER WITH LC TANK LOAD 245 6.2.2
FEEDBACK CASCADE OF TWO AMPLIFIERS 247 6.2.3 NEGATIVE G M PERSPECTIVE
250 CONTENTS 6.2.4 COARSE FREQUENCY CONTROL 251 6.2.5 OSCILLATOR DESIGN
SPECIFICATIONS: VOLTAGE SWING AND Q 252 6.2.6 MODELING/DESIGN EXAMPLE
253 6.2.7 MECHANICAL-BASED OSCILLATORS 257 6.3 RING OSCILLATOR 261 6.3.1
BASIC CMOS INVERTER AND RING OSCILLATOR 261 6.3.2 SINGLE/DIFFERENTIAL
RING OSCILLATORS 263 6.4 VOLTAGE CONTROL OF OSCILLATORS 264 6.4.1
LOCATION IN THE TANK CIRCUIT 264 6.4.2 VARIABLE CAPACITANCE DEVICES 267
6.4.3 VOLTAGE CONTROL OF RING OSCILLATORS 268 6.4.4 VCO DESIGN EXAMPLE
269 6.5 OSCILLATOR PHASE NOISE AND ESTIMATION 270 6.5.1 LC TANK PHASE
NOISE 272 6.5.2 RING OSCILLATOR PHASE NOISE 275 6.5.3 VCO CONTROL LINE
PHASE NOISE 276 6.5.4 PN EXAMPLE CALCULATION 276 REFERENCES 278 SELECTED
BIBLIOGRAPHY 279 CHAPTER 7 CMOS MIXER CIRCUITS 281 7.1 GENERAL MIXER
CONCEPTS 281 7.1.1 TERMINOLOGY 281 7.1.2 IDEAL PASSIVE MIXERS*WEAK
NONLINEARITY 284 7.1.3 IDEAL ACTIVE MIXERS*SWITCHING OR MULTIPLYING
MIXERS 285 7.1.4 SINGLE- AND DOUBLE-BALANCED MIXERS: GENERAL DEFINITIONS
287 7.2 SINGLE MOS MIXER TOPOLOGIES 288 7.2.1 CONCEPTUAL MOSFET MIXER (V
GS - V R ) 288 7.2.2 TRANSCONDUCTANCE MIXER 290 7.2.3 RESISTIVE MIXER
293 7.2.4 DESIGN EXAMPLE: TRANSCONDUCTANCE MIXER 295 7.3 BALANCED MOSFET
MIXERS 297 7.3.1 SINGLE BALANCED MIXER 300 7.3.2 DOUBLE BALANCED MIXER
301 7.3.3 MIXER NOISE 304 7.3.4 DESIGN EXAMPLE: SINGLE BALANCED MIXER
307 7.3.5 MIXER NONLINEARITIES 310 7.3.6 MIXER SUMMARY 311 7.4 IMAGE
REJECTION CIRCUIT TOPOLOGIES 311 7.4.1 ARCHITECTURES 312 7.5 I/Q MIXER
TOPOLOGIES 318 7.5.1 ARCHITECTURES 318 REFERENCES 320 SELECTED
BIBLIOGRAPHY 321 CONTENTS XI CHAPTER 8 CMOS PLLS AND FREQUENCY
SYNTHESIZERS 323 8.1 INTRODUCTION TO THE PHASE LOCK LOOP 323 8.1.1
DEFINITIONS AND BASIC OPERATION 323 8.1.2 PHASE DETECTION AND
PHASE-FREQUENCY DETECTION 326 8.1.3 LOOP FILTERS 334 8.1.4 PLL NOISE
BEHAVIOR 346 8.1.5 PLL BEHAVIORAL MODELING 349 8.2 FREQUENCY SYNTHESIS
352 8.2.1 PLL-BASED SYNTHESIZERS 352 8.2.2 DIRECT DIGITAL SYNTHESIS 360
REFERENCES 366 SELECTED BIBLIOGRAPHY 367 CHAPTER 9 CMOS POWER AMPLIFIERS
369 9.1 REVIEW OF AMPLIFIER TERMS 369 9.1.1 LINEAR 370 9.1.2 NONLINEAR
371 9.2 TRANSCONDUCTANCE AMPLIFIERS 373 9.2.1 CONDUCTION ANGLE 375 9.2.2
CLASS A AND B DESIGN EXAMPLES 383 9.3 SWITCHING AMPLIFIERS 388 9.3.1
CLASS E AMPLIFIERS 389 9.3.2 CLASS F AMPLIFIERS 397 9.4 OTHER AMPLIFIERS
401 9.4.1 DISTRIBUTED AMPLIFIERS 401 9.4.2 KAHN AND DOHERTY STRUCTURES
406 9.5 AMPLIFIER LINEARIZERS 409 9.5.1 BASIC AMPLIFIER LINEARIZATION
410 9.5.2 PREDISTORTION LINEARIZERS 411 9.5.3 FEED-FORWARD LINEARIZERS
412 REFERENCES 414 SELECTED BIBLIOGRAPHY 415 APPENDIX A SAMPLE SPICE-3
PARAMETERS 417 SAMPLE SPICE BSIM PARAMETERS 419 V-PARAMETERS OF THE
MOSFET MODEL 421 PARAMETER CONVERSION EQUATIONS FOR TWO-PORT NETWORKS
423 XII CONTENTS APPENDIX E CONSTANTS AND SOME PROPERTIES OF SILICON AND
CMOS-RELATED MATERIALS 425 ABOUT THE AUTHOR 427 INDEX 429 |
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| discipline_str_mv | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV022523415 |
| illustrated | Illustrated |
| index_date | 2024-07-02T18:04:03Z |
| indexdate | 2024-07-09T20:59:27Z |
| institution | BVB |
| isbn | 9781596931329 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-015730123 |
| oclc_num | 148876360 |
| open_access_boolean | |
| owner | DE-29T DE-Aug4 |
| owner_facet | DE-29T DE-Aug4 |
| physical | XV, 435 S. Ill., graph. Darst. 1 CD-ROM (12 cm) |
| publishDate | 2007 |
| publishDateSearch | 2007 |
| publishDateSort | 2007 |
| publisher | Artech House |
| record_format | marc |
| series2 | Artech House microwave library |
| spelling | Caverly, Robert Verfasser aut CMOS RFIC design principles Robert Caverly Boston [u.a.] Artech House 2007 XV, 435 S. Ill., graph. Darst. 1 CD-ROM (12 cm) txt rdacontent n rdamedia nc rdacarrier Artech House microwave library Integrated circuits CMOS (DE-588)4010319-5 gnd rswk-swf Hochfrequenzschaltung (DE-588)4160147-6 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf CMOS (DE-588)4010319-5 s Hochfrequenzschaltung (DE-588)4160147-6 s Integrierte Schaltung (DE-588)4027242-4 s Schaltungsentwurf (DE-588)4179389-4 s DE-604 GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=015730123&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Caverly, Robert CMOS RFIC design principles Integrated circuits CMOS (DE-588)4010319-5 gnd Hochfrequenzschaltung (DE-588)4160147-6 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Schaltungsentwurf (DE-588)4179389-4 gnd |
| subject_GND | (DE-588)4010319-5 (DE-588)4160147-6 (DE-588)4027242-4 (DE-588)4179389-4 |
| title | CMOS RFIC design principles |
| title_auth | CMOS RFIC design principles |
| title_exact_search | CMOS RFIC design principles |
| title_exact_search_txtP | CMOS RFIC design principles |
| title_full | CMOS RFIC design principles Robert Caverly |
| title_fullStr | CMOS RFIC design principles Robert Caverly |
| title_full_unstemmed | CMOS RFIC design principles Robert Caverly |
| title_short | CMOS RFIC design principles |
| title_sort | cmos rfic design principles |
| topic | Integrated circuits CMOS (DE-588)4010319-5 gnd Hochfrequenzschaltung (DE-588)4160147-6 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Schaltungsentwurf (DE-588)4179389-4 gnd |
| topic_facet | Integrated circuits CMOS Hochfrequenzschaltung Integrierte Schaltung Schaltungsentwurf |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=015730123&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT caverlyrobert cmosrficdesignprinciples |