Parallel computer architecture: a hardware/software approach
Saved in:
| Main Authors: | , , |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
San Francisco, Calif.
Morgan Kaufmann
2006
|
| Edition: | [Repr.] |
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Physical Description: | XXIX, 1025 S. Ill., graph. Darst. |
| ISBN: | 1558603433 9781558603431 |
Staff View
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| 245 | 1 | 0 | |a Parallel computer architecture |b a hardware/software approach |c David E. Culler, Jaswinder Pal Singh with Anoop Gupta |
| 250 | |a [Repr.] | ||
| 264 | 1 | |a San Francisco, Calif. |b Morgan Kaufmann |c 2006 | |
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| 700 | 1 | |a Gupta, Anoop |e Verfasser |4 aut | |
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Record in the Search Index
| _version_ | 1804136444914040832 |
|---|---|
| adam_text | Contents
Foreword
Preface
Introduction
1.1
1.1.1
1.1.2
1.1.3
1.1.4
1.1.5
1.2
1.2.1
1.2.2
1.2.3
1.2.4
1.2.5
1.2.6
1.2.7
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.4
1.5
1.6
xii Contents
Parallel
2.1
2.1.1
2.1.2
2.1.3
2.1.4
2.2
2.2.1
2.2.2
2.2.3
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.4
2.5
Programming for Performance
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.2
3.2.1
3.2.2
3.2.3
Perspective
3.3
3.3.1
3.3.2
3.4
3.5
3.5.1
3.5.2
3.5.3
3.5.4
Contents xiii
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.6.6
3.6.7
3.6.8
3.7
3.8
Workload-Driven Evaluation
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.4
4.4.1
4.4.2
4.5
4.6
Shared Memory Multiprocessors
5.1
5.1.1
5.1.2
xiv Contents
5.2 Memory
5.2.1
5.2.2
5.3
5.3.1
5.3.2
5.3.3
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.5
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.5.6
5.6
5.7
5.8
Snoop-Based Multiprocessor Design
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.3
6.3.1
6.3.2
6.4
6.4.1
6.4.2
Contents
6.4.3
6.4.4
6.4.5
6.4.6
6.4.7
6.4.8
6.4.9
6.5
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
6.5.7
6.5.8
6.5.9
6.6
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.7
6.8
Scalable Multiprocessors
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.3
7.3.1
7.3.2
xvi Contents
7.3.3
7.3.4
7.4
7.4.1
7.4.2
7.4.3
7.5
7.5.1
7.5.2
7.6
7.6.1
7.6.2
7.6.3
7.7
7.7.1
7.7.2
7.8
7.8.1
7.8.2
7.8.3
7.8.4
7.9
7.9.1
7.9.2
7.10
7.11
8
8.1
8.2
8.2.1
8.2.2
8.2.3
8.3
8.3.1
8.3.2
8.3.3
8.4
8.4.1
8.4.2
Contents xvii
8.5
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.6
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
8.6.6
8.6.7
8.6.8
8.7
8.8
8.8.1
8.8.2
8.9
8.10
8.10.1
8.10.2
8.11
8.12
Hardware/Software Trade-Offs
9.1
9.1.1
9.1.2
9.1.3
9.1.4
9.2
9.2.1
9.2.2
9.3
9.3.1
9.3.2
9.3.3
9.3.4
xviii Contents
9.4
9.4.1
9.5
9.6
9.6.1
9.6.2
9.7
9.8
10
10.1
10.2
10.2.1
10.2.2
10.3
10.3.1
10.3.2
10.3.3
10.4
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
10.4.6
10.5
10.5.1
10.5.2
10.6
10.6.1
10.6.2
10.6.3
10.6.4
10.6.5
10.6.6
10.6.7
10.7
10.7.1
10.7.2
10.7.3
Contents xix
10.7.4 Output.
10.7.5
10.8
10.8.1 Parallel Computer Networks versus
10.8.2 Link-Level
10.8.3 End-to-End
10.9
10.9.1
10.9.2
10.9.3
10.9.4
10.9.5
10.10
10.11
11
11.1
11.1.1
11.1.2
11.1.3
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.3
11.3.1
11.4
11.4.1
11.4.2
11.4.3
11.5
11.5.1
11.5.2
11.5.3
11.6
11.6.1
11.6.2
11.6.3
11.6.4
XX
11.7
11.7.1
11.7.2
11.7.3
11.7.4
11.7.5
11.8
11.9
11.10
12
12.1
12.1.1
12.1.2
12.1.3
12.2
12.2.1
12.2.2
12.2.3
Appendix: Parallel Benchmark Suites
A.I ScaLapack
A.2 TPC
A.3 SPLASH
A.4
A.5 PARKBENCH
A.6 Other Ongoing Efforts
References
Index
|
| adam_txt |
Contents
Foreword
Preface
Introduction
1.1
1.1.1
1.1.2
1.1.3
1.1.4
1.1.5
1.2
1.2.1
1.2.2
1.2.3
1.2.4
1.2.5
1.2.6
1.2.7
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.4
1.5
1.6
xii Contents
Parallel
2.1
2.1.1
2.1.2
2.1.3
2.1.4
2.2
2.2.1
2.2.2
2.2.3
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.4
2.5
Programming for Performance
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.2
3.2.1
3.2.2
3.2.3
Perspective
3.3
3.3.1
3.3.2
3.4
3.5
3.5.1
3.5.2
3.5.3
3.5.4
Contents xiii
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.6.6
3.6.7
3.6.8
3.7
3.8
Workload-Driven Evaluation
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.4
4.4.1
4.4.2
4.5
4.6
Shared Memory Multiprocessors
5.1
5.1.1
5.1.2
xiv Contents
5.2 Memory
5.2.1
5.2.2
5.3
5.3.1
5.3.2
5.3.3
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.5
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.5.6
5.6
5.7
5.8
Snoop-Based Multiprocessor Design
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.3
6.3.1
6.3.2
6.4
6.4.1
6.4.2
Contents
6.4.3
6.4.4
6.4.5
6.4.6
6.4.7
6.4.8
6.4.9
6.5
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
6.5.7
6.5.8
6.5.9
6.6
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.7
6.8
Scalable Multiprocessors
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.3
7.3.1
7.3.2
xvi Contents
7.3.3
7.3.4
7.4
7.4.1
7.4.2
7.4.3
7.5
7.5.1
7.5.2
7.6
7.6.1
7.6.2
7.6.3
7.7
7.7.1
7.7.2
7.8
7.8.1
7.8.2
7.8.3
7.8.4
7.9
7.9.1
7.9.2
7.10
7.11
8
8.1
8.2
8.2.1
8.2.2
8.2.3
8.3
8.3.1
8.3.2
8.3.3
8.4
8.4.1
8.4.2
Contents xvii
8.5
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.6
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
8.6.6
8.6.7
8.6.8
8.7
8.8
8.8.1
8.8.2
8.9
8.10
8.10.1
8.10.2
8.11
8.12
Hardware/Software Trade-Offs
9.1
9.1.1
9.1.2
9.1.3
9.1.4
9.2
9.2.1
9.2.2
9.3
9.3.1
9.3.2
9.3.3
9.3.4
xviii Contents
9.4
9.4.1
9.5
9.6
9.6.1
9.6.2
9.7
9.8
10
10.1
10.2
10.2.1
10.2.2
10.3
10.3.1
10.3.2
10.3.3
10.4
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
10.4.6
10.5
10.5.1
10.5.2
10.6
10.6.1
10.6.2
10.6.3
10.6.4
10.6.5
10.6.6
10.6.7
10.7
10.7.1
10.7.2
10.7.3
Contents xix
10.7.4 Output.
10.7.5
10.8
10.8.1 Parallel Computer Networks versus
10.8.2 Link-Level
10.8.3 End-to-End
10.9
10.9.1
10.9.2
10.9.3
10.9.4
10.9.5
10.10
10.11
11
11.1
11.1.1
11.1.2
11.1.3
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.3
11.3.1
11.4
11.4.1
11.4.2
11.4.3
11.5
11.5.1
11.5.2
11.5.3
11.6
11.6.1
11.6.2
11.6.3
11.6.4
XX
11.7
11.7.1
11.7.2
11.7.3
11.7.4
11.7.5
11.8
11.9
11.10
12
12.1
12.1.1
12.1.2
12.1.3
12.2
12.2.1
12.2.2
12.2.3
Appendix: Parallel Benchmark Suites
A.I ScaLapack
A.2 TPC
A.3 SPLASH
A.4
A.5 PARKBENCH
A.6 Other Ongoing Efforts
References
Index |
| any_adam_object | 1 |
| any_adam_object_boolean | 1 |
| author | Culler, David E. Singh, Jaswinder Pal Gupta, Anoop |
| author_facet | Culler, David E. Singh, Jaswinder Pal Gupta, Anoop |
| author_role | aut aut aut |
| author_sort | Culler, David E. |
| author_variant | d e c de dec j p s jp jps a g ag |
| building | Verbundindex |
| bvnumber | BV022387744 |
| classification_rvk | ST 150 |
| ctrlnum | (OCoLC)633322644 (DE-599)BVBBV022387744 |
| discipline | Informatik |
| discipline_str_mv | Informatik |
| edition | [Repr.] |
| format | Book |
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| id | DE-604.BV022387744 |
| illustrated | Illustrated |
| index_date | 2024-07-02T17:13:20Z |
| indexdate | 2024-07-09T20:56:30Z |
| institution | BVB |
| isbn | 1558603433 9781558603431 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-015596630 |
| oclc_num | 633322644 |
| open_access_boolean | |
| owner | DE-355 DE-BY-UBR |
| owner_facet | DE-355 DE-BY-UBR |
| physical | XXIX, 1025 S. Ill., graph. Darst. |
| publishDate | 2006 |
| publishDateSearch | 2006 |
| publishDateSort | 2006 |
| publisher | Morgan Kaufmann |
| record_format | marc |
| spelling | Culler, David E. Verfasser aut Parallel computer architecture a hardware/software approach David E. Culler, Jaswinder Pal Singh with Anoop Gupta [Repr.] San Francisco, Calif. Morgan Kaufmann 2006 XXIX, 1025 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Computerarchitektur (DE-588)4048717-9 gnd rswk-swf Parallelverarbeitung (DE-588)4075860-6 gnd rswk-swf Parallelrechner (DE-588)4173280-7 gnd rswk-swf Parallelrechner (DE-588)4173280-7 s Computerarchitektur (DE-588)4048717-9 s DE-604 Parallelverarbeitung (DE-588)4075860-6 s Singh, Jaswinder Pal Verfasser aut Gupta, Anoop Verfasser aut Digitalisierung UB Regensburg application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=015596630&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Culler, David E. Singh, Jaswinder Pal Gupta, Anoop Parallel computer architecture a hardware/software approach Computerarchitektur (DE-588)4048717-9 gnd Parallelverarbeitung (DE-588)4075860-6 gnd Parallelrechner (DE-588)4173280-7 gnd |
| subject_GND | (DE-588)4048717-9 (DE-588)4075860-6 (DE-588)4173280-7 |
| title | Parallel computer architecture a hardware/software approach |
| title_auth | Parallel computer architecture a hardware/software approach |
| title_exact_search | Parallel computer architecture a hardware/software approach |
| title_exact_search_txtP | Parallel computer architecture a hardware/software approach |
| title_full | Parallel computer architecture a hardware/software approach David E. Culler, Jaswinder Pal Singh with Anoop Gupta |
| title_fullStr | Parallel computer architecture a hardware/software approach David E. Culler, Jaswinder Pal Singh with Anoop Gupta |
| title_full_unstemmed | Parallel computer architecture a hardware/software approach David E. Culler, Jaswinder Pal Singh with Anoop Gupta |
| title_short | Parallel computer architecture |
| title_sort | parallel computer architecture a hardware software approach |
| title_sub | a hardware/software approach |
| topic | Computerarchitektur (DE-588)4048717-9 gnd Parallelverarbeitung (DE-588)4075860-6 gnd Parallelrechner (DE-588)4173280-7 gnd |
| topic_facet | Computerarchitektur Parallelverarbeitung Parallelrechner |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=015596630&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT cullerdavide parallelcomputerarchitectureahardwaresoftwareapproach AT singhjaswinderpal parallelcomputerarchitectureahardwaresoftwareapproach AT guptaanoop parallelcomputerarchitectureahardwaresoftwareapproach |