Charge-based MOS transistor modeling: the EKV model for low-power and RF IC design
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| Main Authors: | , |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Hoboken, NJ [u.a.]
Wiley
2006
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| Subjects: | |
| Online Access: | Inhaltsverzeichnis Beschreibung für Leser Inhaltsverzeichnis Inhaltsverzeichnis |
| Physical Description: | XXIII, 303 S. graph. Darst. |
| ISBN: | 047085541X 9780470855416 |
Staff View
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| 264 | 1 | |a Hoboken, NJ [u.a.] |b Wiley |c 2006 | |
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Record in the Search Index
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| adam_text | Contents
Foreword xiii
Preface xv
List of Symbols xvii
1 Introduction 1
1.1 The Importance of Device Modeling for IC Design 1
1.2 A Short History of the EKV MOS Transistor Model 2
1.3 The Book Structure 5
Part I The Basic Long Channel Intrinsic Charge Based Model 7
2 Definitions 9
2.1 The N channel Transistor Structure 9
2.2 Definition of Charges, Current, Potential, and Electric Fields 10
2.3 Transistor Symbol and P channel Transistor 11
3 The Basic Charge Model 13
3.1 Poisson s Equation and Gradual Channel Approximation 13
3.2 Surface Potential as a Function of Gate Voltage 17
3.3 Gate Capacitance 18
3.4 Charge Sheet Approximation 20
3.5 Density of Mobile Inverted Charge 21
3.5.1 Mobile Charge as a Function of Gate Voltage and Surface Potential 21
3.5.2 Mobile Charge as a Function of Channel Voltage and
Surface Potential 23
3.6 Charge Potential Linearization 23
3.6.1 Linearization of Gi(*s) 23
3.6.2 Linearized Bulk Depletion Charge Qb 26
3.6.3 Strong Inversion Approximation 27
3.6.4 Evaluation of the Slope Factor 29
3.6.5 Compact Model Parameters 32
viii CONTENTS
4 Static Drain Current 33
4.1 Drain Current Expression 33
4.2 Forward and Reverse Current Components 35
4.3 Modes of Operation 36
4.4 Model of Drain Current Based on Charge Linearization 37
4.4.1 Expression Valid for All Levels of Inversion 37
4.4.2 Compact Model Parameters 39
4.4.3 Inversion Coefficient 40
4.4.4 Approximation of the Drain Current in Strong Inversion 41
4.4.5 Approximation of the Drain Current in Weak Inversion 43
4.4.6 Alternative Continuous Models 45
4.5 Fundamental Property: Validity and Application 46
4.5.1 Generalization of Drain Current Expression 46
4.5.2 Domain of Validity 46
4.5.3 Causes of Degradation 48
4.5.4 Concept of Pseudo Resistor 49
4.6 Channel Length Modulation 50
4.6.1 Effective Channel Length 50
4.6.2 Weak Inversion 52
4.6.3 Strong Inversion 52
4.6.4 Geometrical Effects 53
5 The Small Signal Model 55
5.1 The Static Small Signal Model 55
5.1.1 Transconductances 55
5.1.2 Residual Output Conductance in Saturation 60
5.1.3 Equivalent Circuit 61
5.1.4 The Normalized Transconductance to Drain Current Ratio 62
5.2 A General NQS Small Signal Model 65
5.3 The QS Dynamic Small Signal Model 72
5.3.1 Intrinsic Capacitances 72
5.3.2 Transcapacitances 74
5.3.3 Complete QS Circuit 75
5.3.4 Domains of Validity of the Different Models 77
6 The Noise Model 81
6.1 Noise Calculation Methods 81
6.1.1 General Expression 81
6.1.2 Long Channel Simplification 86
6.2 Low Frequency Channel Thermal Noise 87
6.2.1 Drain Current Thermal Noise PSD 87
6.2.2 Thermal Noise Excess Factor Definitions 89
6.2.3 Circuit Examples 91
6.3 Flicker Noise 96
6.3.1 Carrier Number Fluctuations (Me Worther Model) 96
6.3.2 Mobility Fluctuations (Hooge Model) 101
6.3.3 Additional Contributions Due to the Source and
Drain Access Resistances 103
CONTENTS ix
6.3.4 Total 1// Noise at the Drain 104
6.3.5 Scaling Properties 105
6.4 Appendices 106
Appendix: The Nyquist and Bode Theorems 106
Appendix: General Noise Expression 108
7 Temperature Effects and Matching 111
7.1 Introduction 111
7.2 Temperature Effects 112
7.2.1 Variation of Basic Physical Parameters 112
7.2.2 Variation of the Voltage Charge Characteristics 116
7.2.3 Variation of the Voltage Current Characteristics 118
7.2.4 Variation of the Current Charge Characteristics 120
7.3 Matching 120
7.3.1 Introduction 120
7.3.2 Deterministic Mismatch 121
7.3.3 Random Mismatch 125
Part II The Extended Charge Based Model 131
8 Nonideal Effects Related to the Vertical Dimension 133
8.1 Introduction 133
8.2 Mobility Reduction Due to the Vertical Field 133
8.3 Nonuniform Vertical Doping 138
8.3.1 Introduction and General Case 138
8.3.2 Constant Gradient Doping Profile 139
8.3.3 Step Profile 141
8.3.4 Effect on the Basic Model 147
8.4 Polysilicon Depletion 148
8.4.1 Definition of the Effect 148
8.4.2 Effect on the Mobile Inverted Charge 149
8.4.3 Slope Factors and Pinch Off Surface Potential 150
8.4.4 Voltage Slope Factor ns 152
8.4.5 Charge Slope Factor nq 153
8.4.6 Effect on Q (V), Currents, and Transconductances 154
8.4.7 Strong Inversion Approximation 155
8.5 Band Gap Widening 156
8.5.1 Introduction 156
8.5.2 Extension of the General Charge Voltage Expression 158
8.5.3 Extension of the General Current Voltage Expression 160
8.6 Gate Leakage Current 161
9 Short Channel Effects 167
9.1 Velocity Saturation 167
9.1.1 Velocity Field Models 169
9.1.2 Effect of VS on the Drain Current 171
9.1.3 Effect of VS on the Transconductances 181
x CONTENTS
9.2 Channel Length Modulation 186
9.3 Drain Induced Barrier Lowering 189
9.3.1 Introduction 189
9.3.2 Evaluation of the Surface Potential 189
9.3.3 Effect on the Drain Current 194
9.3.4 Effect on Small Signal Parameters in Weak Inversion 196
9.4 Short Channel Thermal Noise Model 197
9.4.1 Thermal Noise Drain Conductance 198
9.4.2 Effect of VS and Carrier Heating on Thermal Noise 205
9.4.3 Effects of Vertical Field Mobility Reduction and Channel
Length Modulation 209
9.4.4 Summary 211
10 The Extrinsic Model 213
10.1 Extrinsic Part of the Device 213
10.2 Access Resistances 215
10.2.1 Source and Drain Resistances 215
10.2.2 The Gate Resistance 217
10.3 Overlap Regions 220
10.3.1 Overlap Capacitances 220
10.3.2 Overlap Gate Leakage Current 223
10.4 Source and Drain Junctions 223
10.4.1 Source and Drain Diodes Large Signal Model 223
10.4.2 Source and Drain Junction Capacitances 224
10.4.3 Source and Drain Junction Conductances 226
10.5 Extrinsic Noise Sources 226
Part III The High Frequency Model 229
11 Equivalent Circuit at RF 231
11.1 RF MOS Transistor Structure and Layout 231
11.2 What Changes at RF? 231
11.3 Transistor Figures of Merit 232
11.3.1 Transit Frequency 232
11.3.2 Maximum Frequency of Oscillation/max 236
11.3.3 Minimum Noise Figure 238
11.3.4 Moderate and Weak Inversion for RF Circuits 239
11.4 Equivalent Circuit at RF 240
11.4.1 Equivalent Circuit at RF 240
11.4.2 Intradevice Substrate Coupling and Substrate Resistive
Networks 242
11.4.3 Practical Implementation Issues 247
12 The Small Signal Model at RF 249
12.1 The Equivalent Small Signal Circuit at RF 249
12.2 Y Parameters Analysis 251
12.3 The Large Signal Model at RF 257
CONTENTS xi
13 The Noise Model at RF 261
13.1 The HF Noise Parameters 261
13.1.1 The Noisy Two Port 261
13.1.2 The Correlation Admittance 263
13.1.3 The Noise Factor 265
13.1.4 Minimum Noise Factor 266
13.2 The High Frequency Thermal Noise Model 267
13.2.1 Generalized High Frequency Noise Model 268
13.2.2 The Two Transistor Approach at High Frequency 269
13.2.3 Generic PSDs Derivation 272
13.2.4 First Order Approximation 273
13.2.5 Higher Order Effects 279
13.3 HF Noise Parameters of a Common Source Amplifier 282
13.3.1 Simple Equivalent Circuit Including Induced Gate Noise and
Drain Noise 282
13.3.2 Equivalent Circuit Including Induced Gate Noise, Drain Noise,
Gate and Substrate Resistances Noise 288
References 291
Index 299
|
| adam_txt |
Contents
Foreword xiii
Preface xv
List of Symbols xvii
1 Introduction 1
1.1 The Importance of Device Modeling for IC Design 1
1.2 A Short History of the EKV MOS Transistor Model 2
1.3 The Book Structure 5
Part I The Basic Long Channel Intrinsic Charge Based Model 7
2 Definitions 9
2.1 The N channel Transistor Structure 9
2.2 Definition of Charges, Current, Potential, and Electric Fields 10
2.3 Transistor Symbol and P channel Transistor 11
3 The Basic Charge Model 13
3.1 Poisson's Equation and Gradual Channel Approximation 13
3.2 Surface Potential as a Function of Gate Voltage 17
3.3 Gate Capacitance 18
3.4 Charge Sheet Approximation 20
3.5 Density of Mobile Inverted Charge 21
3.5.1 Mobile Charge as a Function of Gate Voltage and Surface Potential 21
3.5.2 Mobile Charge as a Function of Channel Voltage and
Surface Potential 23
3.6 Charge Potential Linearization 23
3.6.1 Linearization of Gi(*s) 23
3.6.2 Linearized Bulk Depletion Charge Qb 26
3.6.3 Strong Inversion Approximation 27
3.6.4 Evaluation of the Slope Factor 29
3.6.5 Compact Model Parameters 32
viii CONTENTS
4 Static Drain Current 33
4.1 Drain Current Expression 33
4.2 Forward and Reverse Current Components 35
4.3 Modes of Operation 36
4.4 Model of Drain Current Based on Charge Linearization 37
4.4.1 Expression Valid for All Levels of Inversion 37
4.4.2 Compact Model Parameters 39
4.4.3 Inversion Coefficient 40
4.4.4 Approximation of the Drain Current in Strong Inversion 41
4.4.5 Approximation of the Drain Current in Weak Inversion 43
4.4.6 Alternative Continuous Models 45
4.5 Fundamental Property: Validity and Application 46
4.5.1 Generalization of Drain Current Expression 46
4.5.2 Domain of Validity 46
4.5.3 Causes of Degradation 48
4.5.4 Concept of Pseudo Resistor 49
4.6 Channel Length Modulation 50
4.6.1 Effective Channel Length 50
4.6.2 Weak Inversion 52
4.6.3 Strong Inversion 52
4.6.4 Geometrical Effects 53
5 The Small Signal Model 55
5.1 The Static Small Signal Model 55
5.1.1 Transconductances 55
5.1.2 Residual Output Conductance in Saturation 60
5.1.3 Equivalent Circuit 61
5.1.4 The Normalized Transconductance to Drain Current Ratio 62
5.2 A General NQS Small Signal Model 65
5.3 The QS Dynamic Small Signal Model 72
5.3.1 Intrinsic Capacitances 72
5.3.2 Transcapacitances 74
5.3.3 Complete QS Circuit 75
5.3.4 Domains of Validity of the Different Models 77
6 The Noise Model 81
6.1 Noise Calculation Methods 81
6.1.1 General Expression 81
6.1.2 Long Channel Simplification 86
6.2 Low Frequency Channel Thermal Noise 87
6.2.1 Drain Current Thermal Noise PSD 87
6.2.2 Thermal Noise Excess Factor Definitions 89
6.2.3 Circuit Examples 91
6.3 Flicker Noise 96
6.3.1 Carrier Number Fluctuations (Me Worther Model) 96
6.3.2 Mobility Fluctuations (Hooge Model) 101
6.3.3 Additional Contributions Due to the Source and
Drain Access Resistances 103
CONTENTS ix
6.3.4 Total 1// Noise at the Drain 104
6.3.5 Scaling Properties 105
6.4 Appendices 106
Appendix: The Nyquist and Bode Theorems 106
Appendix: General Noise Expression 108
7 Temperature Effects and Matching 111
7.1 Introduction 111
7.2 Temperature Effects 112
7.2.1 Variation of Basic Physical Parameters 112
7.2.2 Variation of the Voltage Charge Characteristics 116
7.2.3 Variation of the Voltage Current Characteristics 118
7.2.4 Variation of the Current Charge Characteristics 120
7.3 Matching 120
7.3.1 Introduction 120
7.3.2 Deterministic Mismatch 121
7.3.3 Random Mismatch 125
Part II The Extended Charge Based Model 131
8 Nonideal Effects Related to the Vertical Dimension 133
8.1 Introduction 133
8.2 Mobility Reduction Due to the Vertical Field 133
8.3 Nonuniform Vertical Doping 138
8.3.1 Introduction and General Case 138
8.3.2 Constant Gradient Doping Profile 139
8.3.3 Step Profile 141
8.3.4 Effect on the Basic Model 147
8.4 Polysilicon Depletion 148
8.4.1 Definition of the Effect 148
8.4.2 Effect on the Mobile Inverted Charge 149
8.4.3 Slope Factors and Pinch Off Surface Potential 150
8.4.4 Voltage Slope Factor ns 152
8.4.5 Charge Slope Factor nq 153
8.4.6 Effect on Q\(V), Currents, and Transconductances 154
8.4.7 Strong Inversion Approximation 155
8.5 Band Gap Widening 156
8.5.1 Introduction 156
8.5.2 Extension of the General Charge Voltage Expression 158
8.5.3 Extension of the General Current Voltage Expression 160
8.6 Gate Leakage Current 161
9 Short Channel Effects 167
9.1 Velocity Saturation 167
9.1.1 Velocity Field Models 169
9.1.2 Effect of VS on the Drain Current 171
9.1.3 Effect of VS on the Transconductances 181
x CONTENTS
9.2 Channel Length Modulation 186
9.3 Drain Induced Barrier Lowering 189
9.3.1 Introduction 189
9.3.2 Evaluation of the Surface Potential 189
9.3.3 Effect on the Drain Current 194
9.3.4 Effect on Small Signal Parameters in Weak Inversion 196
9.4 Short Channel Thermal Noise Model 197
9.4.1 Thermal Noise Drain Conductance 198
9.4.2 Effect of VS and Carrier Heating on Thermal Noise 205
9.4.3 Effects of Vertical Field Mobility Reduction and Channel
Length Modulation 209
9.4.4 Summary 211
10 The Extrinsic Model 213
10.1 Extrinsic Part of the Device 213
10.2 Access Resistances 215
10.2.1 Source and Drain Resistances 215
10.2.2 The Gate Resistance 217
10.3 Overlap Regions 220
10.3.1 Overlap Capacitances 220
10.3.2 Overlap Gate Leakage Current 223
10.4 Source and Drain Junctions 223
10.4.1 Source and Drain Diodes Large Signal Model 223
10.4.2 Source and Drain Junction Capacitances 224
10.4.3 Source and Drain Junction Conductances 226
10.5 Extrinsic Noise Sources 226
Part III The High Frequency Model 229
11 Equivalent Circuit at RF 231
11.1 RF MOS Transistor Structure and Layout 231
11.2 What Changes at RF? 231
11.3 Transistor Figures of Merit 232
11.3.1 Transit Frequency 232
11.3.2 Maximum Frequency of Oscillation/max 236
11.3.3 Minimum Noise Figure 238
11.3.4 Moderate and Weak Inversion for RF Circuits 239
11.4 Equivalent Circuit at RF 240
11.4.1 Equivalent Circuit at RF 240
11.4.2 Intradevice Substrate Coupling and Substrate Resistive
Networks 242
11.4.3 Practical Implementation Issues 247
12 The Small Signal Model at RF 249
12.1 The Equivalent Small Signal Circuit at RF 249
12.2 Y Parameters Analysis 251
12.3 The Large Signal Model at RF 257
CONTENTS xi
13 The Noise Model at RF 261
13.1 The HF Noise Parameters 261
13.1.1 The Noisy Two Port 261
13.1.2 The Correlation Admittance 263
13.1.3 The Noise Factor 265
13.1.4 Minimum Noise Factor 266
13.2 The High Frequency Thermal Noise Model 267
13.2.1 Generalized High Frequency Noise Model 268
13.2.2 The Two Transistor Approach at High Frequency 269
13.2.3 Generic PSDs Derivation 272
13.2.4 First Order Approximation 273
13.2.5 Higher Order Effects 279
13.3 HF Noise Parameters of a Common Source Amplifier 282
13.3.1 Simple Equivalent Circuit Including Induced Gate Noise and
Drain Noise 282
13.3.2 Equivalent Circuit Including Induced Gate Noise, Drain Noise,
Gate and Substrate Resistances Noise 288
References 291
Index 299 |
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| id | DE-604.BV022380853 |
| illustrated | Illustrated |
| index_date | 2024-07-02T17:11:14Z |
| indexdate | 2024-07-09T20:56:23Z |
| institution | BVB |
| isbn | 047085541X 9780470855416 |
| language | English |
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| physical | XXIII, 303 S. graph. Darst. |
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| publisher | Wiley |
| record_format | marc |
| spelling | Enz, Christian C. Verfasser aut Charge-based MOS transistor modeling the EKV model for low-power and RF IC design Christian C. Enz ; Eric A. Vittoz Hoboken, NJ [u.a.] Wiley 2006 XXIII, 303 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Mathematisches Modell Metal oxide semiconductor field-effect transistors Mathematical models Metal oxide semiconductors Mathematical models MOS (DE-588)4130209-6 gnd rswk-swf MOS (DE-588)4130209-6 s DE-604 Vittoz, Eric Verfasser aut http://www.gbv.de/dms/ilmenau/toc/50634052X.PDF Inhaltsverzeichnis http://www.loc.gov/catdir/enhancements/fy0653/2006041744-d.html Beschreibung für Leser http://digitool.hbz-nrw.de:1801/webclient/DeliveryManager?pid=1700712&custom_att_2=simple_viewer Charge-based MOS transistor modeling Inhaltsverzeichnis HBZ Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=015589843&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Enz, Christian C. Vittoz, Eric Charge-based MOS transistor modeling the EKV model for low-power and RF IC design Mathematisches Modell Metal oxide semiconductor field-effect transistors Mathematical models Metal oxide semiconductors Mathematical models MOS (DE-588)4130209-6 gnd |
| subject_GND | (DE-588)4130209-6 |
| title | Charge-based MOS transistor modeling the EKV model for low-power and RF IC design |
| title_auth | Charge-based MOS transistor modeling the EKV model for low-power and RF IC design |
| title_exact_search | Charge-based MOS transistor modeling the EKV model for low-power and RF IC design |
| title_exact_search_txtP | Charge-based MOS transistor modeling the EKV model for low-power and RF IC design |
| title_full | Charge-based MOS transistor modeling the EKV model for low-power and RF IC design Christian C. Enz ; Eric A. Vittoz |
| title_fullStr | Charge-based MOS transistor modeling the EKV model for low-power and RF IC design Christian C. Enz ; Eric A. Vittoz |
| title_full_unstemmed | Charge-based MOS transistor modeling the EKV model for low-power and RF IC design Christian C. Enz ; Eric A. Vittoz |
| title_short | Charge-based MOS transistor modeling |
| title_sort | charge based mos transistor modeling the ekv model for low power and rf ic design |
| title_sub | the EKV model for low-power and RF IC design |
| topic | Mathematisches Modell Metal oxide semiconductor field-effect transistors Mathematical models Metal oxide semiconductors Mathematical models MOS (DE-588)4130209-6 gnd |
| topic_facet | Mathematisches Modell Metal oxide semiconductor field-effect transistors Mathematical models Metal oxide semiconductors Mathematical models MOS |
| url | http://www.gbv.de/dms/ilmenau/toc/50634052X.PDF http://www.loc.gov/catdir/enhancements/fy0653/2006041744-d.html http://digitool.hbz-nrw.de:1801/webclient/DeliveryManager?pid=1700712&custom_att_2=simple_viewer http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=015589843&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT enzchristianc chargebasedmostransistormodelingtheekvmodelforlowpowerandrficdesign AT vittozeric chargebasedmostransistormodelingtheekvmodelforlowpowerandrficdesign |
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