Verfügbarkeit: Formal verification of hardware design

Formal verification of hardware design:

Gespeichert in:

Bibliographische Detailangaben
Format:	Buch
Sprache:	English
Veröffentlicht:	Los Alamitos, Calif. [u.a.] IEEE Computer Soc. Pr. 1990
Schriftenreihe:	IEEE Computer Society Press tutorial
Schlagworte:	Hardwareentwurf Schaltungsentwurf Software Integrierte Schaltung Hardwareverifikation VLSI CAD Aufsatzsammlung
Beschreibung:	IX, 326 S. graph. Darst.
ISBN:	0818690178 0818660171

Internformat

MARC


LEADER	00000nam a2200000zc 4500
001	BV021913535
003	DE-604
005	20040301000000.0
007	t
008	930910s1990 d\|\|\| \|\|\|\| 00\|\|\| eng d
020			\|a 0818690178 \|9 0-8186-9017-8
020			\|a 0818660171 \|9 0-8186-6017-1
035			\|a (OCoLC)301026231
035			\|a (DE-599)BVBBV021913535
040			\|a DE-604 \|b ger
041	0		\|a eng
049			\|a DE-706
084			\|a ST 190 \|0 (DE-625)143607: \|2 rvk
084			\|a ST 195 \|0 (DE-625)143608: \|2 rvk
084			\|a ZN 4030 \|0 (DE-625)157339: \|2 rvk
245	1	0	\|a Formal verification of hardware design \|c ed. by Michael Yoeli
264		1	\|a Los Alamitos, Calif. [u.a.] \|b IEEE Computer Soc. Pr. \|c 1990
300			\|a IX, 326 S. \|b graph. Darst.
336			\|b txt \|2 rdacontent
337			\|b n \|2 rdamedia
338			\|b nc \|2 rdacarrier
490	0		\|a IEEE Computer Society Press tutorial
650	0	7	\|a Hardwareentwurf \|0 (DE-588)4159103-3 \|2 gnd \|9 rswk-swf
650	0	7	\|a Schaltungsentwurf \|0 (DE-588)4179389-4 \|2 gnd \|9 rswk-swf
650	0	7	\|a Software \|0 (DE-588)4055382-6 \|2 gnd \|9 rswk-swf
650	0	7	\|a Integrierte Schaltung \|0 (DE-588)4027242-4 \|2 gnd \|9 rswk-swf
650	0	7	\|a Hardwareverifikation \|0 (DE-588)4214982-4 \|2 gnd \|9 rswk-swf
650	0	7	\|a VLSI \|0 (DE-588)4117388-0 \|2 gnd \|9 rswk-swf
650	0	7	\|a CAD \|0 (DE-588)4069794-0 \|2 gnd \|9 rswk-swf
655		7	\|8 1\p \|0 (DE-588)4143413-4 \|a Aufsatzsammlung \|2 gnd-content
689	0	0	\|a Integrierte Schaltung \|0 (DE-588)4027242-4 \|D s
689	0		\|5 DE-604
689	1	0	\|a Software \|0 (DE-588)4055382-6 \|D s
689	1		\|5 DE-604
689	2	0	\|a CAD \|0 (DE-588)4069794-0 \|D s
689	2		\|5 DE-604
689	3	0	\|a VLSI \|0 (DE-588)4117388-0 \|D s
689	3		\|5 DE-604
689	4	0	\|a Schaltungsentwurf \|0 (DE-588)4179389-4 \|D s
689	4		\|5 DE-604
689	5	0	\|a Hardwareentwurf \|0 (DE-588)4159103-3 \|D s
689	5		\|8 2\p \|5 DE-604
689	6	0	\|a Hardwareverifikation \|0 (DE-588)4214982-4 \|D s
689	6		\|8 3\p \|5 DE-604
700	1		\|a Yoeli, Michael \|e Sonstige \|4 oth
999			\|a oai:aleph.bib-bvb.de:BVB01-015128706
883	1		\|8 1\p \|a cgwrk \|d 20201028 \|q DE-101 \|u https://d-nb.info/provenance/plan#cgwrk
883	1		\|8 2\p \|a cgwrk \|d 20201028 \|q DE-101 \|u https://d-nb.info/provenance/plan#cgwrk
883	1		\|8 3\p \|a cgwrk \|d 20201028 \|q DE-101 \|u https://d-nb.info/provenance/plan#cgwrk

Datensatz im Suchindex

_version_	1804135863968333824
adam_txt
any_adam_object
any_adam_object_boolean
building	Verbundindex
bvnumber	BV021913535
classification_rvk	ST 190 ST 195 ZN 4030
ctrlnum	(OCoLC)301026231 (DE-599)BVBBV021913535
discipline	Informatik Elektrotechnik / Elektronik / Nachrichtentechnik
discipline_str_mv	Informatik Elektrotechnik / Elektronik / Nachrichtentechnik
format	Book
fullrecord	<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02268nam a2200613zc 4500</leader><controlfield tag="001">BV021913535</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20040301000000.0</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">930910s1990 d\|\|\| \|\|\|\| 00\|\|\| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0818690178</subfield><subfield code="9">0-8186-9017-8</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0818660171</subfield><subfield code="9">0-8186-6017-1</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)301026231</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV021913535</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-706</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 190</subfield><subfield code="0">(DE-625)143607:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 195</subfield><subfield code="0">(DE-625)143608:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4030</subfield><subfield code="0">(DE-625)157339:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Formal verification of hardware design</subfield><subfield code="c">ed. by Michael Yoeli</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Los Alamitos, Calif. [u.a.]</subfield><subfield code="b">IEEE Computer Soc. Pr.</subfield><subfield code="c">1990</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">IX, 326 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="0" ind2=" "><subfield code="a">IEEE Computer Society Press tutorial</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Hardwareentwurf</subfield><subfield code="0">(DE-588)4159103-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Schaltungsentwurf</subfield><subfield code="0">(DE-588)4179389-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Software</subfield><subfield code="0">(DE-588)4055382-6</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Hardwareverifikation</subfield><subfield code="0">(DE-588)4214982-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">CAD</subfield><subfield code="0">(DE-588)4069794-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="8">1\p</subfield><subfield code="0">(DE-588)4143413-4</subfield><subfield code="a">Aufsatzsammlung</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">Software</subfield><subfield code="0">(DE-588)4055382-6</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="2" ind2="0"><subfield code="a">CAD</subfield><subfield code="0">(DE-588)4069794-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="3" ind2="0"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="3" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="4" ind2="0"><subfield code="a">Schaltungsentwurf</subfield><subfield code="0">(DE-588)4179389-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="4" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="5" ind2="0"><subfield code="a">Hardwareentwurf</subfield><subfield code="0">(DE-588)4159103-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="5" ind2=" "><subfield code="8">2\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="6" ind2="0"><subfield code="a">Hardwareverifikation</subfield><subfield code="0">(DE-588)4214982-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="6" ind2=" "><subfield code="8">3\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Yoeli, Michael</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-015128706</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">2\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">3\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield></record></collection>
genre	1\p (DE-588)4143413-4 Aufsatzsammlung gnd-content
genre_facet	Aufsatzsammlung
id	DE-604.BV021913535
illustrated	Illustrated
index_date	2024-07-02T16:05:23Z
indexdate	2024-07-09T20:47:16Z
institution	BVB
isbn	0818690178 0818660171
language	English
oai_aleph_id	oai:aleph.bib-bvb.de:BVB01-015128706
oclc_num	301026231
open_access_boolean
owner	DE-706
owner_facet	DE-706
physical	IX, 326 S. graph. Darst.
publishDate	1990
publishDateSearch	1990
publishDateSort	1990
publisher	IEEE Computer Soc. Pr.
record_format	marc
series2	IEEE Computer Society Press tutorial
spelling	Formal verification of hardware design ed. by Michael Yoeli Los Alamitos, Calif. [u.a.] IEEE Computer Soc. Pr. 1990 IX, 326 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier IEEE Computer Society Press tutorial Hardwareentwurf (DE-588)4159103-3 gnd rswk-swf Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf Software (DE-588)4055382-6 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Hardwareverifikation (DE-588)4214982-4 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf CAD (DE-588)4069794-0 gnd rswk-swf 1\p (DE-588)4143413-4 Aufsatzsammlung gnd-content Integrierte Schaltung (DE-588)4027242-4 s DE-604 Software (DE-588)4055382-6 s CAD (DE-588)4069794-0 s VLSI (DE-588)4117388-0 s Schaltungsentwurf (DE-588)4179389-4 s Hardwareentwurf (DE-588)4159103-3 s 2\p DE-604 Hardwareverifikation (DE-588)4214982-4 s 3\p DE-604 Yoeli, Michael Sonstige oth 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk
spellingShingle	Formal verification of hardware design Hardwareentwurf (DE-588)4159103-3 gnd Schaltungsentwurf (DE-588)4179389-4 gnd Software (DE-588)4055382-6 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Hardwareverifikation (DE-588)4214982-4 gnd VLSI (DE-588)4117388-0 gnd CAD (DE-588)4069794-0 gnd
subject_GND	(DE-588)4159103-3 (DE-588)4179389-4 (DE-588)4055382-6 (DE-588)4027242-4 (DE-588)4214982-4 (DE-588)4117388-0 (DE-588)4069794-0 (DE-588)4143413-4
title	Formal verification of hardware design
title_auth	Formal verification of hardware design
title_exact_search	Formal verification of hardware design
title_exact_search_txtP	Formal verification of hardware design
title_full	Formal verification of hardware design ed. by Michael Yoeli
title_fullStr	Formal verification of hardware design ed. by Michael Yoeli
title_full_unstemmed	Formal verification of hardware design ed. by Michael Yoeli
title_short	Formal verification of hardware design
title_sort	formal verification of hardware design
topic	Hardwareentwurf (DE-588)4159103-3 gnd Schaltungsentwurf (DE-588)4179389-4 gnd Software (DE-588)4055382-6 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Hardwareverifikation (DE-588)4214982-4 gnd VLSI (DE-588)4117388-0 gnd CAD (DE-588)4069794-0 gnd
topic_facet	Hardwareentwurf Schaltungsentwurf Software Integrierte Schaltung Hardwareverifikation VLSI CAD Aufsatzsammlung
work_keys_str_mv	AT yoelimichael formalverificationofhardwaredesign

Verfügbarkeit

Es ist kein Print-Exemplar vorhanden.

Fernleihe Bestellen Achtung: Nicht im THWS-Bestand!

MARC

Datensatz im Suchindex

Es ist kein Print-Exemplar vorhanden.

Ähnliche Einträge