VLSI design techniques for analog and digital circuits:
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
New York [u.a.]
McGraw-Hill
1990
|
| Ausgabe: | 2. print. |
| Schriftenreihe: | McGraw-Hill series in electrical engineering
|
| Schlagworte: | |
| Beschreibung: | XV, 969 S. Ill., graph. Darst. |
| ISBN: | 0070232539 |
Internformat
MARC
| LEADER | 00000nam a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV021900316 | ||
| 003 | DE-604 | ||
| 005 | 20040301000000.0 | ||
| 007 | t | ||
| 008 | 911018s1990 ad|| |||| 00||| eng d | ||
| 020 | |a 0070232539 |9 0-07-023253-9 | ||
| 035 | |a (OCoLC)18960645 | ||
| 035 | |a (DE-599)BVBBV021900316 | ||
| 040 | |a DE-604 |b ger | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-706 | ||
| 050 | 0 | |a TK7874 | |
| 082 | 0 | |a 621.381/73 |2 19 | |
| 084 | |a ZN 4950 |0 (DE-625)157424: |2 rvk | ||
| 100 | 1 | |a Geiger, Randall L. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a VLSI design techniques for analog and digital circuits |c Randall L. Geiger ; Phillip E. Allen ; Noel R. Strader |
| 250 | |a 2. print. | ||
| 264 | 1 | |a New York [u.a.] |b McGraw-Hill |c 1990 | |
| 300 | |a XV, 969 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 0 | |a McGraw-Hill series in electrical engineering | |
| 650 | 4 | |a Entegre devreler - Büyük ölçekli entegre devre - Tasarım ve yapı | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |x Design and construction | |
| 650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Entwurf |0 (DE-588)4121208-3 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 0 | 1 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |D s |
| 689 | 0 | |8 1\p |5 DE-604 | |
| 689 | 1 | 0 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 1 | 1 | |a Entwurf |0 (DE-588)4121208-3 |D s |
| 689 | 1 | |8 2\p |5 DE-604 | |
| 700 | 1 | |a Berlemann, Friedrich R. |e Verfasser |4 aut | |
| 700 | 1 | |a Strader, Noel R. |e Verfasser |4 aut | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-015115498 | ||
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 2\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
Datensatz im Suchindex
| _version_ | 1804135846324994048 |
|---|---|
| adam_txt | |
| any_adam_object | |
| any_adam_object_boolean | |
| author | Geiger, Randall L. Berlemann, Friedrich R. Strader, Noel R. |
| author_facet | Geiger, Randall L. Berlemann, Friedrich R. Strader, Noel R. |
| author_role | aut aut aut |
| author_sort | Geiger, Randall L. |
| author_variant | r l g rl rlg f r b fr frb n r s nr nrs |
| building | Verbundindex |
| bvnumber | BV021900316 |
| callnumber-first | T - Technology |
| callnumber-label | TK7874 |
| callnumber-raw | TK7874 |
| callnumber-search | TK7874 |
| callnumber-sort | TK 47874 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ZN 4950 |
| ctrlnum | (OCoLC)18960645 (DE-599)BVBBV021900316 |
| dewey-full | 621.381/73 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.381/73 |
| dewey-search | 621.381/73 |
| dewey-sort | 3621.381 273 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| discipline_str_mv | Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | 2. print. |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01845nam a2200493zc 4500</leader><controlfield tag="001">BV021900316</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20040301000000.0</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">911018s1990 ad|| |||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0070232539</subfield><subfield code="9">0-07-023253-9</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)18960645</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV021900316</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-706</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK7874</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.381/73</subfield><subfield code="2">19</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4950</subfield><subfield code="0">(DE-625)157424:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Geiger, Randall L.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">VLSI design techniques for analog and digital circuits</subfield><subfield code="c">Randall L. Geiger ; Phillip E. Allen ; Noel R. Strader</subfield></datafield><datafield tag="250" ind1=" " ind2=" "><subfield code="a">2. print.</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">New York [u.a.]</subfield><subfield code="b">McGraw-Hill</subfield><subfield code="c">1990</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XV, 969 S.</subfield><subfield code="b">Ill., graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="0" ind2=" "><subfield code="a">McGraw-Hill series in electrical engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Entegre devreler - Büyük ölçekli entegre devre - Tasarım ve yapı</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits</subfield><subfield code="x">Very large scale integration</subfield><subfield code="x">Design and construction</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Entwurf</subfield><subfield code="0">(DE-588)4121208-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2="1"><subfield code="a">Entwurf</subfield><subfield code="0">(DE-588)4121208-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="8">2\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Berlemann, Friedrich R.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Strader, Noel R.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-015115498</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">2\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield></record></collection> |
| id | DE-604.BV021900316 |
| illustrated | Illustrated |
| index_date | 2024-07-02T16:04:38Z |
| indexdate | 2024-07-09T20:46:59Z |
| institution | BVB |
| isbn | 0070232539 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-015115498 |
| oclc_num | 18960645 |
| open_access_boolean | |
| owner | DE-706 |
| owner_facet | DE-706 |
| physical | XV, 969 S. Ill., graph. Darst. |
| publishDate | 1990 |
| publishDateSearch | 1990 |
| publishDateSort | 1990 |
| publisher | McGraw-Hill |
| record_format | marc |
| series2 | McGraw-Hill series in electrical engineering |
| spelling | Geiger, Randall L. Verfasser aut VLSI design techniques for analog and digital circuits Randall L. Geiger ; Phillip E. Allen ; Noel R. Strader 2. print. New York [u.a.] McGraw-Hill 1990 XV, 969 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier McGraw-Hill series in electrical engineering Entegre devreler - Büyük ölçekli entegre devre - Tasarım ve yapı Integrated circuits Very large scale integration Design and construction VLSI (DE-588)4117388-0 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf VLSI (DE-588)4117388-0 s Integrierte Schaltung (DE-588)4027242-4 s 1\p DE-604 Entwurf (DE-588)4121208-3 s 2\p DE-604 Berlemann, Friedrich R. Verfasser aut Strader, Noel R. Verfasser aut 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Geiger, Randall L. Berlemann, Friedrich R. Strader, Noel R. VLSI design techniques for analog and digital circuits Entegre devreler - Büyük ölçekli entegre devre - Tasarım ve yapı Integrated circuits Very large scale integration Design and construction VLSI (DE-588)4117388-0 gnd Entwurf (DE-588)4121208-3 gnd Integrierte Schaltung (DE-588)4027242-4 gnd |
| subject_GND | (DE-588)4117388-0 (DE-588)4121208-3 (DE-588)4027242-4 |
| title | VLSI design techniques for analog and digital circuits |
| title_auth | VLSI design techniques for analog and digital circuits |
| title_exact_search | VLSI design techniques for analog and digital circuits |
| title_exact_search_txtP | VLSI design techniques for analog and digital circuits |
| title_full | VLSI design techniques for analog and digital circuits Randall L. Geiger ; Phillip E. Allen ; Noel R. Strader |
| title_fullStr | VLSI design techniques for analog and digital circuits Randall L. Geiger ; Phillip E. Allen ; Noel R. Strader |
| title_full_unstemmed | VLSI design techniques for analog and digital circuits Randall L. Geiger ; Phillip E. Allen ; Noel R. Strader |
| title_short | VLSI design techniques for analog and digital circuits |
| title_sort | vlsi design techniques for analog and digital circuits |
| topic | Entegre devreler - Büyük ölçekli entegre devre - Tasarım ve yapı Integrated circuits Very large scale integration Design and construction VLSI (DE-588)4117388-0 gnd Entwurf (DE-588)4121208-3 gnd Integrierte Schaltung (DE-588)4027242-4 gnd |
| topic_facet | Entegre devreler - Büyük ölçekli entegre devre - Tasarım ve yapı Integrated circuits Very large scale integration Design and construction VLSI Entwurf Integrierte Schaltung |
| work_keys_str_mv | AT geigerrandalll vlsidesigntechniquesforanaloganddigitalcircuits AT berlemannfriedrichr vlsidesigntechniquesforanaloganddigitalcircuits AT stradernoelr vlsidesigntechniquesforanaloganddigitalcircuits |