Wafer-scale integration of systolic arrays:
VLSI technologies are fast developing wafer-scale integration. Rather than partitioning a silicon wafer into chips as is usually done, the idea behind wafer-scale integration is to assemble an entire system (or network of chips) on a single wafer, thus avoiding the costs and performance loss associa...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Cambridge, Mass.
Mass. Inst. of Technology, Laboratory for Computer Science
1983
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| Schlagworte: | |
| Zusammenfassung: | VLSI technologies are fast developing wafer-scale integration. Rather than partitioning a silicon wafer into chips as is usually done, the idea behind wafer-scale integration is to assemble an entire system (or network of chips) on a single wafer, thus avoiding the costs and performance loss associated with individual packaging of chips. A major problem with assembling a large system of microprocessors on a single wafer, however, is that some of the processors, or cells, on the wafer are likely to be defective. In the paper, we describe practical procedures for integrating wafer-scale systems 'around' such faults. The procedures are designed to minimize the length of the longest wire in the system, thus minimizing the communication time between cells. Although the underlying network problems are NP-complete, we prove that the procedures are reliable by assuming a probabilistic model of cell failure. We also discuss applications of this work to problems in VLSI layout theory, graph theory, fault-tolerant systems and planar geometry. |
| Beschreibung: | 29 S. graph. Darst. |
Internformat
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| 245 | 1 | 0 | |a Wafer-scale integration of systolic arrays |c Frank Thomson Leighton and Charles E. Leiserson |
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| 520 | 3 | |a VLSI technologies are fast developing wafer-scale integration. Rather than partitioning a silicon wafer into chips as is usually done, the idea behind wafer-scale integration is to assemble an entire system (or network of chips) on a single wafer, thus avoiding the costs and performance loss associated with individual packaging of chips. A major problem with assembling a large system of microprocessors on a single wafer, however, is that some of the processors, or cells, on the wafer are likely to be defective. In the paper, we describe practical procedures for integrating wafer-scale systems 'around' such faults. The procedures are designed to minimize the length of the longest wire in the system, thus minimizing the communication time between cells. Although the underlying network problems are NP-complete, we prove that the procedures are reliable by assuming a probabilistic model of cell failure. We also discuss applications of this work to problems in VLSI layout theory, graph theory, fault-tolerant systems and planar geometry. | |
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| id | DE-604.BV021879006 |
| illustrated | Illustrated |
| index_date | 2024-07-02T16:03:41Z |
| indexdate | 2024-07-09T20:46:33Z |
| institution | BVB |
| language | English |
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| physical | 29 S. graph. Darst. |
| publishDate | 1983 |
| publishDateSearch | 1983 |
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| publisher | Mass. Inst. of Technology, Laboratory for Computer Science |
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| spelling | Leighton, Frank T. Verfasser aut Wafer-scale integration of systolic arrays Frank Thomson Leighton and Charles E. Leiserson Cambridge, Mass. Mass. Inst. of Technology, Laboratory for Computer Science 1983 29 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier VLSI technologies are fast developing wafer-scale integration. Rather than partitioning a silicon wafer into chips as is usually done, the idea behind wafer-scale integration is to assemble an entire system (or network of chips) on a single wafer, thus avoiding the costs and performance loss associated with individual packaging of chips. A major problem with assembling a large system of microprocessors on a single wafer, however, is that some of the processors, or cells, on the wafer are likely to be defective. In the paper, we describe practical procedures for integrating wafer-scale systems 'around' such faults. The procedures are designed to minimize the length of the longest wire in the system, thus minimizing the communication time between cells. Although the underlying network problems are NP-complete, we prove that the procedures are reliable by assuming a probabilistic model of cell failure. We also discuss applications of this work to problems in VLSI layout theory, graph theory, fault-tolerant systems and planar geometry. Arrays dtict Cells dtict Chips(Electronics) dtict Circuit interconnections dtict Electric wire dtict Electrical and Electronic Equipment scgdst Failure dtict Faults dtict Geometry dtict Graphs dtict Length dtict Losses dtict Microprocessors dtict Models dtict Networks dtict Nodes dtict Packaging dtict Performance(Engineering) dtict Planar structures dtict Probability dtict Silicon dtict Solid State Physics scgdst Theory dtict Time dtict Tolerance dtict Wafers dtict Wire dtict Work dtict ULSI (DE-588)4226286-0 gnd rswk-swf Stochastisches System (DE-588)4057635-8 gnd rswk-swf Fehlertoleranz (DE-588)4123192-2 gnd rswk-swf Stochastisches System (DE-588)4057635-8 s DE-604 Fehlertoleranz (DE-588)4123192-2 s ULSI (DE-588)4226286-0 s Leiserson, Charles E. Verfasser aut |
| spellingShingle | Leighton, Frank T. Leiserson, Charles E. Wafer-scale integration of systolic arrays Arrays dtict Cells dtict Chips(Electronics) dtict Circuit interconnections dtict Electric wire dtict Electrical and Electronic Equipment scgdst Failure dtict Faults dtict Geometry dtict Graphs dtict Length dtict Losses dtict Microprocessors dtict Models dtict Networks dtict Nodes dtict Packaging dtict Performance(Engineering) dtict Planar structures dtict Probability dtict Silicon dtict Solid State Physics scgdst Theory dtict Time dtict Tolerance dtict Wafers dtict Wire dtict Work dtict ULSI (DE-588)4226286-0 gnd Stochastisches System (DE-588)4057635-8 gnd Fehlertoleranz (DE-588)4123192-2 gnd |
| subject_GND | (DE-588)4226286-0 (DE-588)4057635-8 (DE-588)4123192-2 |
| title | Wafer-scale integration of systolic arrays |
| title_auth | Wafer-scale integration of systolic arrays |
| title_exact_search | Wafer-scale integration of systolic arrays |
| title_exact_search_txtP | Wafer-scale integration of systolic arrays |
| title_full | Wafer-scale integration of systolic arrays Frank Thomson Leighton and Charles E. Leiserson |
| title_fullStr | Wafer-scale integration of systolic arrays Frank Thomson Leighton and Charles E. Leiserson |
| title_full_unstemmed | Wafer-scale integration of systolic arrays Frank Thomson Leighton and Charles E. Leiserson |
| title_short | Wafer-scale integration of systolic arrays |
| title_sort | wafer scale integration of systolic arrays |
| topic | Arrays dtict Cells dtict Chips(Electronics) dtict Circuit interconnections dtict Electric wire dtict Electrical and Electronic Equipment scgdst Failure dtict Faults dtict Geometry dtict Graphs dtict Length dtict Losses dtict Microprocessors dtict Models dtict Networks dtict Nodes dtict Packaging dtict Performance(Engineering) dtict Planar structures dtict Probability dtict Silicon dtict Solid State Physics scgdst Theory dtict Time dtict Tolerance dtict Wafers dtict Wire dtict Work dtict ULSI (DE-588)4226286-0 gnd Stochastisches System (DE-588)4057635-8 gnd Fehlertoleranz (DE-588)4123192-2 gnd |
| topic_facet | Arrays Cells Chips(Electronics) Circuit interconnections Electric wire Electrical and Electronic Equipment Failure Faults Geometry Graphs Length Losses Microprocessors Models Networks Nodes Packaging Performance(Engineering) Planar structures Probability Silicon Solid State Physics Theory Time Tolerance Wafers Wire Work ULSI Stochastisches System Fehlertoleranz |
| work_keys_str_mv | AT leightonfrankt waferscaleintegrationofsystolicarrays AT leisersoncharlese waferscaleintegrationofsystolicarrays |