New lower bound techniques for VLSI:
In this paper, crossing number and wire area arguments are used to find lower bounds on the layout area and maximum edge length of a variety of new and computationally useful networks. In particular, an N-node planar graph which has layout are theta(N log N) and maximum edge length theta(N(1/2)/log(...
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| Main Author: | |
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| Format: | Book |
| Language: | English |
| Published: |
Cambridge, Mass.
Laboratory for Computer Science, Massachusetts Inst. of Technology
1982
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| Subjects: | |
| Summary: | In this paper, crossing number and wire area arguments are used to find lower bounds on the layout area and maximum edge length of a variety of new and computationally useful networks. In particular, an N-node planar graph which has layout are theta(N log N) and maximum edge length theta(N(1/2)/log(1/2)N), an N-node graph with an theta(x 1/2)-separator which has layout area theta(N log(2)N) and maximum edge length theta(N(1/2)logN/loglogN), and an N-node graph with an theta(x(1-1/r)-separator which has maximum edge length theta(N(1-1/r) for any r > or = .3. |
| Physical Description: | 29 S. |
Staff View
MARC
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| 245 | 1 | 0 | |a New lower bound techniques for VLSI |c Frank Thomson Leighton |
| 264 | 1 | |a Cambridge, Mass. |b Laboratory for Computer Science, Massachusetts Inst. of Technology |c 1982 | |
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| 520 | 3 | |a In this paper, crossing number and wire area arguments are used to find lower bounds on the layout area and maximum edge length of a variety of new and computationally useful networks. In particular, an N-node planar graph which has layout are theta(N log N) and maximum edge length theta(N(1/2)/log(1/2)N), an N-node graph with an theta(x 1/2)-separator which has layout area theta(N log(2)N) and maximum edge length theta(N(1/2)logN/loglogN), and an N-node graph with an theta(x(1-1/r)-separator which has maximum edge length theta(N(1-1/r) for any r > or = .3. | |
| 650 | 4 | |a Lower bounds | |
| 650 | 4 | |a Thompson grid model | |
| 650 | 4 | |a VLSI(Very Large Scale Integration) | |
| 650 | 7 | |a Chips(electronics) |2 dtict | |
| 650 | 7 | |a Computers |2 dtict | |
| 650 | 7 | |a Edges |2 dtict | |
| 650 | 7 | |a Electrical and Electronic Equipment |2 scgdst | |
| 650 | 7 | |a Graphs |2 dtict | |
| 650 | 7 | |a Grids |2 dtict | |
| 650 | 7 | |a Integrated circuits |2 dtict | |
| 650 | 7 | |a Length |2 dtict | |
| 650 | 7 | |a Mathematical models |2 dtict | |
| 650 | 7 | |a Mesh |2 dtict | |
| 650 | 7 | |a Networks |2 dtict | |
| 650 | 7 | |a Nodes |2 dtict | |
| 650 | 7 | |a Space(room) |2 dtict | |
| 650 | 7 | |a Trees |2 dtict | |
| 650 | 7 | |a Wire |2 dtict | |
| 650 | 4 | |a Mathematisches Modell | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-015091999 | ||
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| id | DE-604.BV021876383 |
| illustrated | Not Illustrated |
| index_date | 2024-07-02T16:03:36Z |
| indexdate | 2024-07-09T20:46:30Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-015091999 |
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| physical | 29 S. |
| publishDate | 1982 |
| publishDateSearch | 1982 |
| publishDateSort | 1982 |
| publisher | Laboratory for Computer Science, Massachusetts Inst. of Technology |
| record_format | marc |
| spelling | Leighton, Frank T. Verfasser aut New lower bound techniques for VLSI Frank Thomson Leighton Cambridge, Mass. Laboratory for Computer Science, Massachusetts Inst. of Technology 1982 29 S. txt rdacontent n rdamedia nc rdacarrier In this paper, crossing number and wire area arguments are used to find lower bounds on the layout area and maximum edge length of a variety of new and computationally useful networks. In particular, an N-node planar graph which has layout are theta(N log N) and maximum edge length theta(N(1/2)/log(1/2)N), an N-node graph with an theta(x 1/2)-separator which has layout area theta(N log(2)N) and maximum edge length theta(N(1/2)logN/loglogN), and an N-node graph with an theta(x(1-1/r)-separator which has maximum edge length theta(N(1-1/r) for any r > or = .3. Lower bounds Thompson grid model VLSI(Very Large Scale Integration) Chips(electronics) dtict Computers dtict Edges dtict Electrical and Electronic Equipment scgdst Graphs dtict Grids dtict Integrated circuits dtict Length dtict Mathematical models dtict Mesh dtict Networks dtict Nodes dtict Space(room) dtict Trees dtict Wire dtict Mathematisches Modell |
| spellingShingle | Leighton, Frank T. New lower bound techniques for VLSI Lower bounds Thompson grid model VLSI(Very Large Scale Integration) Chips(electronics) dtict Computers dtict Edges dtict Electrical and Electronic Equipment scgdst Graphs dtict Grids dtict Integrated circuits dtict Length dtict Mathematical models dtict Mesh dtict Networks dtict Nodes dtict Space(room) dtict Trees dtict Wire dtict Mathematisches Modell |
| title | New lower bound techniques for VLSI |
| title_auth | New lower bound techniques for VLSI |
| title_exact_search | New lower bound techniques for VLSI |
| title_exact_search_txtP | New lower bound techniques for VLSI |
| title_full | New lower bound techniques for VLSI Frank Thomson Leighton |
| title_fullStr | New lower bound techniques for VLSI Frank Thomson Leighton |
| title_full_unstemmed | New lower bound techniques for VLSI Frank Thomson Leighton |
| title_short | New lower bound techniques for VLSI |
| title_sort | new lower bound techniques for vlsi |
| topic | Lower bounds Thompson grid model VLSI(Very Large Scale Integration) Chips(electronics) dtict Computers dtict Edges dtict Electrical and Electronic Equipment scgdst Graphs dtict Grids dtict Integrated circuits dtict Length dtict Mathematical models dtict Mesh dtict Networks dtict Nodes dtict Space(room) dtict Trees dtict Wire dtict Mathematisches Modell |
| topic_facet | Lower bounds Thompson grid model VLSI(Very Large Scale Integration) Chips(electronics) Computers Edges Electrical and Electronic Equipment Graphs Grids Integrated circuits Length Mathematical models Mesh Networks Nodes Space(room) Trees Wire Mathematisches Modell |
| work_keys_str_mv | AT leightonfrankt newlowerboundtechniquesforvlsi |