Holdings: Sequential logic :: THWS Bibkatalog

Sequential logic: analysis and synthesis

Saved in:

Bibliographic Details
Main Author:	Cavanagh, Joseph J. (Author)
Format:	Book
Language:	English
Published:	Boca Raton u.a. CRC/Taylor & Francis 2007
Subjects:	Sequential machine theory Sequenzielle Logik
Online Access:	Table of contents only Publisher description Inhaltsverzeichnis
Item Description:	Includes index.
Physical Description:	XIII, 896 S. Ill. 27 cm
ISBN:	0849375649 9780849375644

Staff View

MARC


LEADER	00000nam a2200000zc 4500
001	BV021772116
003	DE-604
005	20090202
007	t
008	061018s2007 xxua\|\|\| \|\|\|\| 00\|\|\| eng d
010			\|a 2006002621
020			\|a 0849375649 \|c alk. paper \|9 0-8493-7564-9
020			\|a 9780849375644 \|9 978-0-8493-7564-4
035			\|a (OCoLC)63692553
035			\|a (DE-599)BVBBV021772116
040			\|a DE-604 \|b ger \|e aacr
041	0		\|a eng
044			\|a xxu \|c US
049			\|a DE-384 \|a DE-91G
050		0	\|a QA267.5.S4
082	0		\|a 511.3/5
084			\|a ST 125 \|0 (DE-625)143586: \|2 rvk
084			\|a DAT 552f \|2 stub
084			\|a DAT 195f \|2 stub
100	1		\|a Cavanagh, Joseph J. \|e Verfasser \|4 aut
245	1	0	\|a Sequential logic \|b analysis and synthesis \|c Joseph Cavanagh
264		1	\|a Boca Raton u.a. \|b CRC/Taylor & Francis \|c 2007
300			\|a XIII, 896 S. \|b Ill. \|c 27 cm
336			\|b txt \|2 rdacontent
337			\|b n \|2 rdamedia
338			\|b nc \|2 rdacarrier
500			\|a Includes index.
650		4	\|a Sequential machine theory
650	0	7	\|a Sequenzielle Logik \|0 (DE-588)4323079-9 \|2 gnd \|9 rswk-swf
689	0	0	\|a Sequenzielle Logik \|0 (DE-588)4323079-9 \|D s
689	0		\|5 DE-604
856	4		\|u http://www.loc.gov/catdir/toc/ecip068/2006002621.html \|3 Table of contents only
856	4		\|u http://www.loc.gov/catdir/enhancements/fy0654/2006002621-d.html \|3 Publisher description
856	4	2	\|m GBV Datenaustausch \|q application/pdf \|u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=014985033&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA \|3 Inhaltsverzeichnis
999			\|a oai:aleph.bib-bvb.de:BVB01-014985033

Record in the Search Index

_version_	1804135640406687744
adam_text	SEQUENTIAL LOGIC ANALYSIS AND SYNTHESIS JOSEPH CAVAHAGH SANTA CLARA UNIVERSITY R & FRANCIS * TAYLONSI FRANCIS GROUP , BOCA.RATON LONDON NEW YORK CRC IS AN IMPRINT OF THE TAYLOR & FRANCIS GROUP, AN INFORMA BUSINESS CONTENTS PREFACE XI CHAPTER 1 REVIEW OF COMBINATIONAL LOGIC 1 1.1 NUMBER SYSTEMS 2 1.1.1 BINARY NUMBER SYSTEM 3 1.1.2 OCTAL NUMBER SYSTEM 4 1.1.3 DECIMAL NUMBER SYSTEM 4 1.1.4 HEXADECIMAL NUMBER SYSTEM 5 1.2 NUMBER REPRESENTATIONS 8 1.2.1 SIGN MAGNITUDE 8 1.2.2 DIMINISHED-RADIX COMPLEMENT 9 1.2.3 RADIX COMPLEMENT 10 1.3 BOOLEAN ALGEBRA 12 1.4 MINIMIZATION TECHNIQUES 18 1.4.1 ALGEBRAIC MINIMIZATION 19 1.4.2 KARNAUGH MAPS 20 1.4.3 QUINE-MCCLUSKEY ALGORITHM 28 1.5 LOGIC SYMBOLS 35 1.6 ANALYSIS OF COMBINATIONAL LOGIC 37 1.7 SYNTHESIS OF COMBINATIONAL LOGIC 42 1.8 MULTIPLEXERS 45 1.9 DECODERS 47 1.10 ENCODERS 53 . 1.11 COMPARATORS 54 1.12 STORAGE ELEMENTS 56 1.12.1 SR LATCH 57 1.12.2 D FLIP-FLOP 57 1.12.3 JK FLIP-FLOP 59 1.12.4 T FLIP-FLOP 60 1.13 PROGRAMMABLE LOGIC DEVICES 61 1.13.1 PROGRAMMABLE READ-ONLY MEMORIES 61 1.13.2 PROGRAMMABLE ARRAY LOGIC 64 1.13.3 PROGRAMMABLE LOGIC ARRAY 67 1.14 PROBLEMS 69 CHAPTER 2 ANALYSIS OF SYNCHRONOUS SEQUENTIAL MACHINES 77 2.1 SEQUENTIAL CIRCUITS 78 2.1.1 MACHINE ALPHABETS 79 2.1.2 FORMAL DEFINITION OF A SYNCHRONOUS SEQUENTIAL MACHINE 82 VIII CONTENTS 2.2 CLASSES OF SEQUENTIAL MACHINES 89 2.2.1 COMBINATIONAL LOGIC 89 2.2.2 REGISTERS 93 . ,;. 5 . 2.2.3 COUNTERS 98 2.2.4 MOORE MACHINES 105 2.2.5 MEALY MACHINES 110 2.2.6 ASYNCHRONOUS SEQUENTIAL MACHINES 121 2.2.7 ADDITIONAL DEFINITIONS FOR SYNCHRONOUS SEQUENTIAL . MACHINES 123 2.3 METHODS OF ANALYSIS 136 2.3.1. NEXT-STATE TABLE 136 2.3.2 PRESENT-STATE MAP 137 2.3.3 NEXT-STATE MAP 137 2.3.4 INPUT MAP 138 2.3.5 OUTPUT MAP 140; , . -. 2.3.6 TIMING DIAGRAM 141 .. 2.3.7 STATE DIAGRAM 143 2.3.8 ANALYSIS EXAMPLES 146 2.4 COMPLETE AND INCOMPLETE SYNCHRONOUS SEQUENTIAL MACHINES 161 2.4.1 COMPLETE SYNCHRONOUS SEQUENTIAL,MACHINES 161 2.4.2 INCOMPLETE SYNCHRONOUS SEQUENTIAL MACHINES 162 2.5 PROBLEMS 166 . . CHAPTER 3 SYNTHESIS OF SYNCHRONOUS SEQUENTIAL MACHINES 1181 3.1 SYNTHESIS PROCEDURE 182 3.1.1 EQUIVALENT STATES 183 3.2 SYNCHRONOUS REGISTERS 197 3.2.1 PARALLEL-IN, PARALLEL-OUT REGISTERS 197 3.2.2 PARALLEL-IN, SERIAL-OUT REGISTERS 201 3.2.3 - SERIAL-IRI, PARALLEL-OUT REGISTERS 205 3.2.4 SERIAL-IN^ SERIAL-OUT REGISTERS 208 3.2.5 LINEAR FEEDBACK SHIFT REGISTERS 212 3.2.6 COMBINATIONAL SHIFTER 218 3.3 SYNCHRONOUS COUNTERS 223 3.3.1 MODULO-8 COUNTER 223 3.3.2 MODULO-10 COUNTER234 ; , V - .- , 3.3.3 JOHNSON COUNTER 245 3.3.4 BINARY-TO-GRAY CODE CONVERTER 248 3.4 MOORE MACHINES 254 , ..-. * : ; 3.5. MEALY MACHINES 277 ..* , : 3.6 MOORE-MEALY EQUIVALENCE 298 B .. : 3.6.1 MEALY-TO-MOORE TRANSFORMATION 298 3.6.2 MOORE-TO-MEALY TRANSFORMATION 307 3.7 OUTPUT GLITCHES 307 CONTENTS IX 3.7.1 GLITCH ELIMINATION USING STATE CODE ASSIGNMENT 312 3.7.2 GLITCH ELIMINATION USING STORAGE ELEMENTS 319 3.7.3 GLITCH ELIMINATION USING COMPLEMENTED CLOCK 323 3.7.4 GLITCH ELIMINATION USING DELAYED CLOCK 326 3.7.5 GLITCHES AND OUTPUT MAPS 333 -....- 3.7.6 COMPENDIUM OF OUTPUT GLITCHES 339 3.8 PROBLEMS 344 CHAPTER 4 SYNTHESIS OF SYNCHRONOUS SEQUENTIAL MACHINES 2 361 4.1 MULTIPLEXERS FOR 8 NEXT-STATE LOGIC 361 4.1.1 LINEAR-SELECT MULTIPLEXERS 363 4.1.2 NONLINEAR-SELECT MULTIPLEXERS 377 4.2 DECODERS FOR 1 OUTPUT LOGIC 400 4.3 PROGRAMMABLE LOGIC DEVICES 412 4.3.1 PROGRAMMABLE READ-ONLY MEMORY 413 4.3.2 PROGRAMMABLE ARRAY LOGIC 421 , ..,., .4.3.3 PROGRAMMABLE LOGIC ARRAY 432 ., . * 4-3.4 FIELD-PROGRAMMABLE GATE ARRAY 437 4.4 A MICROPROCESSOR-CONTROLLED SEQUENTIAL MACHINES 448 , R .... , 4.4..1 GENERAL CONSIDERATIONS 449 , ... .,- 4.4.2 MEALY MACHINE SYNTHESIS 453 .-,. 4.4.3 MACHINE STATE AUGMENTATION 461 , 4.4.4 MOORE AND MEALY OUTPUTS 466 4.4.5 SYSTEM ARCHITECTURE 467 4.4.6 MULTIPLE MACHINES 477 4.5 SEQUENTIAL ITERATIVE MACHINES 481 4.6 ERROR DETECTION IN SYNCHRONOUS SEQUENTIAL MACHINES 489 : : 4:7- PROBLEMS 500 * * * * * : - * ; CHAPTER 5 ANALYSIS OF ASYNCHRONOUS SEQUENTIAL MACHINES 519 5.1 INTRODUCTION 520 . 5.2 FUNDAMENTAL-MODE MODEL 522 5.3 * .METHODS OF ANALYSIS 526 5.4. ; HAZARDS 553 : . 5.4.1 STATIC HAZARDS 553 .. 5.4.2 DYNAMIC HAZARDS 568 5.4.3 ESSENTIAL HAZARDS 572 5.4.4 MULTIPLE-ORDER HAZARDS 577 5.5 OSCILLATIONS 578 , ., . * ., : ,. * 5.6 RACES 582 5.6.1 NONCRITICAL RACES 583 , 5.6.2 CYCLES 586 CONTENTS 5.6.3 CRITICAL RACES 586 5.7 PROBLEMS 590 CHAPTER 6 SYNTHESIS OF ASYNCHRONOUS SEQUENTIAL MACHINES 607 . 6.1 INTRODUCTION 608 6.2 SYNTHESIS PROCEDURE 610 6.2.1 STATE DIAGRAM 612 6.2.2 PRIMITIVE FLOW TABLE 616 6.2.3 EQUIVALENT STATES 632 6.2.4 MERGER DIAGRAM 645 6.2.5 MERGED FLOW TABLE 656 6.2.6 EXCITATION MAPS AND EQUATIONS 661 6.2.7 OUTPUT MAPS AND EQUATIONS 691 6.2.8 LOGIC DIAGRAM 710 6.3 SYNTHESIS EXAMPLES 716 6.3.1 MEALY MACHINE WITH TWO INPUTS AND ONE OUTPUT 716 6.3.2 MEALY MACHINE WITH TWO INPUTS AND ONE OUTPUT USING A PROGRAMMABLE LOGIC ARRAY (PLA) 727 6.3.3 MOORE MACHINE WITH ONE INPUT AND ONE OUTPUT 735 6.3.4 MEALY MACHINE WITH TWO INPUTS AND TWO OUTPUTS 741 6.3.5 MEALY MACHINE WITH THREE INPUTS AND ONE OUTPUT 755 6.3.6 MEALY MACHINE WITH TWO INPUTS AND TWO OUTPUTS 765 6.4 PROBLEMS 777 CHAPTER 7 PULSE-MODE ASYNCHRONOUS SEQUENTIAL MACHINES 807 7.1 ANALYSIS PROCEDURE 809 7.1.1 57? LATCHES AS STORAGE ELEMENTS 810 7.1.2 57? LATCHES WITH D FLIP-FLOPS AS STORAGE ELEMENTS 817 7.2 SYNTHESIS PROCEDURE 823 7.2.1 SR LATCHES AS STORAGE ELEMENTS 823 7.2.2 T FLIP-FLOPS AS STORAGE ELEMENTS 830 7.2.3 57?-R FLIP-FLOPS AS STORAGE ELEMENTS 836 7.2.4 57? LATCHES WITH D FLIP-FLOPS AS STORAGE ELEMENTS 844 7.3 PROBLEMS 850 APPENDIX ANSWERS TO SELECTED PROBLEMS 861 INDEX 889
adam_txt	SEQUENTIAL LOGIC ANALYSIS AND SYNTHESIS JOSEPH CAVAHAGH SANTA CLARA UNIVERSITY R & FRANCIS * TAYLONSI FRANCIS GROUP , BOCA.RATON LONDON NEW YORK \ CRC IS AN IMPRINT OF THE TAYLOR & FRANCIS GROUP, AN INFORMA BUSINESS CONTENTS PREFACE XI CHAPTER 1 REVIEW OF COMBINATIONAL LOGIC 1 1.1 NUMBER SYSTEMS 2 1.1.1 BINARY NUMBER SYSTEM 3 1.1.2 OCTAL NUMBER SYSTEM 4 1.1.3 DECIMAL NUMBER SYSTEM 4 1.1.4 HEXADECIMAL NUMBER SYSTEM 5 1.2 NUMBER REPRESENTATIONS 8 1.2.1 SIGN MAGNITUDE 8 1.2.2 DIMINISHED-RADIX COMPLEMENT 9 1.2.3 RADIX COMPLEMENT 10 1.3 BOOLEAN ALGEBRA 12 1.4 MINIMIZATION TECHNIQUES 18 1.4.1 ALGEBRAIC MINIMIZATION 19 1.4.2 KARNAUGH MAPS 20 1.4.3 QUINE-MCCLUSKEY ALGORITHM 28 1.5 LOGIC SYMBOLS 35 1.6 ANALYSIS OF COMBINATIONAL LOGIC 37 1.7 SYNTHESIS OF COMBINATIONAL LOGIC 42 1.8 MULTIPLEXERS 45 1.9 DECODERS 47 1.10 ENCODERS 53 . 1.11 COMPARATORS 54 1.12 STORAGE ELEMENTS 56 1.12.1 SR LATCH 57 1.12.2 D FLIP-FLOP 57 1.12.3 JK FLIP-FLOP 59 1.12.4 T FLIP-FLOP 60 1.13 PROGRAMMABLE LOGIC DEVICES 61 1.13.1 PROGRAMMABLE READ-ONLY MEMORIES 61 1.13.2 PROGRAMMABLE ARRAY LOGIC 64 1.13.3 PROGRAMMABLE LOGIC ARRAY 67 1.14 PROBLEMS 69 CHAPTER 2 ANALYSIS OF SYNCHRONOUS SEQUENTIAL MACHINES 77 2.1 SEQUENTIAL CIRCUITS 78 2.1.1 MACHINE ALPHABETS 79 2.1.2 FORMAL DEFINITION OF A SYNCHRONOUS SEQUENTIAL MACHINE 82 ' VIII CONTENTS 2.2 CLASSES OF SEQUENTIAL MACHINES 89 2.2.1 COMBINATIONAL LOGIC 89 2.2.2 REGISTERS 93 . ,;. 5 . 2.2.3 COUNTERS 98 2.2.4 MOORE MACHINES 105 2.2.5 MEALY MACHINES 110 2.2.6 ASYNCHRONOUS SEQUENTIAL MACHINES 121 2.2.7 ADDITIONAL DEFINITIONS FOR SYNCHRONOUS SEQUENTIAL . MACHINES 123 2.3 METHODS OF ANALYSIS 136 2.3.1. NEXT-STATE TABLE 136 2.3.2 PRESENT-STATE MAP 137 2.3.3 NEXT-STATE MAP 137 2.3.4 INPUT MAP 138 2.3.5 OUTPUT MAP 140; , . -. 2.3.6 TIMING DIAGRAM 141 . 2.3.7 STATE DIAGRAM 143 2.3.8 ANALYSIS EXAMPLES 146 2.4 COMPLETE AND INCOMPLETE SYNCHRONOUS SEQUENTIAL MACHINES 161 2.4.1 COMPLETE SYNCHRONOUS SEQUENTIAL,MACHINES 161 2.4.2 INCOMPLETE SYNCHRONOUS SEQUENTIAL MACHINES 162 2.5 PROBLEMS 166 . . CHAPTER 3 SYNTHESIS OF SYNCHRONOUS SEQUENTIAL MACHINES 1181 3.1 SYNTHESIS PROCEDURE 182 3.1.1 EQUIVALENT STATES 183 3.2 SYNCHRONOUS REGISTERS 197 3.2.1 PARALLEL-IN, PARALLEL-OUT REGISTERS 197 3.2.2 PARALLEL-IN, SERIAL-OUT REGISTERS 201 3.2.3'- SERIAL-IRI, PARALLEL-OUT REGISTERS 205 3.2.4 SERIAL-IN^ SERIAL-OUT REGISTERS 208 3.2.5 LINEAR FEEDBACK SHIFT REGISTERS 212 3.2.6 COMBINATIONAL SHIFTER 218 ' 3.3 SYNCHRONOUS COUNTERS 223 3.3.1 MODULO-8 COUNTER 223 3.3.2 MODULO-10 COUNTER234 ; , " V - .- ,' 3.3.3 JOHNSON COUNTER 245 3.3.4 BINARY-TO-GRAY CODE CONVERTER 248 3.4 MOORE MACHINES 254 , .-. * : ; 3.5. MEALY MACHINES 277 .* , : 3.6 MOORE-MEALY EQUIVALENCE 298 B . : 3.6.1 MEALY-TO-MOORE TRANSFORMATION 298 3.6.2 MOORE-TO-MEALY TRANSFORMATION 307 3.7 OUTPUT GLITCHES 307 CONTENTS IX 3.7.1 GLITCH ELIMINATION USING STATE CODE ASSIGNMENT 312 3.7.2 GLITCH ELIMINATION USING STORAGE ELEMENTS 319 ' 3.7.3 GLITCH ELIMINATION USING COMPLEMENTED CLOCK 323 3.7.4 GLITCH ELIMINATION USING DELAYED CLOCK 326 3.7.5 GLITCHES AND OUTPUT MAPS 333 -.- 3.7.6 COMPENDIUM OF OUTPUT GLITCHES 339 3.8 PROBLEMS 344 CHAPTER 4 SYNTHESIS OF SYNCHRONOUS SEQUENTIAL MACHINES 2 361 4.1 MULTIPLEXERS FOR 8 NEXT-STATE LOGIC 361 4.1.1 LINEAR-SELECT MULTIPLEXERS 363 4.1.2 NONLINEAR-SELECT MULTIPLEXERS 377 4.2 DECODERS FOR 1 OUTPUT LOGIC 400 4.3 PROGRAMMABLE LOGIC DEVICES 412 4.3.1 PROGRAMMABLE READ-ONLY MEMORY 413 4.3.2 PROGRAMMABLE ARRAY LOGIC 421 ,' ' .,., .4.3.3 PROGRAMMABLE LOGIC ARRAY 432 ., .' * 4-3.4 FIELD-PROGRAMMABLE GATE ARRAY 437 4.4 A MICROPROCESSOR-CONTROLLED SEQUENTIAL MACHINES 448 , R . , 4.4.1 GENERAL CONSIDERATIONS 449 , . .,- 4.4.2 MEALY MACHINE SYNTHESIS 453 .-,. 4.4.3 MACHINE STATE AUGMENTATION 461 , 4.4.4 MOORE AND MEALY OUTPUTS 466 4.4.5 SYSTEM ARCHITECTURE 467 4.4.6 MULTIPLE MACHINES 477 4.5 SEQUENTIAL ITERATIVE MACHINES 481 4.6 ERROR DETECTION IN SYNCHRONOUS SEQUENTIAL MACHINES 489 : ' : 4:7-"' PROBLEMS 500 * * * * * ' " : - * ' ; CHAPTER 5 ANALYSIS OF ASYNCHRONOUS SEQUENTIAL MACHINES 519 5.1 INTRODUCTION 520 . 5.2 FUNDAMENTAL-MODE MODEL 522 5.3 * .METHODS OF ANALYSIS 526 5.4. ; HAZARDS 553 : . 5.4.1 STATIC HAZARDS 553 . 5.4.2 DYNAMIC HAZARDS 568 5.4.3 ESSENTIAL HAZARDS 572 5.4.4 MULTIPLE-ORDER HAZARDS 577 5.5 OSCILLATIONS 578 , ., . * ., : ,. * 5.6 RACES 582 ' ''''' ' ' 5.6.1 NONCRITICAL RACES 583 , 5.6.2 CYCLES 586 CONTENTS 5.6.3 CRITICAL RACES 586 5.7 PROBLEMS 590 CHAPTER 6 SYNTHESIS OF ASYNCHRONOUS SEQUENTIAL MACHINES 607 . 6.1 INTRODUCTION 608 6.2 SYNTHESIS PROCEDURE 610 6.2.1 STATE DIAGRAM 612 6.2.2 PRIMITIVE FLOW TABLE 616 6.2.3 EQUIVALENT STATES 632 6.2.4 MERGER DIAGRAM 645 6.2.5 MERGED FLOW TABLE 656 6.2.6 EXCITATION' MAPS AND EQUATIONS 661 6.2.7 OUTPUT MAPS AND EQUATIONS 691 6.2.8 LOGIC DIAGRAM 710 6.3 SYNTHESIS EXAMPLES 716 6.3.1 MEALY MACHINE WITH TWO INPUTS AND ONE OUTPUT 716 6.3.2 MEALY MACHINE WITH TWO INPUTS AND ONE OUTPUT USING A PROGRAMMABLE LOGIC ARRAY (PLA) 727 6.3.3 MOORE MACHINE WITH ONE INPUT AND ONE OUTPUT 735 6.3.4 MEALY MACHINE WITH TWO INPUTS AND TWO OUTPUTS 741 6.3.5 MEALY MACHINE WITH THREE INPUTS AND ONE OUTPUT 755 6.3.6 MEALY MACHINE WITH TWO INPUTS AND TWO OUTPUTS 765 6.4 PROBLEMS 777 ' CHAPTER 7 PULSE-MODE ASYNCHRONOUS SEQUENTIAL MACHINES 807 7.1 ANALYSIS PROCEDURE 809 7.1.1 57? LATCHES AS STORAGE ELEMENTS 810 7.1.2 57? LATCHES WITH D FLIP-FLOPS AS STORAGE ELEMENTS 817 7.2 SYNTHESIS PROCEDURE 823 7.2.1 SR LATCHES AS STORAGE ELEMENTS 823 7.2.2 T FLIP-FLOPS AS STORAGE ELEMENTS 830 7.2.3 57?-R FLIP-FLOPS AS STORAGE ELEMENTS 836 7.2.4 57? LATCHES WITH D FLIP-FLOPS AS STORAGE ELEMENTS 844 7.3 PROBLEMS 850 APPENDIX ANSWERS TO SELECTED PROBLEMS 861 INDEX 889
any_adam_object	1
any_adam_object_boolean	1
author	Cavanagh, Joseph J.
author_facet	Cavanagh, Joseph J.
author_role	aut
author_sort	Cavanagh, Joseph J.
author_variant	j j c jj jjc
building	Verbundindex
bvnumber	BV021772116
callnumber-first	Q - Science
callnumber-label	QA267
callnumber-raw	QA267.5.S4
callnumber-search	QA267.5.S4
callnumber-sort	QA 3267.5 S4
callnumber-subject	QA - Mathematics
classification_rvk	ST 125
classification_tum	DAT 552f DAT 195f
ctrlnum	(OCoLC)63692553 (DE-599)BVBBV021772116
dewey-full	511.3/5
dewey-hundreds	500 - Natural sciences and mathematics
dewey-ones	511 - General principles of mathematics
dewey-raw	511.3/5
dewey-search	511.3/5
dewey-sort	3511.3 15
dewey-tens	510 - Mathematics
discipline	Informatik Mathematik
discipline_str_mv	Informatik Mathematik
format	Book
fullrecord	<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01670nam a2200445zc 4500</leader><controlfield tag="001">BV021772116</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20090202 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">061018s2007 xxua\|\|\| \|\|\|\| 00\|\|\| eng d</controlfield><datafield tag="010" ind1=" " ind2=" "><subfield code="a">2006002621</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0849375649</subfield><subfield code="c">alk. paper</subfield><subfield code="9">0-8493-7564-9</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780849375644</subfield><subfield code="9">978-0-8493-7564-4</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)63692553</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV021772116</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="044" ind1=" " ind2=" "><subfield code="a">xxu</subfield><subfield code="c">US</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-384</subfield><subfield code="a">DE-91G</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">QA267.5.S4</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">511.3/5</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 125</subfield><subfield code="0">(DE-625)143586:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">DAT 552f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">DAT 195f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Cavanagh, Joseph J.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Sequential logic</subfield><subfield code="b">analysis and synthesis</subfield><subfield code="c">Joseph Cavanagh</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boca Raton u.a.</subfield><subfield code="b">CRC/Taylor & Francis</subfield><subfield code="c">2007</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XIII, 896 S.</subfield><subfield code="b">Ill.</subfield><subfield code="c">27 cm</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Includes index.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Sequential machine theory</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Sequenzielle Logik</subfield><subfield code="0">(DE-588)4323079-9</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Sequenzielle Logik</subfield><subfield code="0">(DE-588)4323079-9</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="856" ind1="4" ind2=" "><subfield code="u">http://www.loc.gov/catdir/toc/ecip068/2006002621.html</subfield><subfield code="3">Table of contents only</subfield></datafield><datafield tag="856" ind1="4" ind2=" "><subfield code="u">http://www.loc.gov/catdir/enhancements/fy0654/2006002621-d.html</subfield><subfield code="3">Publisher description</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">GBV Datenaustausch</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=014985033&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-014985033</subfield></datafield></record></collection>
id	DE-604.BV021772116
illustrated	Illustrated
index_date	2024-07-02T15:38:48Z
indexdate	2024-07-09T20:43:43Z
institution	BVB
isbn	0849375649 9780849375644
language	English
lccn	2006002621
oai_aleph_id	oai:aleph.bib-bvb.de:BVB01-014985033
oclc_num	63692553
open_access_boolean
owner	DE-384 DE-91G DE-BY-TUM
owner_facet	DE-384 DE-91G DE-BY-TUM
physical	XIII, 896 S. Ill. 27 cm
publishDate	2007
publishDateSearch	2007
publishDateSort	2007
publisher	CRC/Taylor & Francis
record_format	marc
spelling	Cavanagh, Joseph J. Verfasser aut Sequential logic analysis and synthesis Joseph Cavanagh Boca Raton u.a. CRC/Taylor & Francis 2007 XIII, 896 S. Ill. 27 cm txt rdacontent n rdamedia nc rdacarrier Includes index. Sequential machine theory Sequenzielle Logik (DE-588)4323079-9 gnd rswk-swf Sequenzielle Logik (DE-588)4323079-9 s DE-604 http://www.loc.gov/catdir/toc/ecip068/2006002621.html Table of contents only http://www.loc.gov/catdir/enhancements/fy0654/2006002621-d.html Publisher description GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=014985033&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis
spellingShingle	Cavanagh, Joseph J. Sequential logic analysis and synthesis Sequential machine theory Sequenzielle Logik (DE-588)4323079-9 gnd
subject_GND	(DE-588)4323079-9
title	Sequential logic analysis and synthesis
title_auth	Sequential logic analysis and synthesis
title_exact_search	Sequential logic analysis and synthesis
title_exact_search_txtP	Sequential logic analysis and synthesis
title_full	Sequential logic analysis and synthesis Joseph Cavanagh
title_fullStr	Sequential logic analysis and synthesis Joseph Cavanagh
title_full_unstemmed	Sequential logic analysis and synthesis Joseph Cavanagh
title_short	Sequential logic
title_sort	sequential logic analysis and synthesis
title_sub	analysis and synthesis
topic	Sequential machine theory Sequenzielle Logik (DE-588)4323079-9 gnd
topic_facet	Sequential machine theory Sequenzielle Logik
url	http://www.loc.gov/catdir/toc/ecip068/2006002621.html http://www.loc.gov/catdir/enhancements/fy0654/2006002621-d.html http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=014985033&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
work_keys_str_mv	AT cavanaghjosephj sequentiallogicanalysisandsynthesis

Holdings

There is no print copy available.

Interlibrary loan Place Request Caution: Not in THWS collection! Indexes

MARC

Record in the Search Index

There is no print copy available.

Similar Items