A parallel algorithm synthesis procedure for high performance computer architectures:
Saved in:
| Main Authors: | , |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
New York [u.a.]
Kluwer Academic/Plenum Publ.
2003
|
| Series: | Series in computer science
|
| Subjects: | |
| Online Access: | Table of contents |
| Item Description: | Includes bibliographical references (p. 103-106) and index |
| Physical Description: | XI, 108 S. Ill. |
| ISBN: | 0306477432 |
Staff View
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| id | DE-604.BV021739060 |
| illustrated | Illustrated |
| index_date | 2024-07-02T15:28:49Z |
| indexdate | 2024-08-01T00:28:01Z |
| institution | BVB |
| isbn | 0306477432 |
| language | English |
| lccn | 2003044716 |
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| physical | XI, 108 S. Ill. |
| publishDate | 2003 |
| publishDateSearch | 2003 |
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| publisher | Kluwer Academic/Plenum Publ. |
| record_format | marc |
| series2 | Series in computer science |
| spelling | Dunn, Ian N. Verfasser aut A parallel algorithm synthesis procedure for high performance computer architectures Ian N. Dunn and Gerard G. L. Meyer New York [u.a.] Kluwer Academic/Plenum Publ. 2003 XI, 108 S. Ill. txt rdacontent n rdamedia nc rdacarrier Series in computer science Includes bibliographical references (p. 103-106) and index Datenverarbeitung Computer architecture Electronic data processing Distributed processing High performance computing Parallel algorithms Parallel programming (Computer science) Hochleistungsrechnen (DE-588)4532701-4 gnd rswk-swf Paralleler Algorithmus (DE-588)4193615-2 gnd rswk-swf Hochleistungsrechnen (DE-588)4532701-4 s Paralleler Algorithmus (DE-588)4193615-2 s DE-604 Meyer, Gerard G. L. Verfasser aut http://www.loc.gov/catdir/toc/fy042/2003044716.html Table of contents |
| spellingShingle | Dunn, Ian N. Meyer, Gerard G. L. A parallel algorithm synthesis procedure for high performance computer architectures Datenverarbeitung Computer architecture Electronic data processing Distributed processing High performance computing Parallel algorithms Parallel programming (Computer science) Hochleistungsrechnen (DE-588)4532701-4 gnd Paralleler Algorithmus (DE-588)4193615-2 gnd |
| subject_GND | (DE-588)4532701-4 (DE-588)4193615-2 |
| title | A parallel algorithm synthesis procedure for high performance computer architectures |
| title_auth | A parallel algorithm synthesis procedure for high performance computer architectures |
| title_exact_search | A parallel algorithm synthesis procedure for high performance computer architectures |
| title_exact_search_txtP | A parallel algorithm synthesis procedure for high performance computer architectures |
| title_full | A parallel algorithm synthesis procedure for high performance computer architectures Ian N. Dunn and Gerard G. L. Meyer |
| title_fullStr | A parallel algorithm synthesis procedure for high performance computer architectures Ian N. Dunn and Gerard G. L. Meyer |
| title_full_unstemmed | A parallel algorithm synthesis procedure for high performance computer architectures Ian N. Dunn and Gerard G. L. Meyer |
| title_short | A parallel algorithm synthesis procedure for high performance computer architectures |
| title_sort | a parallel algorithm synthesis procedure for high performance computer architectures |
| topic | Datenverarbeitung Computer architecture Electronic data processing Distributed processing High performance computing Parallel algorithms Parallel programming (Computer science) Hochleistungsrechnen (DE-588)4532701-4 gnd Paralleler Algorithmus (DE-588)4193615-2 gnd |
| topic_facet | Datenverarbeitung Computer architecture Electronic data processing Distributed processing High performance computing Parallel algorithms Parallel programming (Computer science) Hochleistungsrechnen Paralleler Algorithmus |
| url | http://www.loc.gov/catdir/toc/fy042/2003044716.html |
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