A parallel algorithm synthesis procedure for high performance computer architectures:
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
New York [u.a.]
Kluwer Academic/Plenum Publ.
2003
|
| Schriftenreihe: | Series in computer science
|
| Schlagworte: | |
| Online-Zugang: | Table of contents |
| Beschreibung: | Includes bibliographical references (p. 103-106) and index |
| Beschreibung: | XI, 108 S. Ill. |
| ISBN: | 0306477432 |
Internformat
MARC
| LEADER | 00000nam a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV021739060 | ||
| 003 | DE-604 | ||
| 005 | 20061222 | ||
| 007 | t | ||
| 008 | 060921s2003 xxua||| |||| 00||| eng d | ||
| 010 | |a 2003044716 | ||
| 020 | |a 0306477432 |9 0-306-47743-2 | ||
| 035 | |a (OCoLC)249295984 | ||
| 035 | |a (DE-599)BVBBV021739060 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 044 | |a xxu |c US | ||
| 050 | 0 | |a QA76.642 | |
| 082 | 0 | |a 005.2/75 |2 21 | |
| 084 | |a ST 151 |0 (DE-625)143595: |2 rvk | ||
| 100 | 1 | |a Dunn, Ian N. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a A parallel algorithm synthesis procedure for high performance computer architectures |c Ian N. Dunn and Gerard G. L. Meyer |
| 264 | 1 | |a New York [u.a.] |b Kluwer Academic/Plenum Publ. |c 2003 | |
| 300 | |a XI, 108 S. |b Ill. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 0 | |a Series in computer science | |
| 500 | |a Includes bibliographical references (p. 103-106) and index | ||
| 650 | 4 | |a Datenverarbeitung | |
| 650 | 4 | |a Computer architecture | |
| 650 | 4 | |a Electronic data processing |x Distributed processing | |
| 650 | 4 | |a High performance computing | |
| 650 | 4 | |a Parallel algorithms | |
| 650 | 4 | |a Parallel programming (Computer science) | |
| 650 | 0 | 7 | |a Hochleistungsrechnen |0 (DE-588)4532701-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Paralleler Algorithmus |0 (DE-588)4193615-2 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Hochleistungsrechnen |0 (DE-588)4532701-4 |D s |
| 689 | 0 | 1 | |a Paralleler Algorithmus |0 (DE-588)4193615-2 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Meyer, Gerard G. L. |e Verfasser |4 aut | |
| 856 | 4 | |u http://www.loc.gov/catdir/toc/fy042/2003044716.html |3 Table of contents | |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-014952454 | |
Datensatz im Suchindex
| _version_ | 1806142885668585472 |
|---|---|
| adam_text | |
| adam_txt | |
| any_adam_object | |
| any_adam_object_boolean | |
| author | Dunn, Ian N. Meyer, Gerard G. L. |
| author_facet | Dunn, Ian N. Meyer, Gerard G. L. |
| author_role | aut aut |
| author_sort | Dunn, Ian N. |
| author_variant | i n d in ind g g l m ggl gglm |
| building | Verbundindex |
| bvnumber | BV021739060 |
| callnumber-first | Q - Science |
| callnumber-label | QA76 |
| callnumber-raw | QA76.642 |
| callnumber-search | QA76.642 |
| callnumber-sort | QA 276.642 |
| callnumber-subject | QA - Mathematics |
| classification_rvk | ST 151 |
| ctrlnum | (OCoLC)249295984 (DE-599)BVBBV021739060 |
| dewey-full | 005.2/75 |
| dewey-hundreds | 000 - Computer science, information, general works |
| dewey-ones | 005 - Computer programming, programs, data, security |
| dewey-raw | 005.2/75 |
| dewey-search | 005.2/75 |
| dewey-sort | 15.2 275 |
| dewey-tens | 000 - Computer science, information, general works |
| discipline | Informatik |
| discipline_str_mv | Informatik |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>00000nam a2200000zc 4500</leader><controlfield tag="001">BV021739060</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20061222</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">060921s2003 xxua||| |||| 00||| eng d</controlfield><datafield tag="010" ind1=" " ind2=" "><subfield code="a">2003044716</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0306477432</subfield><subfield code="9">0-306-47743-2</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)249295984</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV021739060</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="044" ind1=" " ind2=" "><subfield code="a">xxu</subfield><subfield code="c">US</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">QA76.642</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">005.2/75</subfield><subfield code="2">21</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 151</subfield><subfield code="0">(DE-625)143595:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Dunn, Ian N.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">A parallel algorithm synthesis procedure for high performance computer architectures</subfield><subfield code="c">Ian N. Dunn and Gerard G. L. Meyer</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">New York [u.a.]</subfield><subfield code="b">Kluwer Academic/Plenum Publ.</subfield><subfield code="c">2003</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XI, 108 S.</subfield><subfield code="b">Ill.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="0" ind2=" "><subfield code="a">Series in computer science</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Includes bibliographical references (p. 103-106) and index</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Datenverarbeitung</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer architecture</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronic data processing</subfield><subfield code="x">Distributed processing</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">High performance computing</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Parallel algorithms</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Parallel programming (Computer science)</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Hochleistungsrechnen</subfield><subfield code="0">(DE-588)4532701-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Paralleler Algorithmus</subfield><subfield code="0">(DE-588)4193615-2</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Hochleistungsrechnen</subfield><subfield code="0">(DE-588)4532701-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Paralleler Algorithmus</subfield><subfield code="0">(DE-588)4193615-2</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Meyer, Gerard G. L.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="856" ind1="4" ind2=" "><subfield code="u">http://www.loc.gov/catdir/toc/fy042/2003044716.html</subfield><subfield code="3">Table of contents</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-014952454</subfield></datafield></record></collection> |
| id | DE-604.BV021739060 |
| illustrated | Illustrated |
| index_date | 2024-07-02T15:28:49Z |
| indexdate | 2024-08-01T00:28:01Z |
| institution | BVB |
| isbn | 0306477432 |
| language | English |
| lccn | 2003044716 |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-014952454 |
| oclc_num | 249295984 |
| open_access_boolean | |
| owner | DE-703 |
| owner_facet | DE-703 |
| physical | XI, 108 S. Ill. |
| publishDate | 2003 |
| publishDateSearch | 2003 |
| publishDateSort | 2003 |
| publisher | Kluwer Academic/Plenum Publ. |
| record_format | marc |
| series2 | Series in computer science |
| spelling | Dunn, Ian N. Verfasser aut A parallel algorithm synthesis procedure for high performance computer architectures Ian N. Dunn and Gerard G. L. Meyer New York [u.a.] Kluwer Academic/Plenum Publ. 2003 XI, 108 S. Ill. txt rdacontent n rdamedia nc rdacarrier Series in computer science Includes bibliographical references (p. 103-106) and index Datenverarbeitung Computer architecture Electronic data processing Distributed processing High performance computing Parallel algorithms Parallel programming (Computer science) Hochleistungsrechnen (DE-588)4532701-4 gnd rswk-swf Paralleler Algorithmus (DE-588)4193615-2 gnd rswk-swf Hochleistungsrechnen (DE-588)4532701-4 s Paralleler Algorithmus (DE-588)4193615-2 s DE-604 Meyer, Gerard G. L. Verfasser aut http://www.loc.gov/catdir/toc/fy042/2003044716.html Table of contents |
| spellingShingle | Dunn, Ian N. Meyer, Gerard G. L. A parallel algorithm synthesis procedure for high performance computer architectures Datenverarbeitung Computer architecture Electronic data processing Distributed processing High performance computing Parallel algorithms Parallel programming (Computer science) Hochleistungsrechnen (DE-588)4532701-4 gnd Paralleler Algorithmus (DE-588)4193615-2 gnd |
| subject_GND | (DE-588)4532701-4 (DE-588)4193615-2 |
| title | A parallel algorithm synthesis procedure for high performance computer architectures |
| title_auth | A parallel algorithm synthesis procedure for high performance computer architectures |
| title_exact_search | A parallel algorithm synthesis procedure for high performance computer architectures |
| title_exact_search_txtP | A parallel algorithm synthesis procedure for high performance computer architectures |
| title_full | A parallel algorithm synthesis procedure for high performance computer architectures Ian N. Dunn and Gerard G. L. Meyer |
| title_fullStr | A parallel algorithm synthesis procedure for high performance computer architectures Ian N. Dunn and Gerard G. L. Meyer |
| title_full_unstemmed | A parallel algorithm synthesis procedure for high performance computer architectures Ian N. Dunn and Gerard G. L. Meyer |
| title_short | A parallel algorithm synthesis procedure for high performance computer architectures |
| title_sort | a parallel algorithm synthesis procedure for high performance computer architectures |
| topic | Datenverarbeitung Computer architecture Electronic data processing Distributed processing High performance computing Parallel algorithms Parallel programming (Computer science) Hochleistungsrechnen (DE-588)4532701-4 gnd Paralleler Algorithmus (DE-588)4193615-2 gnd |
| topic_facet | Datenverarbeitung Computer architecture Electronic data processing Distributed processing High performance computing Parallel algorithms Parallel programming (Computer science) Hochleistungsrechnen Paralleler Algorithmus |
| url | http://www.loc.gov/catdir/toc/fy042/2003044716.html |
| work_keys_str_mv | AT dunniann aparallelalgorithmsynthesisprocedureforhighperformancecomputerarchitectures AT meyergerardgl aparallelalgorithmsynthesisprocedureforhighperformancecomputerarchitectures |