Fast, efficient and predictable memory accesses: optimization algorithms for memory architecture aware compilation
Gespeichert in:
| 1. Verfasser: | |
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| Format: | Abschlussarbeit Buch |
| Sprache: | English |
| Veröffentlicht: |
2005
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| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XVI, 288 S. graph. Darst. 30 cm |
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| 245 | 1 | 0 | |a Fast, efficient and predictable memory accesses |b optimization algorithms for memory architecture aware compilation |c von Lars Wehmeyer |
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Datensatz im Suchindex
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| adam_text | FAST, EFFICIENT AND PREDICTABLE MEMORY ACCESSES
OPTIMIZATION ALGORITHMS FOR MEMORY
ARCHITECTURE AWARE COMPILATION
DISSERTATION
ZUR ERLANGUNG DES GRADES EINES
DOKTOR
S DE
R NATU
R W I SSENSCHAFTE
N
DER UNIVERSITAT DORTMUND
AM FACHBEREICH INFORMATIK
VON
LARS WEHMEYER
DORTMUND
2005
ULB DARMSTADT
ILLLLLLLLLLLLLLLLLL
L
16323551
CONTENTS
DEDICATION III
LIST OF FIGURES IX
LIST OF TABLES XVI
ACKNOWLEDGMENTS XVII
1. ABSTRACT 1
2. INTRODUCTION 3
2.1 MOTIVATION 6
2.2 CONTRIBUTIONS OF THIS WORK 11
2.3 OVERVIEW 14
3. MODELS AND TOOLS 17
3.1 INSTRUCTION SET ARCHITECTURE MODELS 19
3.1.1 ARMV4T 19
3.1.2 SPARC V8 21
3.2 MEMORY MODELS 24
3.2.1 SRAM 25
3.2.2 DRAM 27
3.2.3 FLASH MEMORY 30
3.2.4 CACHES 31
3.3 TIMING MODELS 35
3.3.1 PROCESSOR TIMING 35
3.3.1.1 ARM7TDMI INSTRUCTION TIMING 36
3.3.1.2 LEON INSTRUCTION TIMING 38
3.3.2 MEMORY TIMING 40
3.3.2.1 SRAM TIMING MODEL 40
3.3.2.2 DRAM TIMING MODEL 42
VI
3.3.2.3 FLASH MEMORY TIMING MODEL 44
3.3.2.4 CACHE TIMING MODEL 45
3.4 ENERGY MODELS 46
3.4.1 SOURCES OF ENERGY DISSIPATION 47
3.4.2 PROCESSOR ENERGY 49
3.4.2.1 RELATED WORK 49
3.4.2.2 ARM7 ENERGY MODEL 54
3.4.2.3 LEON ENERGY MODEL 54
3.4.3 MEMORY ENERGY 62
3.4.3.1 RELATED WORK 63
3.4.3.2 SRAM ENERGY MODEL 66
3.4.3.3 DRAM ENERGY MODEL 69
3.4.3.4 FLASH MEMORY ENERGY MODEL 78
3.4.3.5 CACHE ENERGY MODEL 79
3.5 SIMULATION MODELS 80
3.5.1 PROCESSOR SIMULATION MODELS 81
3.5.1.1 RELATED WORK 81
3.5.1.2 ARM7 SIMULATION MODEL 84
3.5.1.3 LEON SIMULATION MODEL 85
3.5.2 MEMORY SIMULATION MODEL 87
3.5.2.1 RELATED WORK 88
3.5.2.2 TECHNICAL REQUIREMENTS 89
3.5.2.3 WORKFLOW 90
3.5.2.4 SIMULATION KERNEL 92
3.5.2.5 COMPONENTS 93
3.5.2.6 CONFIGURATION 97
3.6 THE ENCC COMPILER FRAMEWORK 98
3.6.1 WORKFLOW 99
3.6.2 ENPROFILER 103
3.6.3 MEMORY ARCHITECTURE AWARE COMPILATION 105
4. SCRATCHPAD MEMORY OPTIMIZATIONS 113
4.1 RELATED WORK 115
4.2 MULTI MEMORY OPTIMIZATION 121
4.2.1 MEMORY OBJECTS 123
4.2.2 PREREQUISITES 124
4.2.3 ENERGY FUNCTIONS 125
4.2.4 THE BASE MODEL 126
4.2.5 THE TOP-DOWN MODEL 128
CONTENTS
VII
4.2.6 THE BOTTOM-UP MODEL 136
4.2.7 THE ARM TCM MODEL 140
4.2.8 LEAKAGE-ENERGY AWARE MEMORY CONFIGURATION 142
4.2.9 RESULTS FOR MULTI MEMORY OPTIMIZATION 145
4.2.9.1 COMPARISON OF BASE, TOP-DOWN AND BOTTOM-UP 148
4.2.9.2 RESULTS FOR THE ARM TCM ARCHITECTURE 156
4.2.9.3 RESULTS FOR COMPILER GUIDED MEMORY CONFIGURATION 159
4.3 IMPACT OF SCRATCHPAD ALLOCATION TECHNIQUES ON WCET 162
4.3.1 RELATED WORK 165
4.3.2 TOOLS AND WORKFLOW 168
4.3.3 REQUIRED ANNOTATION INFORMATION 171
4.3.4 BENCHMARKS AND MEMORY HIERARCHY CONFIGURATION 177
4.3.5 WCET RESULTS FOR STATIC ALLOCATION 178
4.3.6 WCET RESULTS FOR DYNAMIC ALLOCATION 187
5. MAIN MEMORY OPTIMIZATIONS 197
5.1 RELATED WORK 198
5.2 MAIN MEMORY POWER MANAGEMENT 200
5.2.1 MOTIVATING EXAMPLE 203
5.2.2 PREREQUISITES 205
5.2.3 MEMORY OBJECTS AND ENERGY FUNCTIONS 205
5.2.4 BINARY DECISION VARIABLES 208
5.2.5 OBJECTIVE FUNCTION 210
5.2.6 CONSTRAINTS 211
5.2.7 RESULTS FOR MAIN MEMORY POWER MANAGEMENT 212
5.3 EXECUTE-IN-PLACE USING FLASH MEMORIES 218
5.3.1 ANALYSIS OF THE COPY FUNCTION 221
5.3.2 MAIN MEMORY PARTITIONING 222
5.3.3 PREREQUISITES 224
5.3.4 PRESELECTION OF MEMORY OBJECTS TO ENABLE DEEP POWER
DOWN 226
5.3.5 FORMALIZATION OF THE PRESELECTION ALGORITHM 230
5.3.6 FORMALIZATION OF THE XIP ALLOCATION PROBLEM 232
5.3.6.1 DECISION VARIABLES 233
5.3.6.2 CONSTRAINTS 234
5.3.6.3 OBJECTIVE FUNCTION 234
5.3.7 RESULTS FOR XIP 235
VLL
L
6. REGISTER FILE OPTIMIZATION 245
6.1 RELATED WORK 246
6.2 IMPLEMENTATION OF THE REGISTER FILE 247
6.3 REGISTER ALLOCATION AND LIFETIME ANALYSIS 248
6.4 WORKFLOW AND METHODOLOGY 250
6.5 BENCHMARK SUITE 252
6.5.1 RESULTS FOR THE RATIO OF SPILL CODE TO TOTAL CODE SIZE 253
6.5.2 RESULTS FOR THE NUMBER OF CYCLES 254
6.5.3 RESULTS FOR ENERGY CONSUMPTION 257
6.6 COMPILER GUIDED CHOICE OF REGISTER FILE SIZE 258
7. SUMMARY 261
8. FUTURE WORK 267
9. AUTHOR S CONTRIBUTIONS 271
9.1 CONTRIBUTIONS TO THE PH.D. THESIS 271
9.2 CONTRIBUTIONS TO THE LIST OF PUBLICATIONS 273
REFERENCES 277
|
| adam_txt |
FAST, EFFICIENT AND PREDICTABLE MEMORY ACCESSES
OPTIMIZATION ALGORITHMS FOR MEMORY
ARCHITECTURE AWARE COMPILATION
DISSERTATION
ZUR ERLANGUNG DES GRADES EINES
DOKTOR
S DE
R NATU
R W I SSENSCHAFTE
N
DER UNIVERSITAT DORTMUND
AM FACHBEREICH INFORMATIK
VON
LARS WEHMEYER
DORTMUND
2005
ULB DARMSTADT
ILLLLLLLLLLLLLLLLLL
L
16323551
CONTENTS
DEDICATION III
LIST OF FIGURES IX
LIST OF TABLES XVI
ACKNOWLEDGMENTS XVII
1. ABSTRACT 1
2. INTRODUCTION 3
2.1 MOTIVATION 6
2.2 CONTRIBUTIONS OF THIS WORK 11
2.3 OVERVIEW 14
3. MODELS AND TOOLS 17
3.1 INSTRUCTION SET ARCHITECTURE MODELS 19
3.1.1 ARMV4T 19
3.1.2 SPARC V8 21
3.2 MEMORY MODELS 24
3.2.1 SRAM 25
3.2.2 DRAM 27
3.2.3 FLASH MEMORY 30
3.2.4 CACHES 31
3.3 TIMING MODELS 35
3.3.1 PROCESSOR TIMING 35
3.3.1.1 ARM7TDMI INSTRUCTION TIMING 36
3.3.1.2 LEON INSTRUCTION TIMING 38
3.3.2 MEMORY TIMING 40
3.3.2.1 SRAM TIMING MODEL 40
3.3.2.2 DRAM TIMING MODEL 42
VI
3.3.2.3 FLASH MEMORY TIMING MODEL 44
3.3.2.4 CACHE TIMING MODEL 45
3.4 ENERGY MODELS 46
3.4.1 SOURCES OF ENERGY DISSIPATION 47
3.4.2 PROCESSOR ENERGY 49
3.4.2.1 RELATED WORK 49
3.4.2.2 ARM7 ENERGY MODEL 54
3.4.2.3 LEON ENERGY MODEL 54
3.4.3 MEMORY ENERGY 62
3.4.3.1 RELATED WORK 63
3.4.3.2 SRAM ENERGY MODEL 66
3.4.3.3 DRAM ENERGY MODEL 69
3.4.3.4 FLASH MEMORY ENERGY MODEL 78
3.4.3.5 CACHE ENERGY MODEL 79
3.5 SIMULATION MODELS 80
3.5.1 PROCESSOR SIMULATION MODELS 81
3.5.1.1 RELATED WORK 81
3.5.1.2 ARM7 SIMULATION MODEL 84
3.5.1.3 LEON SIMULATION MODEL 85
3.5.2 MEMORY SIMULATION MODEL 87
3.5.2.1 RELATED WORK 88
3.5.2.2 TECHNICAL REQUIREMENTS 89
3.5.2.3 WORKFLOW 90
3.5.2.4 SIMULATION KERNEL 92
3.5.2.5 COMPONENTS 93
3.5.2.6 CONFIGURATION 97
3.6 THE ENCC COMPILER FRAMEWORK 98
3.6.1 WORKFLOW 99
3.6.2 ENPROFILER 103
3.6.3 MEMORY ARCHITECTURE AWARE COMPILATION 105
4. SCRATCHPAD MEMORY OPTIMIZATIONS 113
4.1 RELATED WORK 115
4.2 MULTI MEMORY OPTIMIZATION 121
4.2.1 MEMORY OBJECTS 123
4.2.2 PREREQUISITES 124
4.2.3 ENERGY FUNCTIONS 125
4.2.4 THE BASE MODEL 126
4.2.5 THE TOP-DOWN MODEL 128
CONTENTS
VII
4.2.6 THE BOTTOM-UP MODEL 136
4.2.7 THE ARM TCM MODEL 140
4.2.8 LEAKAGE-ENERGY AWARE MEMORY CONFIGURATION 142
4.2.9 RESULTS FOR MULTI MEMORY OPTIMIZATION 145
4.2.9.1 COMPARISON OF BASE, TOP-DOWN AND BOTTOM-UP 148
4.2.9.2 RESULTS FOR THE ARM TCM ARCHITECTURE 156
4.2.9.3 RESULTS FOR COMPILER GUIDED MEMORY CONFIGURATION 159
4.3 IMPACT OF SCRATCHPAD ALLOCATION TECHNIQUES ON WCET 162
4.3.1 RELATED WORK 165
4.3.2 TOOLS AND WORKFLOW 168
4.3.3 REQUIRED ANNOTATION INFORMATION 171
4.3.4 BENCHMARKS AND MEMORY HIERARCHY CONFIGURATION 177
4.3.5 WCET RESULTS FOR STATIC ALLOCATION 178
4.3.6 WCET RESULTS FOR DYNAMIC ALLOCATION 187
5. MAIN MEMORY OPTIMIZATIONS 197
5.1 RELATED WORK 198
5.2 MAIN MEMORY POWER MANAGEMENT 200
5.2.1 MOTIVATING EXAMPLE 203
5.2.2 PREREQUISITES 205
5.2.3 MEMORY OBJECTS AND ENERGY FUNCTIONS 205
5.2.4 BINARY DECISION VARIABLES 208
5.2.5 OBJECTIVE FUNCTION 210
5.2.6 CONSTRAINTS 211
5.2.7 RESULTS FOR MAIN MEMORY POWER MANAGEMENT 212
5.3 EXECUTE-IN-PLACE USING FLASH MEMORIES 218
5.3.1 ANALYSIS OF THE COPY FUNCTION 221
5.3.2 MAIN MEMORY PARTITIONING 222
5.3.3 PREREQUISITES 224
5.3.4 PRESELECTION OF MEMORY OBJECTS TO ENABLE DEEP POWER
DOWN 226
5.3.5 FORMALIZATION OF THE PRESELECTION ALGORITHM 230
5.3.6 FORMALIZATION OF THE XIP ALLOCATION PROBLEM 232
5.3.6.1 DECISION VARIABLES 233
5.3.6.2 CONSTRAINTS 234
5.3.6.3 OBJECTIVE FUNCTION 234
5.3.7 RESULTS FOR XIP 235
VLL
L
6. REGISTER FILE OPTIMIZATION 245
6.1 RELATED WORK 246
6.2 IMPLEMENTATION OF THE REGISTER FILE 247
6.3 REGISTER ALLOCATION AND LIFETIME ANALYSIS 248
6.4 WORKFLOW AND METHODOLOGY 250
6.5 BENCHMARK SUITE 252
6.5.1 RESULTS FOR THE RATIO OF SPILL CODE TO TOTAL CODE SIZE 253
6.5.2 RESULTS FOR THE NUMBER OF CYCLES 254
6.5.3 RESULTS FOR ENERGY CONSUMPTION 257
6.6 COMPILER GUIDED CHOICE OF REGISTER FILE SIZE 258
7. SUMMARY 261
8. FUTURE WORK 267
9. AUTHOR'S CONTRIBUTIONS 271
9.1 CONTRIBUTIONS TO THE PH.D. THESIS 271
9.2 CONTRIBUTIONS TO THE LIST OF PUBLICATIONS 273
REFERENCES 277 |
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| spelling | Wehmeyer, Lars Verfasser aut Fast, efficient and predictable memory accesses optimization algorithms for memory architecture aware compilation von Lars Wehmeyer 2005 XVI, 288 S. graph. Darst. 30 cm txt rdacontent n rdamedia nc rdacarrier Dortmund, Univ., Diss., 2005 Speicherverwaltung (DE-588)4182146-4 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Speicherverwaltung (DE-588)4182146-4 s DE-604 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=014850078&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Wehmeyer, Lars Fast, efficient and predictable memory accesses optimization algorithms for memory architecture aware compilation Speicherverwaltung (DE-588)4182146-4 gnd |
| subject_GND | (DE-588)4182146-4 (DE-588)4113937-9 |
| title | Fast, efficient and predictable memory accesses optimization algorithms for memory architecture aware compilation |
| title_auth | Fast, efficient and predictable memory accesses optimization algorithms for memory architecture aware compilation |
| title_exact_search | Fast, efficient and predictable memory accesses optimization algorithms for memory architecture aware compilation |
| title_exact_search_txtP | Fast, efficient and predictable memory accesses optimization algorithms for memory architecture aware compilation |
| title_full | Fast, efficient and predictable memory accesses optimization algorithms for memory architecture aware compilation von Lars Wehmeyer |
| title_fullStr | Fast, efficient and predictable memory accesses optimization algorithms for memory architecture aware compilation von Lars Wehmeyer |
| title_full_unstemmed | Fast, efficient and predictable memory accesses optimization algorithms for memory architecture aware compilation von Lars Wehmeyer |
| title_short | Fast, efficient and predictable memory accesses |
| title_sort | fast efficient and predictable memory accesses optimization algorithms for memory architecture aware compilation |
| title_sub | optimization algorithms for memory architecture aware compilation |
| topic | Speicherverwaltung (DE-588)4182146-4 gnd |
| topic_facet | Speicherverwaltung Hochschulschrift |
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