Verfügbarkeit: The boundary-scan handbook

The boundary-scan handbook:

Gespeichert in:

Bibliographische Detailangaben
1. Verfasser:	Parker, Kenneth P. (VerfasserIn)
Format:	Buch
Sprache:	English
Veröffentlicht:	Boston, Mass. Kluwer 2003
Ausgabe:	3. ed.
Schlagworte:	Boundary scan testing Electronic digital computers > Circuits > Design and construction Printed circuits > Testing Printed circuits > Testing > Standards Boundary scan
Online-Zugang:	Inhaltsverzeichnis
Beschreibung:	XXV, 373 S. Ill.
ISBN:	1402074964

Internformat

MARC


LEADER	00000nam a2200000zc 4500
001	BV021504564
003	DE-604
005	20060406
007	t
008	060309s2003 xxua\|\|\| \|\|\|\| 00\|\|\| eng d
010			\|a 2003051404
020			\|a 1402074964 \|9 1-402-07496-4
035			\|a (OCoLC)52203121
035			\|a (DE-599)BVBBV021504564
040			\|a DE-604 \|b ger \|e aacr
041	0		\|a eng
044			\|a xxu \|c US
049			\|a DE-92
050		0	\|a TK7868.P7
082	0		\|a 621.3815/31/0218 \|2 21
084			\|a ZN 4030 \|0 (DE-625)157339: \|2 rvk
084			\|a ZN 4900 \|0 (DE-625)157417: \|2 rvk
100	1		\|a Parker, Kenneth P. \|e Verfasser \|4 aut
245	1	0	\|a The boundary-scan handbook \|c by Kenneth P. Parker
250			\|a 3. ed.
264		1	\|a Boston, Mass. \|b Kluwer \|c 2003
300			\|a XXV, 373 S. \|b Ill.
336			\|b txt \|2 rdacontent
337			\|b n \|2 rdamedia
338			\|b nc \|2 rdacarrier
650		4	\|a Boundary scan testing
650		4	\|a Electronic digital computers \|x Circuits \|x Design and construction
650		4	\|a Printed circuits \|x Testing
650		4	\|a Printed circuits \|x Testing \|x Standards
650	0	7	\|a Boundary scan \|0 (DE-588)4340209-4 \|2 gnd \|9 rswk-swf
689	0	0	\|a Boundary scan \|0 (DE-588)4340209-4 \|D s
689	0		\|5 DE-604
856	4	2	\|m GBV Datenaustausch \|q application/pdf \|u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=014721250&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA \|3 Inhaltsverzeichnis
999			\|a oai:aleph.bib-bvb.de:BVB01-014721250

Datensatz im Suchindex

_version_	1804135237379162112
adam_text	THE BOUNDARY - SCAN HANDBOOK BY KENNETH P. PARKER AGILENT TECHNOLOGIES * KLUWER ACADEMIC PUBLISHERS BOSTON / DORDRECHT / LONDON TABLE OF CONTENTS LIST OF FIGURES XIII LIST OF TABLES XVI LIST OF DESIGN-FOR-TEST RULES XVII PREFACE TO THE FIRST EDITION XXI PREFACE TO THE SECOND EDITION XXIII PREFACE TO THE THIRD EDITION XXIV ACKNOWLEDGEMENT XXVII 1 BOUNDARY-SCAN BASICS AND VOCABULARY 1 1.1 DIGITAL TEST BEFORE BOUNDARY-SCAN 2 1.1.1 EDGE-CONNECTOR FUNCTIONAL TESTING 2 1.1.2 IN-CIRCUIT TESTING 4 1.2 THE PHILOSOPHY OF 1149.1 7 1.3 BASIC ARCHITECTURE 8 1.3.1 THE TAP CONTROLLER 10 1.3.2 THE INSTRUCTION REGISTER 16 1.3.3 DATA REGISTERS .20 1.3.4 THE BOUNDARY REGISTER 21 1.3.5 OPTIMIZING A BOUNDARY REGISTER CELL DESIGN 27 1.3.6 ARCHITECTURE SUMMARY 29 1.3.7 FIELD-PROGRAMMABLE 1* DEVICES 30 1.3.8 BOUNDARY-SCAN CHAINS 31 1.4 NON-INVASIVE OPERATIONAL MODES 33 1.4.1 BYPASS 33 1.4.2 IDCODE 33 1.4.3 USERCODE 35 1.4.4 SAMPLE 35 1.4.5 PRELOAD 35 1.5 PIN-PERMISSION OPERATIONAL MODES 36 1.5.1 EXTEST 36 1.5.2 INTEST 37 1.5.3 RUNBIST 38 1.5.4 HIGHZ 39 1.5.5 CLAMP 39 1.5.6 EXCEPTIONS DUE TO CLOCKING 40 1.6 EXTENSIBILITY 40 1.7 SUBORDINATION OF IEEE 1149.1 41 1.8 COSTS AND BENEFITS 42 1.8.1 COSTS 42 1.8.2 BENEFITS 44 1.8.3 TRENDS 46 1.9 OTHER TESTABILITY STANDARDS 47 2 BOUNDARY-SCAN DESCRIPTION LANGUAGE (BSDL) 49 2.1 THE SCOPE OF BSDL 52 2.1.1 TESTING 52 2.1.2 COMPLIANCE ASSURANCE 53 2.1.3 SYNTHESIS 55 2.2 STRUCTURE OF BSDL 57 2.3 ENTITY DESCRIPTIONS 61 2.3.1 GENERIC PARAMETER 62 2.3.2 LOGICAL PORT DESCRIPTION 62 2.3.3 STANDARD USE STATEMENT 63 2.3.4 USE STATEMENTS 64 2.3.5 COMPONENT CONFORMANCE STATEMENT 64 2.3.6 DEVICE PACKAGE PIN MAPPINGS 65 2.3.7 GROUPED PORT IDENTIFICATION 66 2.3.8 TAP PORT IDENTIFICATION 67 2.3.9 COMPLIANCE ENABLE DESCRIPTION 68 2.3.10 INSTRUCTION REGISTER DESCRIPTION 68 2.3.11 OPTIONAL REGISTER DESCRIPTION 70 2.3.12 REGISTER ACCESS DESCRIPTION 71 2.3.13 BOUNDARY-SCAN REGISTER DESCRIPTION 72 2.3.14 RUNBIST EXECUTION DESCRIPTION 75 2.3.15 INTEST EXECUTION DESCRIPTION 76 2.3.16 USER EXTENSIONS TO BSDL 77 2.3.17 DESIGN WARNINGS 77 2.4 SOME ADVANCED BSDL TOPICS 78 2.4.1 MERGED CELLS 78 2.4.2 ASYMMETRICAL DRIVERS 81 2.5 BSDL DESCRIPTION OF 74BCT8374 81 2.6 PACKAGES AND PACKAGE BODIES 84 2.6.1 STD_1149_1_2001 85 2.6.2 CELL DESCRIPTION CONSTANTS 89 2.6.3 BASIC CELL DEFINITIONS BC_0 TO BC_7 91 2.6.4 CELLS BC_8 TO BC_10 INTRODUCED IN 2001 99 2.6.5 USER-DEFINED BOUNDARY CELLS 101 2.6.6 DEFINITION OF BSDL EXTENSIONS 103 2.7 WRITING BSDL ,. 104 2.8 SUMMARY 106 3 BOUNDARY-SCAN TESTING 107 3.1 BASIC BOUNDARY-SCAN TESTING 108 3.1.1 THE 1149.1 SCANNING SEQUENCE 108 3.1.2 BASIC TEST ALGORITHM 114 3.1.3 THE PERSONAL TESTER VERSUS ATE 115 3.1.4 IN-CIRCUIT BOUNDARY-SCAN 117 3.1.5 1* TEST 119 VLLL 3.1.6 1* BIST 120 3.2 TESTING WITH BOUNDARY-SCAN CHAINS 121 3.2.1 1149.1 CHAIN INTEGRITY 122 3.2.2 INTERCONNECT TEST 125 3.2.3 CONNECTION TESTS 138 3.2.4 INTERACTION TESTS 140 3.2.5 BIST AND CUSTOM TESTS 143 3.3 PORTING BOUNDARY-SCAN TESTS 144 3.4 BOUNDARY-SCAN TEST COVERAGE 146 3.5 SUMMARY 147 4 ADVANCED BOUNDARY-SCAN TOPICS 149 4.1 DC PARAMETRIC 1* TESTS 150 4.2 SAMPLE MODE TESTS 151 4.3 CONCURRENT MONITORING 154 4.4 NON-SCAN 1* TESTING 155 4.5 NON-DIGITAL DEVICE TESTING 158 4.6 MIXED DIGITAL/ANALOG TESTING 159 4.7 MULTI-CHIP MODULE TESTING 161 4.8 FIRMWARE DEVELOPMENT SUPPORT 163 4.9 IN-SYSTEM CONFIGURATION 164 4.10 FLASH PROGRAMMING 166 4.11 HARDWARE FAULT INSERTION 167 4.12 POWER PIN TESTING 149 5 DESIGN FOR BOUNDARY-SCAN TEST 171 5.1 INTEGRATED CIRCUIT LEVEL DFT 173 5.1.1 TAP PIN PLACEMENT 173 5.1.2 POWER AND GROUND DISTRIBUTION 174 5.1.3 INSTRUCTION CAPTURE PATTERN 178 5.1.4 DAMAGE RESISTANT DRIVERS 179 5.1.5 OUTPUT PINS 180 5.1.6 BIDIRECTIONAL PINS 182 5.1.7 POST-LOBOTOMY BEHAVIOR 182 5.1.8 IDCODES 183 5.1.9 USER-DEFINED INSTRUCTIONS 184 5.1.10 CREATION AND VERIFICATION OF BSDL 184 5.2 BOARD-LEVEL DFT 186 5.2.1 CHAIN CONFIGURATIONS 186 5.2.2 TCK/TMS DISTRIBUTION 189 5.2.3 MIXED LOGIC FAMILIES 190 5.2.4 BOARD LEVEL CONFLICTS 192 5.2.5 CONTROL OF CRITICAL NODES 193 5.2.6 POWER DISTRIBUTION 194 5.2.7 BOUNDARY-SCAN MASTERS 195 5.2.8 POST-LOBOTOMY BOARD BEHAVIOR 197 5.3 SYSTEM-LEVEL DFT 197 IX 5.3.1 THE MULTIDROP PROBLEM 198 5.3.2 COORDINATION WITH OTHER STANDARDS 199 5.4 SUMMARY 200 6 ANALOG MEASUREMENT BASICS 201 6.1 ANALOG IN-CIRCUIT TESTING 201 6.1.1 ANALOG FAILURES 202 6.1.2 MEASURING AN IMPEDANCE 204 6.1.3 ERRORS AND CORRECTIONS 208 6.1.4 MEASUREMENT HARDWARE 210 6.2 LIMITED ACCESS TESTING 215 6.2.1 NODE VOLTAGE ANALYSIS 216 6.2.2 TESTING WITH NODE VOLTAGES 217 6.2.3 LIMITED ACCESS NODE VOLTAGE TESTING 219 6.3 THE MIXED-SIGNAL TEST ENVIRONMENT 221 6.4 SUMMARY 224 7 IEEE 1149.4: ANALOG BOUNDARY-SCAN 225 7.1 1149.4 VOCABULARY AND BASICS 226 7.1.1 THE TARGET FAULT SPECTRUM 227 7.1.2 EXTENDED INTERCONNECT 227 7.1.3 DIGITAL PINS 229 7.1.4 ANALOG PINS 230 7.2 GENERAL ARCHITECTURE OF AN 1149.4 1* 231 7.2.1 SILICON SWITCHES 233 7.2.2 THE ANALOG TEST ACCESS PORT (ATAP) 234 7.2.3 THE TEST BUS INTERFACE CIRCUIT (TBIC) 235 7.2.4 THE ANALOG BOUNDARY MODULE (ABM) 240 7.2.5 THE DIGITAL BOUNDARY MODULE (DBM) 246 7.3 THE 1149.4 INSTRUCTION SET 247 7.3.1 THE EXTEST INSTRUCTION 248 7.3.2 THE CLAMP INSTRUCTION 251 7.3.3 THE HIGHZ INSTRUCTION 251 7.3.4 THE PROBE INSTRUCTION 251 7.3.5 THE RUNBIST INSTRUCTION 252 7.3.6 THE INTEST INSTRUCTION 252 7.4 OTHER PROVISIONS OF 1149.4 254 7.4.1 DIFFERENTIAL ATAP PORT 254 7.4.2 DIFFERENTIAL I/O 255 7.4.3 PARTITIONED INTERNAL TEST BUSES 257 7.4.4 SPECIFICATIONS AND LIMITS 260 7.5 DESIGN FOR 1149.4 TESTABILITY 261 7.5.1 INTEGRATED CIRCUIT LEVEL 261 7.5.2 BOARD LEVEL 263 7.5.3 SYSTEM LEVEL 264 7.6 SUMMARY 265 X 8 IEEE 1149.6: TESTING ADVANCED I/O 267 8.1 THE ADVANCED I/O PROBLEM 268 8.1.1 TRADITIONAL INTER-IC COMMUNICATION 268 8.1.2 ADVANCED INTER-IC COMMUNICATION 270 8.1.3 AC COUPLED SIGNAL PATHS 275 8.1.4 TESTING ADVANCED I/O 277 8.2 1149.6 VOCABULARY AND BASICS 279 8.2.1 ADVANCED I/O 279 8.2.2 SIGNAL PIN CATEGORIES 279 8.2.3 OPERATIONAL MODES 280 8.3 TEST FACILITIES FOR AC PINS 281 8.3.1 PROVISIONS FOR ALL SIGNAL PINS 281 8.3.2 PROVISIONS FOR AC PIN DRIVERS 281 8.3.3 AC/DC SELECTION CELLS 284 8.3.4 PROVISIONS FOR AC PIN RECEIVERS 286 8.4 THE DEFECT MODEL FOR 1149.6 287 8.5 THE 1149.6 TEST RECEIVER 290 8.5.1 TEST RECEIVER DEFINITIONS 290 8.5.2 TRANSITIONS 291 8.5.3 TEST RECEIVER DC RESPONSE 293 8.5.4 TEST RECEIVER AC RESPONSE 296 8.5.5 GUARANTEED AC-COUPLING 299 8.5.6 AN INTEGRATED AC/DC TEST RECEIVER 299 8.5.7 INITIALIZING AND CAPTURING HYSTERETIC MEMORY 300 8.6 BSDL EXTENSIONS FOR 1149.6 302 8.6.1 BOUNDARY REGISTERS CELLS FOR 1149.6 303 8.6.2 STD_1149_6_2003 308 8.6.3 EXAMPLE 1149.6 DEVICE AND BSDL 310 8.7 DESIGN FOR 1149.6 TESTABILITY 316 8.7.1 INTEGRATED CIRCUIT LEVEL DFT 316 8.7.2 BOARD-LEVEL DFT 317 8.8 SUMMARY 318 9 IEEE 1532: IN-SYSTEM CONFIGURATION 319 9.1 IEEE 1532 VOCABULARY AND BASICS 321 9.1.1 FIXED SYSTEM PINS 321 9.1.2 ISC SYSTEM PINS 322 9.1.3 SYSTEM MODAL STATES 322 9.1.4 SYSTEM I/O BEHAVIOR 328 9.1.5 ISC PIN I/O CELL DESIGN 329 9.2 PROGRAMMING FEATURES OF IEEE 1532 333 9.2.1 CORE 1532 PROGRAMMING INSTRUCTIONS 334 9.2.2 PROGRAMMING A SINGLE, SIMPLE 1532 DEVICE 336 9.2.3 CONCURRENT PROGRAMMING OF MULTIPLE DEVICES 339 9.3 DESIGN FOR IEEE 1532 PROGRAMMABILITY 339 9.4 EPILOG: WHAT NEXT FOR 1149.1,1149.4,1149.6 AND 1532? 341 XI A. BSDL SYNTAX SPECIFICATIONS 345 A.L CONVENTIONS 345 A.2 LEXICAL ELEMENTS OF BSDL 346 A.3 NOTES ON SYNTAX DEFINITION 349 A.4 BSDL SYNTAX 351 A.5 USER PACKAGE SYNTAX 355 A.6 1149.6 EXTENTION ATTRIBUTE SYNTAX 355 BIBLIOGRAPHY 357 INDEX 365 XII
adam_txt	THE BOUNDARY - SCAN HANDBOOK BY KENNETH P. PARKER AGILENT TECHNOLOGIES * KLUWER ACADEMIC PUBLISHERS BOSTON / DORDRECHT / LONDON TABLE OF CONTENTS LIST OF FIGURES XIII LIST OF TABLES XVI LIST OF DESIGN-FOR-TEST RULES XVII PREFACE TO THE FIRST EDITION XXI PREFACE TO THE SECOND EDITION XXIII PREFACE TO THE THIRD EDITION XXIV ACKNOWLEDGEMENT XXVII 1 BOUNDARY-SCAN BASICS AND VOCABULARY 1 1.1 DIGITAL TEST BEFORE BOUNDARY-SCAN 2 1.1.1 EDGE-CONNECTOR FUNCTIONAL TESTING 2 1.1.2 IN-CIRCUIT TESTING 4 1.2 THE PHILOSOPHY OF 1149.1 7 1.3 BASIC ARCHITECTURE 8 1.3.1 THE TAP CONTROLLER 10 1.3.2 THE INSTRUCTION REGISTER 16 1.3.3 DATA REGISTERS .20 1.3.4 THE BOUNDARY REGISTER 21 1.3.5 OPTIMIZING A BOUNDARY REGISTER CELL DESIGN 27 1.3.6 ARCHITECTURE SUMMARY 29 1.3.7 FIELD-PROGRAMMABLE 1* DEVICES 30 1.3.8 BOUNDARY-SCAN CHAINS 31 1.4 NON-INVASIVE OPERATIONAL MODES 33 1.4.1 BYPASS 33 1.4.2 IDCODE 33 1.4.3 USERCODE 35 1.4.4 SAMPLE 35 1.4.5 PRELOAD 35 1.5 PIN-PERMISSION OPERATIONAL MODES 36 1.5.1 EXTEST 36 1.5.2 INTEST 37 1.5.3 RUNBIST 38 1.5.4 HIGHZ 39 1.5.5 CLAMP 39 1.5.6 EXCEPTIONS DUE TO CLOCKING 40 1.6 EXTENSIBILITY 40 1.7 SUBORDINATION OF IEEE 1149.1 41 1.8 COSTS AND BENEFITS 42 1.8.1 COSTS 42 1.8.2 BENEFITS 44 1.8.3 TRENDS 46 1.9 OTHER TESTABILITY STANDARDS 47 2 BOUNDARY-SCAN DESCRIPTION LANGUAGE (BSDL) 49 2.1 THE SCOPE OF BSDL 52 2.1.1 TESTING 52 2.1.2 COMPLIANCE ASSURANCE 53 2.1.3 SYNTHESIS 55 2.2 STRUCTURE OF BSDL 57 2.3 ENTITY DESCRIPTIONS 61 2.3.1 GENERIC PARAMETER 62 2.3.2 LOGICAL PORT DESCRIPTION 62 2.3.3 STANDARD USE STATEMENT 63 2.3.4 USE STATEMENTS 64 2.3.5 COMPONENT CONFORMANCE STATEMENT 64 2.3.6 DEVICE PACKAGE PIN MAPPINGS 65 2.3.7 GROUPED PORT IDENTIFICATION 66 2.3.8 TAP PORT IDENTIFICATION 67 2.3.9 COMPLIANCE ENABLE DESCRIPTION 68 2.3.10 INSTRUCTION REGISTER DESCRIPTION 68 2.3.11 OPTIONAL REGISTER DESCRIPTION 70 2.3.12 REGISTER ACCESS DESCRIPTION 71 2.3.13 BOUNDARY-SCAN REGISTER DESCRIPTION 72 2.3.14 RUNBIST EXECUTION DESCRIPTION 75 2.3.15 INTEST EXECUTION DESCRIPTION 76 2.3.16 USER EXTENSIONS TO BSDL 77 2.3.17 DESIGN WARNINGS 77 2.4 SOME ADVANCED BSDL TOPICS 78 2.4.1 MERGED CELLS 78 2.4.2 ASYMMETRICAL DRIVERS 81 2.5 BSDL DESCRIPTION OF 74BCT8374 81 2.6 PACKAGES AND PACKAGE BODIES 84 2.6.1 STD_1149_1_2001 85 2.6.2 CELL DESCRIPTION CONSTANTS 89 2.6.3 BASIC CELL DEFINITIONS BC_0 TO BC_7 91 2.6.4 CELLS BC_8 TO BC_10 INTRODUCED IN 2001 99 2.6.5 USER-DEFINED BOUNDARY CELLS 101 2.6.6 DEFINITION OF BSDL EXTENSIONS 103 2.7 WRITING BSDL ,. 104 2.8 SUMMARY 106 3 BOUNDARY-SCAN TESTING 107 3.1 BASIC BOUNDARY-SCAN TESTING 108 3.1.1 THE 1149.1 SCANNING SEQUENCE 108 3.1.2 BASIC TEST ALGORITHM 114 3.1.3 THE "PERSONAL TESTER" VERSUS ATE 115 3.1.4 IN-CIRCUIT BOUNDARY-SCAN 117 3.1.5 1* TEST 119 VLLL 3.1.6 1* BIST 120 3.2 TESTING WITH BOUNDARY-SCAN CHAINS 121 3.2.1 1149.1 CHAIN INTEGRITY 122 3.2.2 INTERCONNECT TEST 125 3.2.3 CONNECTION TESTS 138 3.2.4 INTERACTION TESTS 140 3.2.5 BIST AND CUSTOM TESTS 143 3.3 PORTING BOUNDARY-SCAN TESTS 144 3.4 BOUNDARY-SCAN TEST COVERAGE 146 3.5 SUMMARY 147 4 ADVANCED BOUNDARY-SCAN TOPICS 149 4.1 DC PARAMETRIC 1* TESTS 150 4.2 SAMPLE MODE TESTS 151 4.3 CONCURRENT MONITORING 154 4.4 NON-SCAN 1* TESTING 155 4.5 NON-DIGITAL DEVICE TESTING 158 4.6 MIXED DIGITAL/ANALOG TESTING 159 4.7 MULTI-CHIP MODULE TESTING 161 4.8 FIRMWARE DEVELOPMENT SUPPORT 163 4.9 IN-SYSTEM CONFIGURATION 164 4.10 FLASH PROGRAMMING 166 4.11 HARDWARE FAULT INSERTION 167 4.12 POWER PIN TESTING 149 5 DESIGN FOR BOUNDARY-SCAN TEST 171 5.1 INTEGRATED CIRCUIT LEVEL DFT 173 5.1.1 TAP PIN PLACEMENT 173 5.1.2 POWER AND GROUND DISTRIBUTION 174 5.1.3 INSTRUCTION CAPTURE PATTERN 178 5.1.4 DAMAGE RESISTANT DRIVERS 179 5.1.5 OUTPUT PINS 180 5.1.6 BIDIRECTIONAL PINS 182 5.1.7 POST-LOBOTOMY BEHAVIOR 182 5.1.8 IDCODES 183 5.1.9 USER-DEFINED INSTRUCTIONS 184 5.1.10 CREATION AND VERIFICATION OF BSDL 184 5.2 BOARD-LEVEL DFT 186 5.2.1 CHAIN CONFIGURATIONS 186 5.2.2 TCK/TMS DISTRIBUTION 189 5.2.3 MIXED LOGIC FAMILIES 190 5.2.4 BOARD LEVEL CONFLICTS 192 5.2.5 CONTROL OF CRITICAL NODES 193 5.2.6 POWER DISTRIBUTION 194 5.2.7 BOUNDARY-SCAN MASTERS 195 5.2.8 POST-LOBOTOMY BOARD BEHAVIOR 197 5.3 SYSTEM-LEVEL DFT 197 IX 5.3.1 THE MULTIDROP PROBLEM 198 5.3.2 COORDINATION WITH OTHER STANDARDS 199 5.4 SUMMARY 200 6 ANALOG MEASUREMENT BASICS 201 6.1 ANALOG IN-CIRCUIT TESTING 201 6.1.1 ANALOG FAILURES 202 6.1.2 MEASURING AN IMPEDANCE 204 6.1.3 ERRORS AND CORRECTIONS 208 6.1.4 MEASUREMENT HARDWARE 210 6.2 LIMITED ACCESS TESTING 215 6.2.1 NODE VOLTAGE ANALYSIS 216 6.2.2 TESTING WITH NODE VOLTAGES 217 6.2.3 LIMITED ACCESS NODE VOLTAGE TESTING 219 6.3 THE MIXED-SIGNAL TEST ENVIRONMENT 221 6.4 SUMMARY 224 7 IEEE 1149.4: ANALOG BOUNDARY-SCAN 225 7.1 1149.4 VOCABULARY AND BASICS 226 7.1.1 THE TARGET FAULT SPECTRUM 227 7.1.2 EXTENDED INTERCONNECT 227 7.1.3 DIGITAL PINS 229 7.1.4 ANALOG PINS 230 7.2 GENERAL ARCHITECTURE OF AN 1149.4 1* 231 7.2.1 SILICON "SWITCHES" 233 7.2.2 THE ANALOG TEST ACCESS PORT (ATAP) 234 7.2.3 THE TEST BUS INTERFACE CIRCUIT (TBIC) 235 7.2.4 THE ANALOG BOUNDARY MODULE (ABM) 240 7.2.5 THE DIGITAL BOUNDARY MODULE (DBM) 246 7.3 THE 1149.4 INSTRUCTION SET 247 7.3.1 THE EXTEST INSTRUCTION 248 7.3.2 THE CLAMP INSTRUCTION 251 7.3.3 THE HIGHZ INSTRUCTION 251 7.3.4 THE PROBE INSTRUCTION 251 7.3.5 THE RUNBIST INSTRUCTION 252 7.3.6 THE INTEST INSTRUCTION 252 7.4 OTHER PROVISIONS OF 1149.4 254 7.4.1 DIFFERENTIAL ATAP PORT 254 7.4.2 DIFFERENTIAL I/O 255 7.4.3 PARTITIONED INTERNAL TEST BUSES 257 7.4.4 SPECIFICATIONS AND LIMITS 260 7.5 DESIGN FOR 1149.4 TESTABILITY 261 7.5.1 INTEGRATED CIRCUIT LEVEL 261 7.5.2 BOARD LEVEL 263 7.5.3 SYSTEM LEVEL 264 7.6 SUMMARY 265 X 8 IEEE 1149.6: TESTING ADVANCED I/O 267 8.1 THE ADVANCED I/O PROBLEM 268 8.1.1 TRADITIONAL INTER-IC COMMUNICATION 268 8.1.2 ADVANCED INTER-IC COMMUNICATION 270 8.1.3 AC COUPLED SIGNAL PATHS 275 8.1.4 TESTING ADVANCED I/O 277 8.2 1149.6 VOCABULARY AND BASICS 279 8.2.1 ADVANCED I/O 279 8.2.2 SIGNAL PIN CATEGORIES 279 8.2.3 OPERATIONAL MODES 280 8.3 TEST FACILITIES FOR AC PINS 281 8.3.1 PROVISIONS FOR ALL SIGNAL PINS 281 8.3.2 PROVISIONS FOR AC PIN DRIVERS 281 8.3.3 AC/DC SELECTION CELLS 284 8.3.4 PROVISIONS FOR AC PIN RECEIVERS 286 8.4 THE DEFECT MODEL FOR 1149.6 287 8.5 THE 1149.6 TEST RECEIVER 290 8.5.1 TEST RECEIVER DEFINITIONS 290 8.5.2 TRANSITIONS 291 8.5.3 TEST RECEIVER DC RESPONSE 293 8.5.4 TEST RECEIVER AC RESPONSE 296 8.5.5 GUARANTEED AC-COUPLING 299 8.5.6 AN INTEGRATED AC/DC TEST RECEIVER 299 8.5.7 INITIALIZING AND CAPTURING HYSTERETIC MEMORY 300 8.6 BSDL EXTENSIONS FOR 1149.6 302 8.6.1 BOUNDARY REGISTERS CELLS FOR 1149.6 303 8.6.2 STD_1149_6_2003 308 8.6.3 EXAMPLE 1149.6 DEVICE AND BSDL 310 8.7 DESIGN FOR 1149.6 TESTABILITY 316 8.7.1 INTEGRATED CIRCUIT LEVEL DFT 316 8.7.2 BOARD-LEVEL DFT 317 8.8 SUMMARY 318 9 IEEE 1532: IN-SYSTEM CONFIGURATION 319 9.1 IEEE 1532 VOCABULARY AND BASICS 321 9.1.1 FIXED SYSTEM PINS 321 9.1.2 ISC SYSTEM PINS 322 9.1.3 SYSTEM MODAL STATES 322 9.1.4 SYSTEM I/O BEHAVIOR 328 9.1.5 ISC PIN I/O CELL DESIGN 329 9.2 PROGRAMMING FEATURES OF IEEE 1532 333 9.2.1 CORE 1532 PROGRAMMING INSTRUCTIONS 334 9.2.2 PROGRAMMING A SINGLE, SIMPLE 1532 DEVICE 336 9.2.3 CONCURRENT PROGRAMMING OF MULTIPLE DEVICES 339 9.3 DESIGN FOR IEEE 1532 PROGRAMMABILITY 339 9.4 EPILOG: WHAT NEXT FOR 1149.1,1149.4,1149.6 AND 1532? 341 XI A. BSDL SYNTAX SPECIFICATIONS 345 A.L CONVENTIONS 345 A.2 LEXICAL ELEMENTS OF BSDL 346 A.3 NOTES ON SYNTAX DEFINITION 349 A.4 BSDL SYNTAX 351 A.5 USER PACKAGE SYNTAX 355 A.6 1149.6 EXTENTION ATTRIBUTE SYNTAX 355 BIBLIOGRAPHY 357 INDEX 365 XII
any_adam_object	1
any_adam_object_boolean	1
author	Parker, Kenneth P.
author_facet	Parker, Kenneth P.
author_role	aut
author_sort	Parker, Kenneth P.
author_variant	k p p kp kpp
building	Verbundindex
bvnumber	BV021504564
callnumber-first	T - Technology
callnumber-label	TK7868
callnumber-raw	TK7868.P7
callnumber-search	TK7868.P7
callnumber-sort	TK 47868 P7
callnumber-subject	TK - Electrical and Nuclear Engineering
classification_rvk	ZN 4030 ZN 4900
ctrlnum	(OCoLC)52203121 (DE-599)BVBBV021504564
dewey-full	621.3815/31/0218
dewey-hundreds	600 - Technology (Applied sciences)
dewey-ones	621 - Applied physics
dewey-raw	621.3815/31/0218
dewey-search	621.3815/31/0218
dewey-sort	3621.3815 231 3218
dewey-tens	620 - Engineering and allied operations
discipline	Elektrotechnik / Elektronik / Nachrichtentechnik
discipline_str_mv	Elektrotechnik / Elektronik / Nachrichtentechnik
edition	3. ed.
format	Book
fullrecord	<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01522nam a2200433zc 4500</leader><controlfield tag="001">BV021504564</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20060406 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">060309s2003 xxua\|\|\| \|\|\|\| 00\|\|\| eng d</controlfield><datafield tag="010" ind1=" " ind2=" "><subfield code="a">2003051404</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">1402074964</subfield><subfield code="9">1-402-07496-4</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)52203121</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV021504564</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="044" ind1=" " ind2=" "><subfield code="a">xxu</subfield><subfield code="c">US</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-92</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK7868.P7</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3815/31/0218</subfield><subfield code="2">21</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4030</subfield><subfield code="0">(DE-625)157339:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4900</subfield><subfield code="0">(DE-625)157417:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Parker, Kenneth P.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">The boundary-scan handbook</subfield><subfield code="c">by Kenneth P. Parker</subfield></datafield><datafield tag="250" ind1=" " ind2=" "><subfield code="a">3. ed.</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boston, Mass.</subfield><subfield code="b">Kluwer</subfield><subfield code="c">2003</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XXV, 373 S.</subfield><subfield code="b">Ill.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Boundary scan testing</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronic digital computers</subfield><subfield code="x">Circuits</subfield><subfield code="x">Design and construction</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Printed circuits</subfield><subfield code="x">Testing</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Printed circuits</subfield><subfield code="x">Testing</subfield><subfield code="x">Standards</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Boundary scan</subfield><subfield code="0">(DE-588)4340209-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Boundary scan</subfield><subfield code="0">(DE-588)4340209-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">GBV Datenaustausch</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=014721250&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-014721250</subfield></datafield></record></collection>
id	DE-604.BV021504564
illustrated	Illustrated
index_date	2024-07-02T14:16:40Z
indexdate	2024-07-09T20:37:19Z
institution	BVB
isbn	1402074964
language	English
lccn	2003051404
oai_aleph_id	oai:aleph.bib-bvb.de:BVB01-014721250
oclc_num	52203121
open_access_boolean
owner	DE-92
owner_facet	DE-92
physical	XXV, 373 S. Ill.
publishDate	2003
publishDateSearch	2003
publishDateSort	2003
publisher	Kluwer
record_format	marc
spelling	Parker, Kenneth P. Verfasser aut The boundary-scan handbook by Kenneth P. Parker 3. ed. Boston, Mass. Kluwer 2003 XXV, 373 S. Ill. txt rdacontent n rdamedia nc rdacarrier Boundary scan testing Electronic digital computers Circuits Design and construction Printed circuits Testing Printed circuits Testing Standards Boundary scan (DE-588)4340209-4 gnd rswk-swf Boundary scan (DE-588)4340209-4 s DE-604 GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=014721250&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis
spellingShingle	Parker, Kenneth P. The boundary-scan handbook Boundary scan testing Electronic digital computers Circuits Design and construction Printed circuits Testing Printed circuits Testing Standards Boundary scan (DE-588)4340209-4 gnd
subject_GND	(DE-588)4340209-4
title	The boundary-scan handbook
title_auth	The boundary-scan handbook
title_exact_search	The boundary-scan handbook
title_exact_search_txtP	The boundary-scan handbook
title_full	The boundary-scan handbook by Kenneth P. Parker
title_fullStr	The boundary-scan handbook by Kenneth P. Parker
title_full_unstemmed	The boundary-scan handbook by Kenneth P. Parker
title_short	The boundary-scan handbook
title_sort	the boundary scan handbook
topic	Boundary scan testing Electronic digital computers Circuits Design and construction Printed circuits Testing Printed circuits Testing Standards Boundary scan (DE-588)4340209-4 gnd
topic_facet	Boundary scan testing Electronic digital computers Circuits Design and construction Printed circuits Testing Printed circuits Testing Standards Boundary scan
url	http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=014721250&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
work_keys_str_mv	AT parkerkennethp theboundaryscanhandbook

Verfügbarkeit

Es ist kein Print-Exemplar vorhanden.

Fernleihe Bestellen Achtung: Nicht im THWS-Bestand! Inhaltsverzeichnis

MARC

Datensatz im Suchindex

Es ist kein Print-Exemplar vorhanden.

Ähnliche Einträge