ESD design and analysis handbook:
Saved in:
| Format: | Book |
|---|---|
| Language: | English |
| Published: |
Boston, Mass.
Kluwer
2003
|
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Item Description: | Includes bibliographical references and index |
| Physical Description: | VIII, 207 S. Ill. |
| ISBN: | 140207350X |
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MARC
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| 245 | 1 | 0 | |a ESD design and analysis handbook |c by James E. Vinson ... |
| 264 | 1 | |a Boston, Mass. |b Kluwer |c 2003 | |
| 300 | |a VIII, 207 S. |b Ill. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 500 | |a Includes bibliographical references and index | ||
| 650 | 4 | |a Electrostatics | |
| 650 | 4 | |a Integrated circuits |x Protection | |
| 650 | 4 | |a Semiconductors |x Protection | |
| 650 | 4 | |a Static eliminators | |
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| 700 | 1 | |a Vinson, James E. |e Sonstige |4 oth | |
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Record in the Search Index
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| adam_text | ESD DESIGN AND ANALYSIS HANDBOOK BY JAMES E. VINSON, PH.D. JOSEPH C.
BERNIER GREGG D. CROFT INTERSIL CORPORATION JUIN J. LIOU, PH.D.
UNIVERSITY OF CENTRAL FLORIDA KLUWER ACADEMIC PUBLISHERS BOSTON /
DORDRECHT / LONDON TABLE OF CONTENTS FOREWORD IX CHAPTER 1 PHYSICS AND
MODELS OF AN ESD EVENT 1 1.1 ESD IN OUR WORLD 1 1.1.1 HOME LIFE 1 1.1.2
WORK ENVIRONMENT 3 1.1.3 THREATS FROM ESD 4 1.1.4 NATURE 5 1.2 ESD IN
SEMICONDUCTORS 5 1.2.1 WAFER FABRICATION 6 1.2.2 ASSEMBLY, TEST, AND
CUSTOMERS 7 1.2.3 ESD IMPACT 9 1.3 THE ESD EVENT 10 1.3.1 ESD OVERVIEW
10 1.3.2 CHARGE GENERATION 16 1.3.3 CHARGE TRANSFER 21 1.3.4 CHARGE
CONDUCTION 27 1.3.5 CHARGE INDUCED DAMAGE 46 1.4 DEGRADATION AND LATENCY
52 1.5 TOPICAL REFERENCE LIST 56 1.5.1 ESD AS AN IGNITION SOURCE 56
1.5.2 LIGHTNING 56 1.5.3 ESD IN MANUFACTURING 56 1.5.4 CHARGE GENERATION
57 1.5.5 CHARGE TRANSFER 58 1.5.6 CONDUCTION MECHANISMS 60 1.5.7 DAMAGE
MECHANISMS 60 1.5.8 ESD LATENCY 64 CHAPTER 2 FAILURE ANALYSIS TECHNIQUES
65 2.1 OVERVIEW OF FAILURE ANALYSIS 65 2.2 FAILURE ANALYSIS OBJECTIVES
65 VI 2.3 FAILURE SITE IDENTIFICATION 66 2.3.1 FAILURE ANALYSIS
OPERATIONS 67 2.3.2 DATA REVIEW 68 2.3.3 EXTERNAL EXAMINATION 69 2.3.4
ELECTRICAL VERIFICATION 71 2.3.5 FAILURE SITE LOCALIZATION 75 2.4 ROOT
CAUSE AND CORRECTIVE ACTION 78 2.5 TOPICAL REFERENCE LIST 82 2.5.1 TEST
METHODS 82 2.5.2 FAILURE LOCALIZATION TECHNIQUES 83 2.5.3 ETCHES AND
STAINS 84 2.5.4 EOS VERSUS ESD 84 CHAPTER 3 ENVIRONMENTAL PROTECTION 85
3.1 ENVIRONMENTAL PHILOSOPHY 85 3.1.1 PURPOSE 85 3.1.2 THE NEED 85 3.1.3
PROTECTION STRATEGY 90 3.1.4 ENVIRONMENTAL PROTECTION OVERVIEW 91 3.2
ROOM LEVEL CONTROLS 91 3.3 WORK AREA CONTROLS 94 3.4 PERSONAL CONTROLS
98 3.5 PACKAGING AND STORAGE 100 3.6 HANDLING EQUIPMENT 102 3.7 AUDITING
103 3.8 TOPICAL REFERENCE LIST 105 3.8.1 ROOM CHARGE CONTROLS 105 3.8.2
WORKSTATION CONTROLS 106 3.8.3 PERSONAL CONTROLS 107 3.8.4 EQUIPMENT 108
3.8.5 CONTAINERS 109 3.8.6 AUDITING 109 VLL CHAPTER 4 CHIP LEVEL
PROTECTION 111 4.1 PROTECTION APPROACH ILL 4.2 OFF CHIP PROTECTION 113
4.2.1 PURPOSE 113 4.2.2 PROTECTION OPTIONS 113 4.3 ON-CHIP PROTECTION
120 4.3.1 WAFER TECHNOLOGY ASSESSMENT 121 4.3.2 CIRCUIT ARCHITECTURE
ASSESSMENT 122 4.3.3 PROTECTION TECHNIQUES 125 4.3.4 LAYOUT
CONSIDERATIONS 144 4.3.5 ESD PROTECTION REVIEW 147 4.4 TOPICAL REFERENCE
LIST 148 4.4.1 GENERAL PROTECTION INFORMATION 148 4.4.2 OFF-CHIP
PROTECTION 150 4.4.3 CIRCUIT ELEMENT IMPROVEMENTS 151 4.4.4 CLAMPING
STRUCTURES 153 4.4.5 LAYOUT EFFECTS 155 CHAPTER 5 DEVICE
CHARACTERIZATION 157 5.1 CIRCUIT ELEMENT SENSITIVITY 157 5.1.1 MODELING
LIMITATIONS 157 5.1.2 DEVICE MODELING IN ESD DESIGN 157 5.1.3
MEASUREMENT TECHNIQUES 159 5.2 TLP TESTING 162 5.2.1 CONSTANT CURRENT
TLP TESTER 163 5.2.2 CONSTANT IMPEDANCE TLP TESTER 164 5.2.3 PROBLEMS
AND LIMITATIONS 165 5.2.4 TLP TO HBM CORRELATION 172 5.3
CHARACTERIZATION MATRIX 175 5.4 TOPICAL REFERENCE LIST 177 5.4.1 MOSFET
PROTECTION 177 5.4.2 TRANSMISSION LINE PULSING 178 5.4.3 TLP AND HBM
CORRELATION 179 5.4.4 ESD CHARACTERIZATION 180 VLLL CHAPTER 6 ESD
MODELING 181 6.1 CIRCUIT MODELING 183 6.1.1 INTRODUCTION TO SPICE
SIMULATION 185 6.1.2 PARASITIC INFLUENCE OF ESD PROTECTION 187 6.1.3 KEY
MODELS FOR ESD PROTECTION 188 6.1.4 ESD THRESHOLD PREDICTIONS 194 6.2
DEVICE MODELING 196 6.3 TOPICAL REFERENCE LIST 199 6.3.1 SPICE MODEL
IMPROVEMENTS 199 6.3.2 DEVICE SIMULATION 199 INDEX 201
|
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| ctrlnum | (OCoLC)50948465 (DE-599)BVBBV020821029 |
| dewey-full | 621.3815 |
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| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| illustrated | Illustrated |
| indexdate | 2024-07-09T20:14:03Z |
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| isbn | 140207350X |
| language | English |
| lccn | 2002040683 |
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| physical | VIII, 207 S. Ill. |
| publishDate | 2003 |
| publishDateSearch | 2003 |
| publishDateSort | 2003 |
| publisher | Kluwer |
| record_format | marc |
| spelling | ESD design and analysis handbook by James E. Vinson ... Boston, Mass. Kluwer 2003 VIII, 207 S. Ill. txt rdacontent n rdamedia nc rdacarrier Includes bibliographical references and index Electrostatics Integrated circuits Protection Semiconductors Protection Static eliminators Elektrostatische Entladung (DE-588)4401020-5 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Schutz Elektrotechnik (DE-588)4128586-4 gnd rswk-swf Elektrostatische Entladung (DE-588)4401020-5 s Integrierte Schaltung (DE-588)4027242-4 s Schutz Elektrotechnik (DE-588)4128586-4 s DE-604 Vinson, James E. Sonstige oth HEBIS Datenaustausch Darmstadt application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=013526399&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | ESD design and analysis handbook Electrostatics Integrated circuits Protection Semiconductors Protection Static eliminators Elektrostatische Entladung (DE-588)4401020-5 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Schutz Elektrotechnik (DE-588)4128586-4 gnd |
| subject_GND | (DE-588)4401020-5 (DE-588)4027242-4 (DE-588)4128586-4 |
| title | ESD design and analysis handbook |
| title_auth | ESD design and analysis handbook |
| title_exact_search | ESD design and analysis handbook |
| title_full | ESD design and analysis handbook by James E. Vinson ... |
| title_fullStr | ESD design and analysis handbook by James E. Vinson ... |
| title_full_unstemmed | ESD design and analysis handbook by James E. Vinson ... |
| title_short | ESD design and analysis handbook |
| title_sort | esd design and analysis handbook |
| topic | Electrostatics Integrated circuits Protection Semiconductors Protection Static eliminators Elektrostatische Entladung (DE-588)4401020-5 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Schutz Elektrotechnik (DE-588)4128586-4 gnd |
| topic_facet | Electrostatics Integrated circuits Protection Semiconductors Protection Static eliminators Elektrostatische Entladung Integrierte Schaltung Schutz Elektrotechnik |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=013526399&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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