CMOS circuit design, layout, and simulation:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
New York, NY
IEEE Press
2005
|
| Ausgabe: | second edition |
| Schriftenreihe: | IEEE press series on microelectronic systems
|
| Schlagworte: | |
| Beschreibung: | XXXIII,1038 S. graph. Darst. |
| ISBN: | 047170055X |
Internformat
MARC
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| 650 | 4 | |a Metal oxide semiconductors, Complementary |x Design and construction | |
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| 650 | 0 | 7 | |a MOS-FET |0 (DE-588)4207266-9 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a CMOS |0 (DE-588)4010319-5 |2 gnd |9 rswk-swf |
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| 883 | 1 | |8 2\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
Datensatz im Suchindex
| _version_ | 1804132986068664320 |
|---|---|
| any_adam_object | |
| author | Baker, R. Jacob |
| author_facet | Baker, R. Jacob |
| author_role | aut |
| author_sort | Baker, R. Jacob |
| author_variant | r j b rj rjb |
| building | Verbundindex |
| bvnumber | BV019621868 |
| callnumber-first | T - Technology |
| callnumber-label | TK7871 |
| callnumber-raw | TK7871.99.M44 |
| callnumber-search | TK7871.99.M44 |
| callnumber-sort | TK 47871.99 M44 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ZN 4960 |
| classification_tum | ELT 358f ELT 272f |
| ctrlnum | (OCoLC)250025450 (DE-599)BVBBV019621868 |
| dewey-full | 621.39/732 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/732 |
| dewey-search | 621.39/732 |
| dewey-sort | 3621.39 3732 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | second edition |
| format | Book |
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| id | DE-604.BV019621868 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T20:01:32Z |
| institution | BVB |
| isbn | 047170055X |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-012951232 |
| oclc_num | 250025450 |
| open_access_boolean | |
| owner | DE-1043 DE-91 DE-BY-TUM DE-573 |
| owner_facet | DE-1043 DE-91 DE-BY-TUM DE-573 |
| physical | XXXIII,1038 S. graph. Darst. |
| publishDate | 2005 |
| publishDateSearch | 2005 |
| publishDateSort | 2005 |
| publisher | IEEE Press |
| record_format | marc |
| series2 | IEEE press series on microelectronic systems |
| spelling | Baker, R. Jacob Verfasser aut CMOS circuit design, layout, and simulation R. Jacob Baker CMOS second edition New York, NY IEEE Press 2005 XXXIII,1038 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier IEEE press series on microelectronic systems Integrated circuits Design and construction Metal oxide semiconductor field-effect transistors Metal oxide semiconductors, Complementary Design and construction CMOS-Schaltung (DE-588)4148111-2 gnd rswk-swf Simulation (DE-588)4055072-2 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf MOS-FET (DE-588)4207266-9 gnd rswk-swf CMOS (DE-588)4010319-5 gnd rswk-swf MOS-FET (DE-588)4207266-9 s DE-604 Integrierte Schaltung (DE-588)4027242-4 s Entwurf (DE-588)4121208-3 s CMOS (DE-588)4010319-5 s Schaltungsentwurf (DE-588)4179389-4 s CMOS-Schaltung (DE-588)4148111-2 s 1\p DE-604 Simulation (DE-588)4055072-2 s 2\p DE-604 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Baker, R. Jacob CMOS circuit design, layout, and simulation Integrated circuits Design and construction Metal oxide semiconductor field-effect transistors Metal oxide semiconductors, Complementary Design and construction CMOS-Schaltung (DE-588)4148111-2 gnd Simulation (DE-588)4055072-2 gnd Entwurf (DE-588)4121208-3 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Schaltungsentwurf (DE-588)4179389-4 gnd MOS-FET (DE-588)4207266-9 gnd CMOS (DE-588)4010319-5 gnd |
| subject_GND | (DE-588)4148111-2 (DE-588)4055072-2 (DE-588)4121208-3 (DE-588)4027242-4 (DE-588)4179389-4 (DE-588)4207266-9 (DE-588)4010319-5 |
| title | CMOS circuit design, layout, and simulation |
| title_alt | CMOS |
| title_auth | CMOS circuit design, layout, and simulation |
| title_exact_search | CMOS circuit design, layout, and simulation |
| title_full | CMOS circuit design, layout, and simulation R. Jacob Baker |
| title_fullStr | CMOS circuit design, layout, and simulation R. Jacob Baker |
| title_full_unstemmed | CMOS circuit design, layout, and simulation R. Jacob Baker |
| title_short | CMOS circuit design, layout, and simulation |
| title_sort | cmos circuit design layout and simulation |
| topic | Integrated circuits Design and construction Metal oxide semiconductor field-effect transistors Metal oxide semiconductors, Complementary Design and construction CMOS-Schaltung (DE-588)4148111-2 gnd Simulation (DE-588)4055072-2 gnd Entwurf (DE-588)4121208-3 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Schaltungsentwurf (DE-588)4179389-4 gnd MOS-FET (DE-588)4207266-9 gnd CMOS (DE-588)4010319-5 gnd |
| topic_facet | Integrated circuits Design and construction Metal oxide semiconductor field-effect transistors Metal oxide semiconductors, Complementary Design and construction CMOS-Schaltung Simulation Entwurf Integrierte Schaltung Schaltungsentwurf MOS-FET CMOS |
| work_keys_str_mv | AT bakerrjacob cmoscircuitdesignlayoutandsimulation AT bakerrjacob cmos |