Formal methods in computer-aided design: 5th International Conference, FMCAD 2004, Austin, Texas, USA, November 15 - 17, 2004 ; proceedings
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| Format: | Conference Proceeding Book |
|---|---|
| Language: | English |
| Published: |
Berlin u.a.
Springer
2004
|
| Series: | Lecture Notes in Computer Science
3312 |
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Physical Description: | XI, 444 S. Ill., graph. Darst. 235 mm x 155 mm |
| ISBN: | 3540237380 |
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MARC
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| 245 | 1 | 0 | |a Formal methods in computer-aided design |b 5th International Conference, FMCAD 2004, Austin, Texas, USA, November 15 - 17, 2004 ; proceedings |c Alan J. Hu ... (eds.) |
| 264 | 1 | |a Berlin u.a. |b Springer |c 2004 | |
| 300 | |a XI, 444 S. |b Ill., graph. Darst. |c 235 mm x 155 mm | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Lecture Notes in Computer Science |v 3312 | |
| 650 | 4 | |a Mathematik | |
| 650 | 4 | |a Digital integrated circuits |x Computer-aided design |v Congresses | |
| 650 | 4 | |a Digital integrated circuits |x Design and construction |x Mathematics |v Congresses | |
| 650 | 4 | |a Formal methods (Computer science) |v Congresses | |
| 650 | 4 | |a Integrated circuits |x Verification |v Congresses | |
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| 689 | 2 | |5 DE-604 | |
| 700 | 1 | |a Hu, Alan J. |e Sonstige |4 oth | |
| 711 | 2 | |a FMCAD |n 5 |d 2004 |c Austin, Tex. |j Sonstige |0 (DE-588)6035338-7 |4 oth | |
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Record in the Search Index
| _version_ | 1826212289198424064 |
|---|---|
| adam_text |
TABLE
OF
CONTENTS
CHALLENGES
IN
SYSTEM-LEVEL
DESIGN
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
WAYNE
WOLF
GENERATING
FAST
MULTIPLIERS
USING
CLEVER
CIRCUITS
.
.
.
.
.
.
.
.
.
.
.
6
MARY
SHEERAN
VERIYYCATION
OF
ANALOG
AND
MIXED-SIGNAL
CIRCUITS
USING
HYBRID
SYSTEM
TECHNIQUES
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
21
THAO
DANG,
ALEXANDRE
DONZ´E,
AND
ODED
MALER
A
METHODOLOGY
FOR
THE
FORMAL
VERIYYCATION
OF
FFT
ALGORITHMS
IN
HOL
.
.
37
BEHZAD
AKBARPOUR
AND
SOYY`ENE
TAHAR
A
FUNCTIONAL
APPROACH
TO
THE
FORMAL
SPECIYYCATION
OF
NETWORKS
ON
CHIP
.
52
JULIEN
SCHMALTZ
AND
DOMINIQUE
BORRIONE
PROOF
STYLES
IN
OPERATIONAL
SEMANTICS
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
67
SANDIP
RAY
AND
J.
STROTHER
MOORE
INTEGRATING
REASONING
ABOUT
ORDINAL
ARITHMETIC
INTO
ACL2
.
.
.
.
.
.
82
PANAGIOTIS
MANOLIOS
AND
DARON
VROON
COMBINING
EQUIVALENCE
VERIYYCATION
AND
COMPLETION
FUNCTIONS
.
.
.
.
.
98
MARK
D.
AAGAARD,
VLAD
C.
CIUBOTARIU,
JASON
T.
HIGGINS,
AND
FARZAD
KHALVATI
SYNCHRONIZATION-AT-RETIREMENT
FOR
PIPELINE
VERIYYCATION
.
.
.
.
.
.
.
.
.
113
MARK
D.
AAGAARD,
NANCY
A.
DAY,
AND
ROBERT
B.
JONES
LATE
DESIGN
CHANGES
(ECOS)
FOR
SEQUENTIALLY
OPTIMIZED
ESTEREL
DESIGNS
.
.
.
.
.
.
.
.
.
.
.
.
.
.
128
LAURENT
ARDITI,
GERARD
BERRY,
AND
MICHAEL
KISHINEVSKY
NON-MITER-BASED
COMBINATIONAL
EQUIVALENCE
CHECKING
BY
COMPARING
BDDS
WITH
DIYYERENT
VARIABLE
ORDERS
.
.
.
.
.
.
.
.
.
.
144
IN-HO
MOON
AND
CARL
PIXLEY
SCALABLE
AUTOMATED
VERIYYCATION
VIA
EXPERT-SYSTEM
GUIDED
TRANSFORMATIONS
.
.
.
.
.
.
.
.
.
.
.
.
.
.
159
HARI
MONY,
JASON
BAUMGARTNER,
VIRESH
PARUTHI,
ROBERT
KANZELMAN,
AND
ANDREAS
KUEHLMANN
X
TABLE
OF
CONTENTS
SIMPLE
YET
EYYCIENT
IMPROVEMENTS
OF
SAT
BASED
BOUNDED
MODEL
CHECKING
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
174
EMMANUEL
ZARPAS
SIMPLE
BOUNDED
LTL
MODEL
CHECKING
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
186
TIMO
LATVALA,
ARMIN
BIERE,
KEIJO
HELJANKO,
AND
TOMMI
JUNTTILA
QUBE
++:
AN
EYYCIENT
QBF
SOLVER
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
201
ENRICO
GIUNCHIGLIA,
MASSIMO
NARIZZANO,
AND
ARMANDO
TACCHELLA
BOUNDED
PROBABILISTIC
MODEL
CHECKING
WITH
THE
MUR
YY
VERIYYER
.
.
.
.
.
214
GIUSEPPE
DELLA
PENNA,
BENEDETTO
INTRIGILA,
IGOR
MELATTI,
ENRICO
TRONCI,
AND
MARISA
VENTURINI
ZILLI
INCREASING
THE
ROBUSTNESS
OF
BOUNDED
MODEL
CHECKING
BY
COMPUTING
LOWER
BOUNDS
ON
THE
REACHABLE
STATES
.
.
.
.
.
.
.
.
.
230
MOHAMMAD
AWEDH
AND
FABIO
SOMENZI
BOUNDED
VERIYYCATION
OF
PAST
LTL
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
245
ALESSANDRO
CIMATTI,
MARCO
ROVERI,
AND
DANIEL
SHERIDAN
A
HYBRID
OF
COUNTEREXAMPLE-BASED
AND
PROOF-BASED
ABSTRACTION
.
.
.
.
260
NINA
AMLA
AND
KEN
L.
MCMILLAN
MEMORY
EYYCIENT
ALL-SOLUTIONS
SAT
SOLVER
AND
ITS
APPLICATION
FOR
REACHABILITY
ANALYSIS
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
275
ORNA
GRUMBERG,
ASSAF
SCHUSTER,
AND
AVI
YADGAR
APPROXIMATE
SYMBOLIC
MODEL
CHECKING
FOR
INCOMPLETE
DESIGNS
.
.
.
.
.
290
TOBIAS
NOPPER
AND
CHRISTOPH
SCHOLL
EXTENDING
EXTENDED
VACUITY
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
306
ARIE
GURYYNKEL
AND
MARSHA
CHECHIK
PARAMETERIZED
VACUITY
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
322
MARKO
SAMER
AND
HELMUT
VEITH
AN
OPERATIONAL
SEMANTICS
FOR
WEAK
PSL
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
337
KOEN
CLAESSEN
AND
JOHAN
MYYARTENSSON
ACCEPTING
PREDECESSORS
ARE
BETTER
THAN
BACK
EDGES
IN
DISTRIBUTED
LTL
MODEL-CHECKING
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
352
LUBOYYS
BRIM,
IVANA
YY
CERN´A,
PAVEL
MORAVEC,
AND
JIYYR´YY
YY
SIMYYSA
BLOOM
FILTERS
IN
PROBABILISTIC
VERIYYCATION
.
.
.
.
.
.
.
.
.
.
.
.
.
.
367
PETER
C.
DILLINGER
AND
PANAGIOTIS
MANOLIOS
A
SIMPLE
METHOD
FOR
PARAMETERIZED
VERIYYCATION
OF
CACHE
COHERENCE
PROTOCOLS
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
382
CHING-TSUN
CHOU,
PHANINDRA
K.
MANNAVA,
AND
SEUNGJOON
PARK
TABLE
OF
CONTENTS
XI
A
PARTITIONING
METHODOLOGY
FOR
BDD-BASED
VERIYYCATION
.
.
.
.
.
.
.
.
399
DEBASHIS
SAHOO,
SUBRAMANIAN
IYER,
JAWAHAR
JAIN,
CHRISTIAN
STANGIER,
AMIT
NARAYAN,
DAVID
L.
DILL,
AND
E.
ALLEN
EMERSON
INVARIANT
CHECKING
COMBINING
FORWARD
AND
BACKWARD
TRAVERSAL
.
.
.
.
.
414
CHRISTIAN
STANGIER
AND
THOMAS
SIDLE
VARIABLE
REUSE
FOR
EYYCIENT
IMAGE
COMPUTATION
.
.
.
.
.
.
.
.
.
.
.
.
430
ZIJIANG
YANG
AND
RAJEEV
ALUR
AUTHOR
INDEX
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
445 |
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| bvnumber | BV019619167 |
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| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Conference Proceeding Book |
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| genre | (DE-588)1071861417 Konferenzschrift 2004 Austin Tex. gnd-content |
| genre_facet | Konferenzschrift 2004 Austin Tex. |
| id | DE-604.BV019619167 |
| illustrated | Illustrated |
| indexdate | 2025-03-10T13:02:33Z |
| institution | BVB |
| institution_GND | (DE-588)6035338-7 |
| isbn | 3540237380 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-012948602 |
| oclc_num | 253855378 |
| open_access_boolean | |
| owner | DE-384 DE-91G DE-BY-TUM DE-739 DE-11 DE-706 |
| owner_facet | DE-384 DE-91G DE-BY-TUM DE-739 DE-11 DE-706 |
| physical | XI, 444 S. Ill., graph. Darst. 235 mm x 155 mm |
| publishDate | 2004 |
| publishDateSearch | 2004 |
| publishDateSort | 2004 |
| publisher | Springer |
| record_format | marc |
| series | Lecture Notes in Computer Science |
| series2 | Lecture Notes in Computer Science |
| spelling | Formal methods in computer-aided design 5th International Conference, FMCAD 2004, Austin, Texas, USA, November 15 - 17, 2004 ; proceedings Alan J. Hu ... (eds.) Berlin u.a. Springer 2004 XI, 444 S. Ill., graph. Darst. 235 mm x 155 mm txt rdacontent n rdamedia nc rdacarrier Lecture Notes in Computer Science 3312 Mathematik Digital integrated circuits Computer-aided design Congresses Digital integrated circuits Design and construction Mathematics Congresses Formal methods (Computer science) Congresses Integrated circuits Verification Congresses Formale Methode (DE-588)4333722-3 gnd rswk-swf Model Checking (DE-588)4434799-6 gnd rswk-swf Verifikation (DE-588)4135577-5 gnd rswk-swf CAD (DE-588)4069794-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 2004 Austin Tex. gnd-content CAD (DE-588)4069794-0 s Formale Methode (DE-588)4333722-3 s DE-604 Model Checking (DE-588)4434799-6 s Verifikation (DE-588)4135577-5 s Hu, Alan J. Sonstige oth FMCAD 5 2004 Austin, Tex. Sonstige (DE-588)6035338-7 oth Lecture Notes in Computer Science 3312 (DE-604)BV000000607 3312 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=012948602&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Formal methods in computer-aided design 5th International Conference, FMCAD 2004, Austin, Texas, USA, November 15 - 17, 2004 ; proceedings Lecture Notes in Computer Science Mathematik Digital integrated circuits Computer-aided design Congresses Digital integrated circuits Design and construction Mathematics Congresses Formal methods (Computer science) Congresses Integrated circuits Verification Congresses Formale Methode (DE-588)4333722-3 gnd Model Checking (DE-588)4434799-6 gnd Verifikation (DE-588)4135577-5 gnd CAD (DE-588)4069794-0 gnd |
| subject_GND | (DE-588)4333722-3 (DE-588)4434799-6 (DE-588)4135577-5 (DE-588)4069794-0 (DE-588)1071861417 |
| title | Formal methods in computer-aided design 5th International Conference, FMCAD 2004, Austin, Texas, USA, November 15 - 17, 2004 ; proceedings |
| title_auth | Formal methods in computer-aided design 5th International Conference, FMCAD 2004, Austin, Texas, USA, November 15 - 17, 2004 ; proceedings |
| title_exact_search | Formal methods in computer-aided design 5th International Conference, FMCAD 2004, Austin, Texas, USA, November 15 - 17, 2004 ; proceedings |
| title_full | Formal methods in computer-aided design 5th International Conference, FMCAD 2004, Austin, Texas, USA, November 15 - 17, 2004 ; proceedings Alan J. Hu ... (eds.) |
| title_fullStr | Formal methods in computer-aided design 5th International Conference, FMCAD 2004, Austin, Texas, USA, November 15 - 17, 2004 ; proceedings Alan J. Hu ... (eds.) |
| title_full_unstemmed | Formal methods in computer-aided design 5th International Conference, FMCAD 2004, Austin, Texas, USA, November 15 - 17, 2004 ; proceedings Alan J. Hu ... (eds.) |
| title_short | Formal methods in computer-aided design |
| title_sort | formal methods in computer aided design 5th international conference fmcad 2004 austin texas usa november 15 17 2004 proceedings |
| title_sub | 5th International Conference, FMCAD 2004, Austin, Texas, USA, November 15 - 17, 2004 ; proceedings |
| topic | Mathematik Digital integrated circuits Computer-aided design Congresses Digital integrated circuits Design and construction Mathematics Congresses Formal methods (Computer science) Congresses Integrated circuits Verification Congresses Formale Methode (DE-588)4333722-3 gnd Model Checking (DE-588)4434799-6 gnd Verifikation (DE-588)4135577-5 gnd CAD (DE-588)4069794-0 gnd |
| topic_facet | Mathematik Digital integrated circuits Computer-aided design Congresses Digital integrated circuits Design and construction Mathematics Congresses Formal methods (Computer science) Congresses Integrated circuits Verification Congresses Formale Methode Model Checking Verifikation CAD Konferenzschrift 2004 Austin Tex. |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=012948602&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV000000607 |
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