Holdings: International Conference on Computer Aided Design

International Conference on Computer Aided Design: November 9 - 13, 2003, Doubletree Hotel, San Jose, CA ; [IEEE ACM digest of technical papers]

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Bibliographic Details
Corporate Author:	International Conference on Computer Aided Design (Institute of Electrical and Electronics Engineers) San José, Calif (Author)
Format:	Conference Proceeding Book
Language:	English
Published:	Los Alamitos, Calif. [u.a.] IEEE [u.a.] 2003
Subjects:	CAD Konferenzschrift > 2002 > Los Alamitos Calif. Konferenzschrift > 2002 > San Jose Calif.
Online Access:	Inhaltsverzeichnis
ISBN:	1581137621

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adam_text	Table of Contents Conference Committee ..................................................................................................................... iii Foreword ............................................................................................................................................iv Awards ................................................................................................................................................ v Technical Program Committee ........................................................................................................vi Reviewers .........................................................................................................................................viii Keynote ............................................................................................................................................... χ Tutorial 1: LINUX for EDA ....................................................................................................xi Tutorial 2: Leakage Issues in 1С Design: Trends, Estimation, and Avoidance ..................xi Tutorial 3: Recent Advances in Formal Verification ..........................................................xiii Tutorial 4: Embedded Software Development ....................................................................xiv Sunday Panel: CAD for High-End Design: Help, Hope, or Hype? ...........................................xv Monday Panel: Semiconductor Slowdown: Who Will Blink First? ..........................................xvi Session 1A Interconnect-Centric SoC Design Moderators: Kaustav Banerjee - Univ. of California, Santa Barbara, CA Tajana Simunk - Hewlett-Packard LabsJStanford Univ., Palo Alto, CA 1A.1 Adaptive Error Protection for Energy Efficiency ...........................................................................2 Lin Li, N. Vijaykrishnan, Mahmut Kandemir, Mary Jane Irwin 1A.2 SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips ................................8 Ruibing Lu, Cheng -Кок Koh 1A.3 The Y-Architecture for On-Chip Interconnect: Analysis and Methodology ..............................13 Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion Mandoiu, Qinke Wang, Bo Yao Session IB Energy Optimization using Dynamic Voltage Scaling for Embedded Systems Moderators: Stan Y. Liao - Synopsys, Inc., Mountain View, CA Hiroyuki Tomiyama - Nagoya Univ., Nagoya, Japan 1B.1 Generalized Network Flow Techniques for Dynamic Voltage Scaling in Hard Real- Time Systems ....................................................................................................................................21 Vishnu Swaminathan, Krishnendu Chakrabarty xvii 1В.2 Approaching the Maximum Energy Saving on Embedded Systems with Multiple Voltages .............................................................................................................................................26 Shaoxiong Hua, Gang Qu 1B.3 Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-Time Embedded Systems ...................................................................................30 Le Yan, Jiong Luo, Niraj K. Jha Session 1С New Opportunities in High-Level Synthesis Moderators: James С Hoe - Carnegie Mellon Univ., Pittsburgh, PA Steve Haynal - Intel Corp., Hillsboro, OR ICI RTL Power Optimization with Gate Level Accuracy ...................................................................39 Qi Wang, Sumit Roy 1C.2 Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications ......................................................................................................................................46 Chao Huang, Srivaths Ravi, Ananá Raghunathan, Niraj K. Jha 1C.3 Achieving Design Closure Through Delay Relaxation Parameter ...............................................54 Ankur Srivastava, Seda Ogrenci Memik, Bo-Kyung Choi, Majid Sarrafzadeh 1C.4 Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading .......................................................................................................................58 Brian Swahn, Soha Hassoun Session ID New Ideas in Placement and Floorplanning Moderators: Zhigang (David) Pan - IBM Corp., Yorktown Heights, NY Kia Bazargan - Univ. of Minnesota, Minneapolis, MN 1D.1 Bus-Driven Floorplanning ...............................................................................................................66 Hua Xiang, Xiaoping Tang, Martin D. F. Wong 1 D.2 A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning ....................................74 Peter G. Sassone, Sung K. Lim 1D.3 Placement Method Targeting Predictability Robustness and Performance ...............................81 Cris t ine IA ba bei, Kia Bazargan 1 D.4 Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach ..........................................................................................................................................86 Brent A. Goplen, Sachin S. Sapât nekar Session 2A Improvements in SoC Testing Moderators: Božena Kaminska - 3MTS, Lake Oswego, OR Krishnendu Chakrabarty - Duke Univ., Durham, NC 2A.1 Partial Core Encryption for Performance-Efficient Test of SoCs ............................................... 91 Ozgur Sinanoglu, Alex Orailoglu 2A.2 ТАМ Optimization for Mixed-Signal SoCs using Analog Test Wrappers ..................................95 Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty xviii 2A.3 Using Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints .............................................................................................100 Yu Xia, Małgorzata E. Chrzanowska-Jeske, Benyi Wang, Marcin Ješke Session 2В Electrical and Power Models - System to Transistor Level Moderators: David Overhauser - Cadence Design Systems, Inc., San Jose, CA Farid N. Najm - Univ. of Toronto, Toronto, Canada 2B.1 Moment-Based Power Estimation in Very Deep Submicron Technologies ..............................107 Alberto Garcia-Ortiz, Lukusa Kabulepa, Tudor Murgan, Manfred Glesner 2B.2 IDAP: A Tool for High Level Power Estimation of Custom Array Structures ........................113 Mahesh N. Mamidipaka, Kamal Khouri, Nikil Dutí, Magdy Abadir 2B.3 SOI Transistor Model for Fast Transient Simulation .................................................................120 Dmitry Nadezhin, Sergey Gavrilov, Alexey Glebov, Yury Egorov, Vladimir P. Zolotov, DavidBlaauw, Rajendran Panda, Murat Becer, Alexandre Ardelea, Ajay Patel Session 2C Embedded Tutorial: Design and CAD Challenges for sub^Onm CMOS Technology Moderators: Dennis Sylvester - Univ. of Michigan, Ann Arbor, MI Thomas Burd - Consultant, Berkeley, CA 2C.1 Embedded Tutorial: Design and CAD Challenges in sub-90nm CMOS Technologies ............129 Kerry Bernstein, Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri Session ЗА Emerging Techniques in Dynamic Verification Moderators: Jay Lawrence - Cadence Design Systems, Inc., Chelmsford, MA Arturo Salz - Synopsys, Inc., Mountain View, CA 3A.1 Fast Cycle-Accurate Behavioral Simulation for Pipelined Processors using Early Pipeline Evaluation ........................................................................................................................138 In-Cheol Park, Sehyeon Kang, Yongseok Yi 3A.2 A Framework for Constrained Functional Verification .............................................................142 Jun Yuan, Carl Pixley, Adnan Aziz, Ken Albin 3A.3 Generator-Based Verification .......................................................................................................146 Yunshan Zhu, James H. Kukula 3A.4 Efficient Generation of Monitor Circuits for GSTE Assertion Graphs ....................................154 Alan J. Ни, Jeremy Casas, Jin Yang Session 3B Delay and Signal Modeling for Timing Analysis Moderators: David J. Hathaway - IBM Corp., Essex Junction, VT Timothy Burks - Magma Design Automation, Cupertino, С А 3B.1 Weibull Based Analytical Waveform Model ................................................................................161 Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail xix 3B.2 Equivalent Waveform Propagation for Static Timing Analysis ................................................169 Masanori Hashimoto, Yuji Yantada, Hidetoshi Onodera 3B.3 Timing Analysis in Presence of Power Supply and Ground Voltage Variations ......................176 Rubil Ahmadi, FaridN. Najm 3B.4 Vectorless Analysis of Supply Noise Induced Delay Variation ..................................................184 Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda Session 3C Software Techniques for Energy and Performance Optimization in Embedded Systems Moderators: Wen-Mei W. Hwu - Univ. of Illinois, Urbana, IL Rainer Leupers - RWTH Aachen Univ. of Tech., Aachen, Germany 3d Array Composition and Decomposition for Optimizing Embedded Applications ...................193 Guilin Chen, Mahmut Kandemir, Ugur Sezer, Avanti Nadgir 3C.2 Code Placement with Selective Cache Activity Minimization for Embedded Real-Time Software Design ..............................................................................................................................197 Junhyung Urn, Taewhan Kim 3C.3 Energy Optimization of Distributed Embedded Processors by Combined Data Compression and Functional Partitioning ...................................................................................201 Jinfeng Liu, Pai H. Chou 3C.4 Energy-Aware Fault Tolerance in Fixed-Priority Real-Time Embedded Systems ..................209 Ying Zhang, Krishnendu Chakrabarty, Vishnu Swaminathan Session 3D Optimization of Global Interconnects Moderators: Martin D. F. Wong - Univ. of Illinois, Urbana, IL Atsushi Takahashi- Tokyo Institute of Tech., Tokyo, Japan 3D.1 Retiming for Wire Pipelining in System-On-Chip ......................................................................215 Chuan Lin, Hai Zhou 3D.2 Retiming with Interconnect and Gate Delay ...............................................................................221 Chris Chu, Evangeline F. Y. Young, Dennis K. Y. Tong, Sampath Dechu 3D.3 Performance Optimization of Latency Insensitive Systems through Buffer Queue Sizing of Communication Channels .............................................................................................227 Ruibing Lu, Cheng -Кок Koh 3D.4 Clock Scheduling and Clocktree Construction for High Performance ASICs .........................232 Stephan Held, Bernhard Korte, Jens Maßberg, Matthias Ringe, Jens Vygen xx Session 4A Numerical Methods for Analog Optimization and Analysis Moderators: Eric Bracken - Anso f t Corp., Pittsburgh, PA Joel R. Phillips - Cadence Berkeley Labs., San Jose, С А 4A.1 Initial Sizing of Analog Integrated Circuits by Centering within Topology-Given Implicit Specifications ...................................................................................................................241 Guido Stehr, Michael Pronath, Frank Schenkel, Helmut Graeb, Kurt Antreich 4A.2 A Generalized Method for Computing Oscillator Phase Noise Spectra ....................................247 Piet Vanassche, Georges G. Gielen, Willy Sansen 4A.3 Efficient Iterative Time Preconditioners for Harmonic Balance RF Circuit Simulation ........251 Fabrice Veersé Session 4B CAD Algorithms for Emerging Technologies Moderators: Bernard Courtois - TIMA Labs., Grenoble, France Michael R. Butts - Cadence Design Systems, Inc., Portland, OR 4B.1 Fredkin/Toffoli Templates for Reversible Logic Synthesis ........................................................256 Dmitri Maslov, Gerhard W. Dueck, David M. Miller 4B.2 Evaluation of Placement Techniques for DNA Probe Array Layout ........................................262 Andrew B. Kahng, Ion Mandoiu, Sherief Reda, Хи Хи, Alex Z. Zelikovsky 4B.3 Physical and Reduced-Order Dynamic Analysis of MEMS .......................................................270 Sudipto K. DE, Nar ay an Aluru Session 4C Design Techniques for Customized Processors Moderators: Radu Marculescu - Carnegie Mellon Univ., Pittsburgh, PA Tony Givargis - Univ. of California, Irvine, CA 4C.1 Fast, Accurate Static Analysis for Fixed-Point Finite Precision Effects in DSP Designs .........275 Claire F. Fang, Rob A. Rutenbar, Tsuhan Chen 4C.2 A Scalable Application-Specific Processor Synthesis Methodology ..........................................283 Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha 4C.3 INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors .......................................................................................................................................291 Newton Cheung, Sri Parameswaran, Joerg Henkel Session 4D New Improvements in Placement Moderators: Kia Bazargan - Univ. of Minnesota, Minneapolis, MN Salii Raje - Hier Design Inc., Santa Clara, CA 4D.1 An Enhanced Multilevel Algorithm for Circuit Placement ........................................................299 Tony F. Chan, Jason Cong, Tim Kong, Joseph R. Shinnerl, Kenton Sze 4D.2 Fractional Cut: Improved Recursive Bisection Placement .........................................................307 Ameya Agnihotri, Mehmet С. YILDIZ, Ateen Khatkhate, Ajita Mathur, Satoshi Ono, Patrick H. Madden xxi 4D.3 On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis ......................311 Saurabh N. Adya, Igor L. Markov, Paul G Villarrubia Session 5A Optimizations for Verification Engines Moderators: Aarti Gupta - NEC Labs., Princeton, NJ Eugene Goldberg - Cadence Berkeley Labs., Berkeley, CA 5A.1 ŠATORI - A Fast Sequential SAT Engine for Circuits ............................................................320 Madhu Iyer, Ganapathy Parthasarathy, Kwang Ting (Tim) Cheng 5A.2 САМА: A Multi-Valued Satisfiability Solver ..............................................................................326 Cong Liu, Andreas Kuehlmann, Matthew W. Moskewicz 5A.3 The Compositional Far Side of Image Computation ..................................................................334 Chao Wang, Gary D. Hachtel, Fabio Somenzi Session 5B System Design Concepts Moderators: Vijaykrishnan Narayanan - Penn State Univ., University Park, PA Yatin Hoskote - Intel Corp., Portland, OR 5B.1 Cache Optimization For Embedded Processor Cores: An Analytical Approach .....................342 Arijit Ghosh, Tony Givargis 5B.2 Fault-Tolerant Techniques for Ambient Intelligent Distributed Systems .................................348 Diana Marculescu, Nicholas H. Zamora, Phillip Stanley-Marbell, Radu Marculescu 5B.3 Performance Efficiency of Context-Flow System-On-Chip Platform .......................................356 Rami Beidas, Jianwen Zhu Session 5C Analog Design and Methodology Moderators: Kenneth Kundért - Cadence Design Systems, Inc., San Jose, CA Georges G. Gielen - Katholieke Univ., Leuven, Belgium 5C.1 Amplification of Ultrawideband Signals ......................................................................................363 Won Namgoong, Jongrit Lerdworatawee 5C.2 A Statistical Approach to Estimate the Dynamic Non-Linearity Parameters of Pipeline ADCs ...............................................................................................................................................367 Mohammad Taherzadeh-Sani, Reza Lotfi, Omid Shoaei 5C.3 Systematic Design for Power Minimization of Pipelined Analog-to-Digital Converters .........371 Reza Lotfi, Mohammad Taherzadeh-Sani, Mohammad Yaser Azizi, Omid Shoaei 5C.4 A Framework for Designing Reusable Analog Circuits .............................................................375 Dean Liu, Stefanos Sidiropoulos, Mark Horowtiz xxii Session 5D Routing Moderators: Hai Zhou - Northwestern Univ., Evanston, IL Charles Chiang - Synopsys, Inc., Mountain View, CA 5D.1 A Fast Crosstalk- and Performance-Driven Multilevel Routing System..................................382 Tsung-Yi Ho, Yao-Wen Chang, Sao -Ле Chen, and D. T. Lee 5D.2 A Min-Cost Flow Based Detailed Router for FPGAs ..................................................................388 Seokjin Lee, Yongseok Cheon, Martin D. F. Wong 5D.3 Length-Matching Routing for High-Speed Printed Circuit Boards ..........................................394 Muhammet Mustafa Ozdal, Martin D. F. Wong 5D.4 Analytical Bound for Unwanted Clock Skew Due to Wire Width Variation ...........................401 Anand K. Rajaram, Bing Lu, Wei Guo, Rabi N. Mahapatra, Jiang Ни Session 6A Automatic Abstraction for Formal Verification Moderators: James H. Kukula - Synopsys, Inc., Hillsboro, OR Ken McMillan - Cadence Berkeley Labs., Berkeley, CA 6A.1 Improving Ariadne s Bundle by Following Multiple Threads in Abstraction Refinement ......................................................................................................................................408 Chao Wang, Bing Li, HoonSang Jin, Gary D. Hachtel, Fabio Somenzi 6A.2 Iterative Abstraction using SAT-based BMC with Proof Analysis ...........................................416 Aarti Gupta, Malay Ganai, Zijiang Yang, Pranav Ashar 6A.3 Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits .......424 Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda Session 6B Embedded Tutorial: System Level Design and Verification using a Synchronous Lan Moderators: Nikil Dutt - Univ. of California, Irvine, С А Joerg Henkel - NEC Labs., Princeton, NJ 6B.1 Embedded Tutorial: System Level Design and Verification using a Synchronous Language ........................................................................................................................................433 Gérard Berry, Michael Kishinevshy, Satnam Singh Session 6C Nonlinear Modelling of Analog and Optical Systems Moderators: Jaijeet Roychowdhury - Univ. of Minnesota, Minneapolis, MN Mustafa Celik - Magma Design Automation, Cupertino, С А 6C.1 Noise Analysis for Optical Fiber Communication Systems ........................................................441 Alper Demir 6C.2 Analog Macromodeling using Kernel Methods ...........................................................................446 Joel R. Phillips, João Pedro Afonso, Arlindo Oliveira, Ĺ. Miguel Silveira xxiii 6C.3 A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits ............................................................................................................................................454 Peng Li, Xin Li, YangXu, Lawrence T. Pileggi Session 6D Timing and Tradeoffs in Placement Moderators: Igor L. Markov - Univ. of Michigan, Ann Arbor, MI Rajeev Jayaraman - Xilinx Inc., San Jose, CA 6D.1 Incremental Placement for Timing Optimization .......................................................................463 Wonjoon Choi, Kia Bazargan 6D.2 A Trade-off Oriented Placement Tool ..........................................................................................467 Huaiyu Xu, Maogang Wang, Bo-Kyung Choi, Majid Sarrafzadeh 6D.3 Optimality and Stability Study of Timing-Driven Placement Algorithms ................................472 Jason Cong, Michail Romesis, Min Xie Session 7A Simulation at the Nanometer Scale Moderators: Kenneth Kundért - Cadence Design Systems, Inc, San Jose, CA Narayan Aluru - Univ. of Illinois, Urbana, IL 7A.1 A Probabilistic-Based Design Methodology for Nanoscale Computation .................................480 R. Iris Bahar, Joseph Mundy, Jie Chen 7A.2 Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation .......................................................................................................................................487 Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy 7A.3 Circuit Simulation of Nanotechnology Devices with Non-Monotonic I-V Characteristics ...............................................................................................................................491 Jiayong Le, Lawrence T. Pileggi, Anirudh Devgan 7A.4 A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits ............................................................................................................................................497 Santanu Mahapatra, Kaustav Banerjee, Florent Pegeon, Adrian M. Ionescu Session 7B Energy Issues in Systems Design Moderators: Wolfgang Nebel - Oldenburg Univ. and OFFIS, Oldenburg, Germany Marcello Lajolo - NEC Labs., Princeton, NJ 7B.1 A Game Theoretic Approach to Dynamic Energy Minimization in Wireless Transceivers ...................................................................................................................................504 Alilranli, Hani/ Fatemi, MassoudPedram 7B.2 Communication-Aware Task Scheduling and Voltage Selection for Total Systems Energy Minimization .....................................................................................................................510 Girish V. Varatkar, Radu Marculescu 7B J LRU-SEQ: A Novel Replacement Policy for Transition Energy Reduction in Instruction Caches .........................................................................................................................518 Proveen G. Kalla, Xiaobo Sharon Hu, Joerg Henkel xxiv 7B.4 Compiler-Based Register Name Adjustment for Low-Power Embedded Processors ..............523 Peter Petrov, Alex Orailoglu Session 7C Constraint Driven High-Level Synthesis Moderators: Michael Kishinevsky - Intel Corp., Hillsboro, OR Barry Pangrle - Synopsys, Inc., Mountain View, CA 7C.1 Gradual Relaxation Techniques with Applications to Behavioral Synthesis ............................529 Zhiru Zhang, Yiping Fan, Miodrag Potkonjak, Jason Cong 7C.2 Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication ..............................................................................................................................536 Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang 7C.3 Binding, Allocation and Floorplanning in Low Power High-Level Synthesis ..........................544 Ansgar Stammermann, Domenik Helms, Milan Schulte, Arne Schulz, Wolfgang Nebel 7C.4 A High-Level Interconnect Power Model for Design Space Exploration ..................................551 Pallav Gupta, Lin Zhong, Niraj K. Jha Session 7D Optimal Interconnect Synthesis and Analysis Moderators: Leon Stok - IBM Corp., Yorktown Heights, NY John P. Fishburn - Consultant, Murray Hill, NJ 7D.1 A Probabilistic Approach to Buffer Insertion .............................................................................560 Vishal Khandelwal, Azadeh Davoodi, Akash Nanavati, Ankur Sr ivas tava 7D.2 Simultaneous Analytic Area and Power Optimization for Repeater Insertion ........................568 Giuseppe S. Garcea, Nick P. van der Meijs, Ralph H. J. M. Otten 7D.3 Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion .................................................................................................574 Weiping Liao, Lei He 7D.4 Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing ...................................581 Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng Session 8A Memory Testing Moderators: Yervant Zorian - Virage Logic, Fremont, CA Adit Singh - Auburn Univ., Montgomery, AL 8A.1 Dynamic Data-bit Memory Built-in Self-Repair .........................................................................588 Michael Nicolaidis, Nadir Achouri, Slimane Boutobza 8A.2 FAME: A Fault-Pattern Based Memory Failure Analysis Framework ....................................595 Kuo-Liang Cheng, Chih-Wea Wang, Jih-NungLee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu 8A.3 Hardware/Software Co-Testing of Embedded Memories in Complex SoCs ............................599 Bai Hong Fang, Qiang Xu, Nicola Nicoiici xxv Session 8В Statistical Static Timing - 1 Moderators: Louis Scheffer - Cadence Design Systems, Inc., San Jose, CA Duncan M. (Hank) Walker - Texas A&M Univ., College Station, TX 8B. I Block-Based Static Timing Analysis with Uncertainty ...............................................................607 Anirudh Devgan, Chandramouli Kashyap 8B.2 TAU: Timing Analysis Under Uncertainty ..................................................................................615 Sarvesh Bhardwaj, Sarma В. Vrudhula, David Blaauw 8B.3 Statistical Timing Analysis Considering Spatial Correlations Using a Single PERT- like Traversal ..................................................................................................................................621 Hongliang Chang, Sachin S. Sapatnekar Session 8C Power-Aware Design Moderators: Tanay Kamik - Intel Corp., Hillsboro, OR Bora Nikolic - Univ. of California, Berkeley, С А 8C.1 Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches .............................................................................................................................................627 Nam S. Kim, David Blaauw, Trevor N. Mudge 8C.2 Dynamic Fault-Tolerance and Metrics for Battery Powered, Failure-Prone Systems ............633 Phillip Stanley-Marbell, Diana Marculescu 8C.3 Dynamic Platform Management for Configurable Platform-Based System-on-Chips ............641 Krishna Sekar, Kanishka Lahiri, Suj it Dey Session 8D Interconnect Reduction Moderators: Chung-Kuan Cheng - Univ. of California at San Diego, La J olla, CA Eli Chiprout - Intel Corp., Chandler, AZ 8D.1 A General s-Domain Hierarchical Network Reduction Algorithm........................................... 650 Sheldon X.-D. Tan 8D.2 Branch Merge Reduction of RLCM Networks ............................................................................658 Bernard N. Sheehan 8D 3 A Sum-Over-Paths Impulse-Response Moment-Extraction Algorithm for IC- Interconnect Networks: Verification, Coupled RC Lines ..........................................................665 Yannick L. Le Coz, Dhivya Krishna, Dusan M. Petranovic, William M. Loh, Peter Bendix Session 9A Embedded Tutorial: Mixed Signal DFT: A Concise Overview Moderators: Erik Larsson - Linköping Univ., Linköping, Sweden Sule Ozev - Duke Univ., Durham, NC 9A.1 Embedded Tutorial: Mixed Signal DFT: A Concise Overview _______________________672 Božena Kaminska, Karím Arabi xxvi Session 9В Embedded Tutorial: Manufacturing-Aware Physical Design Moderators: Sani R. Nassif- IBM Corp., Austin, TX Sachin S. Sapatnekar - Univ. of Minnesota, Minneapolis, MN 9B.1 Embedded Tutorial: Manufacturing-Aware Physical Design ....................................................681 Andrew B. Kahng, Puneet Gupta Session 9C Cool Topics in Logic Synthesis Moderators: Olivier R. Coaderì - Monterey Design Systems, Inc., Sunnyvale, CA Diana Marculescu - Carnegie Mellon Univ., Pittsburgh, PA 9C.1 A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits ............................................................................................................................................689 Rahul M. Rao, Frank Liu, Jeffrey L. Burns, Richard В . Brown 9C.2 Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level ..................................................693 Yuvraj S. Dhillon, Abdulkadir U. Diril, Abhijit Chatter/ ее, Hsien-Hsin S. Lee 9C.3 On the Interaction between Power-Aware FPGA CAD Algorithms .........................................701 Julien Lamoureux, Steven J. E. Wilton 9C.4 A Theory of Non-Deterministic Networks ...................................................................................709 Alan Mishchenko, Robert K. Bray ton Session 9Đ Graph Algorithmic Approaches to EDA Problems Moderators: Dwight D. Hill - Synopsys, Inc., Montain View, С А Igor L. Markov - Univ. of Michigan, Ann Arbor, MI 9D.1 Stable Multiway Circuit Partitioning for ECO ...........................................................................718 Yongseok Cheon, Seokjin Lee, Martin D. F. Wong 9D.2 Multi-Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization .................................................................................................726 Navaratnasothie Selvakkumaran, George Karypis 9D.3 An Algorithmic Approach for Generic Parallel Adders .............................................................734 Jianhua Liu, Shuo Zhou, Haikun Zhu, Chung-Kuan Cheng 9D.4 FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits ....................................741 Lei Yang, C.-J. Richard Shi Session 10A Parametric Considerations in Test Schemes Moderators: Andre Ivanov - Univ. of British Columbia, Vancouver, Canada Kwang-Ting (Tim) Cheng - Univ. of California, Santa Barbara, CA 10A.1 Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis .............................................................................................748 Abhishek Singh, Jitin Tharian, Jim P ¡usque!lie xxvii 10А.2 Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage .....................754 Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma 10A.3 Static Verification of Test Vectors for IR Drop Failure .............................................................760 Aman A. Kokrady, С. Р. Ravikumar 10A.4 ATPG for Noise-Induced Switch Failures in Domino Logic ......................................................765 Rahul Kundu, Ronald D . (Shawn) Blanton Session 10B Power-Grid and Substrate Analysis Moderators: Kenneth L. Shepard - Columbia Univ., New York, NY David Blaauw - Univ. of Michigan, Ann Arbor, MI 10B.1 Statistical Verification of Power Grids Considering Process-Induced Leakage Current Variations .......................................................................................................................................770 ImadA. Ferzli, F arid N. Najm 10B.2 A Methodology for the Computation of an Upper Bound on Noise Current Spectrum of CMOS Switching Activity .........................................................................................................778 Alessandra Nardi, Haibo Zeng, Joshua L. Garrett, Luca Daniel, Alberto L. Sangiovanni- Vincentelli 10B.3 SuPREME : Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation .......................................................................................................................................786 Tsung Hao Chen, Clement Luk, Charlie Chung-Ping Chen 10B.4 SILCA: Fast-Yet-Accurate Time-Domain Simulation of VLSI Circuits with Strong Parasitic Coupling Effects .............................................................................................................793 Zhao Li, C.-J. Richard Shi Session IOC Hot Topics in Logic Synthesis Moderators: Michel Berkelaar - Magma Design Automation, Eindhoven, The Netherlands Yusuke Matsunaga - Kyushu Univ., Fukuoka, Japan 10C.1 Multi-Domain Clock Skew Scheduling ........................................................................................801 Kaushik Ravindran, Andreas Kuehlmann, Ellen M. Sentovich 10C.2 Clock Period Minimization of Non-Zero Clock Skew Circuits ..................................................809 Shih-Hsu Huang, Yow-Tyng Nieh 10CJ Minimum-Area Sequential Budgeting for FPGA ........................................................................813 Chao-Yang Yeh, Małgorzata Marek-Sadowska 10C.4 ILP Models for the Synthesis of Asynchronous Control Circuits ..............................................818 Josep Cannona, Jordi Cortadella xxvUi Session IOD Interconnect Modeling Moderators: Nick van der Meijs - Delft Univ. of Tech., Delft, The Netherlands Sharad Kapur - Integrand Software, Hoboken, NJ 10D.1 Passive Synthesis of Compact Frequency-Dependent Interconnect Models via Quadrature Spectral Rules ...........................................................................................................827 Traíanos Yioultsis, Anne Woo, Andreas С Cangellaris 10D.2 Analytic Modeling of Interconnects for Deep Sub-Micron Circuits ..........................................835 Dinesh Pamunuwa, Shauki Elassaad, Hannu Tenhunen 10D.3 A New Surface Integral Formulation for Wideband Impedance Extraction of 3-D Structures .......................................................................................................................................843 Ben Song, Zhenhai Z. Zhu, John D. Rockway, Jacob K. White 10D.4 Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis ................................848 Yu Cao, Xiao-dong Yang, Xuejue Huang, Dennis Sylvester Session HA Test Data Reduction Techniques Moderators: Alex Orailoglu - Univ. of California at San Diego, La Jolla, С А Vivek Chickermane - IBM Corp., Endicott, NY НАЛ On Compacting Test Response Data Containing Unknown Values ..........................................855 Chen Wang, Sudhakar M. Ready, Irith Pomeranz , Janusz Rajski, Jerzy Tyszer 11 A.2 Adjustable Width Linear Combinational Scan Vector Decompression ....................................863 C. V. Krishna, Nur A. Touba 11A.3 On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic ..................................................................................867 Irith Pomeranz, Sudhakar M. Ready Session Η Β Embedded Tutorial: Formal Methods for Dynamic Power Management Moderators: Giovanni De Micheli - Stanford Univ., Stanford CA Massoud Pedram - Univ. of Southern California, Los Angeles, С А 11B.1 Embedded Tutorial: Formal Methods for Dynamic Power Mangement ..................................874 Rajesh K. Gupta, Sandeep K. Shukla, Sandy Irani Session HC Embedded Tutorial: Large-Scale Circuit Placement: Gap and Promise Moderators: William H. Joyner, Jr. - SRC, Research Triangle Park, NC Yoji Kajitani - Univ. of Kitakyushu, Fukuoka, Japan ИС.1 Embedded Tutorial: Large-Scale Circuit Placement: Gap and Promise ..................................883 Jason Cong, Tim Kong, Joseph R. Shinnerl, Min Xie, Xin Yuan 11C.2 Embedded Tutorial: Multi-Million Gate FPGA Physical Design Challenges ...........................891 Maogang Wang, Abhishek Ranjan, Salii Raje xxix Session HD Statistical Static Timing - II Moderators: Nagib Z. Hakim - Intel Corp., Santa Clara, CA Sani R. Nassif- IBM Corp., Austin, TX 1 1D.1 Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations .........900 Aseem Agarwal, David Blaauw, Vladimir Zolotov 11D.2 A Statistical Gate-Delay Model Considering Intra-Gate Variability ........................................908 Kenichi Okada, Kento Yamaoka, Hidetoshi Onodera 1 1D.3 Statistical Clock Skew Analysis Considering Intra-Die Process Variation ...............................914 Aseem Agarwal, David Blaauw, Vladimir Zolotov xxx
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spelling	International Conference on Computer Aided Design (Institute of Electrical and Electronics Engineers) 2003 San José, Calif. Verfasser (DE-588)10073718-3 aut International Conference on Computer Aided Design November 9 - 13, 2003, Doubletree Hotel, San Jose, CA ; [IEEE ACM digest of technical papers] IEEE/ACM International Conference on Computer Aided Design, ICCAD 2003 ICCAD 2003 IEEE ACM digest of technical papers Los Alamitos, Calif. [u.a.] IEEE [u.a.] 2003 txt rdacontent n rdamedia nc rdacarrier CAD (DE-588)4069794-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 2002 Los Alamitos Calif. gnd-content (DE-588)1071861417 Konferenzschrift 2002 San Jose Calif. gnd-content CAD (DE-588)4069794-0 s DE-604 Institute of Electrical and Electronics Engineers Sonstige (DE-588)1692-5 oth Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=010633546&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis
spellingShingle	International Conference on Computer Aided Design November 9 - 13, 2003, Doubletree Hotel, San Jose, CA ; [IEEE ACM digest of technical papers] CAD (DE-588)4069794-0 gnd
subject_GND	(DE-588)4069794-0 (DE-588)1071861417
title	International Conference on Computer Aided Design November 9 - 13, 2003, Doubletree Hotel, San Jose, CA ; [IEEE ACM digest of technical papers]
title_alt	ICCAD 2003 IEEE ACM digest of technical papers
title_auth	International Conference on Computer Aided Design November 9 - 13, 2003, Doubletree Hotel, San Jose, CA ; [IEEE ACM digest of technical papers]
title_exact_search	International Conference on Computer Aided Design November 9 - 13, 2003, Doubletree Hotel, San Jose, CA ; [IEEE ACM digest of technical papers]
title_full	International Conference on Computer Aided Design November 9 - 13, 2003, Doubletree Hotel, San Jose, CA ; [IEEE ACM digest of technical papers] IEEE/ACM International Conference on Computer Aided Design, ICCAD 2003
title_fullStr	International Conference on Computer Aided Design November 9 - 13, 2003, Doubletree Hotel, San Jose, CA ; [IEEE ACM digest of technical papers] IEEE/ACM International Conference on Computer Aided Design, ICCAD 2003
title_full_unstemmed	International Conference on Computer Aided Design November 9 - 13, 2003, Doubletree Hotel, San Jose, CA ; [IEEE ACM digest of technical papers] IEEE/ACM International Conference on Computer Aided Design, ICCAD 2003
title_short	International Conference on Computer Aided Design
title_sort	international conference on computer aided design november 9 13 2003 doubletree hotel san jose ca ieee acm digest of technical papers
title_sub	November 9 - 13, 2003, Doubletree Hotel, San Jose, CA ; [IEEE ACM digest of technical papers]
topic	CAD (DE-588)4069794-0 gnd
topic_facet	CAD Konferenzschrift 2002 Los Alamitos Calif. Konferenzschrift 2002 San Jose Calif.
url	http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=010633546&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
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