Correct hardware design and verification methods: 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003 : proceedings
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| Format: | Conference Proceeding Book |
|---|---|
| Language: | English |
| Published: |
Berlin u.a.
Springer
2003
|
| Series: | Lecture notes in computer science
2860 |
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Item Description: | Includes bibliographical references and index |
| Physical Description: | XII, 426 S. |
| ISBN: | 354020363X |
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| 245 | 1 | 0 | |a Correct hardware design and verification methods |b 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003 : proceedings |c Daniel Geist, Enrico Tronci, (Eds.) |
| 264 | 1 | |a Berlin u.a. |b Springer |c 2003 | |
| 300 | |a XII, 426 S. | ||
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| 490 | 1 | |a Lecture notes in computer science |v 2860 | |
| 500 | |a Includes bibliographical references and index | ||
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Record in the Search Index
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| adam_text |
TABLE
OF
CONTENTS
INVITED
TALKS
WHAT
IS
BEYOND
THE
RTL
HORIZON
FOR
MICROPROCESSOR
AND
SYSTEM
DESIGN?
.
1
WOLFGANG
ROESNER
THE
CHARM
E
OF
ABSTRACT
ENTITIES
.
2
FABIO
SOMENZI
TUTORIAL
THE
PSL/SUGAR
SPECIFICATION
LANGUAGE
A
LANGUAGE
FOR
ALL
SEASONS
.
3
DANIEL
GEIST
SOFTWARE
VERIFICATION
FINDING
REGULARITY:
DESCRIBING
AND
ANALYSING
CIRCUITS
THAT
ARE
NOT
QUITE
REGULAR
.
4
MARY
SHEERAN
PREDICATE
ABSTRACTION
WITH
MINIMUM
PREDICATES
.
19
SAGAR
CHAKI,
EDMUND
CLARKE,
ALEX
GROCE,
OFER
STRICHMAN
EFFICIENT
SYMBOLIC
MODEL
CHECKING
OF
SOFTWARE
USING
PARTIAL
DISJUNCTIVE
PARTITIONING
.
35
SHARON
BARNER,
ISHAI
RABINOVITZ
PROCESSOR
VERIFICATION
INSTANTIATING
UNINTERPRETED
FUNCTIONAL
UNITS
AND
MEMORY
SYSTEM:
FUNCTIONAL
VERIFICATION
OF
THE
VAMP
.
51
SVEN
BEYER,
CHRIS
JACOBI,
DANIEL
KRONING,
DIRK
LEINENBACH,
WOLFGANG
J.
PAUL
A
HAZARDS-BASED
CORRECTNESS
STATEMENT
FOR
PIPELINED
CIRCUITS
.
66
MARK
D.
AAGAARD
ANALYZING
THE
INTEL
ITANIUM
MEMORY
ORDERING
RULES
USING
LOGIC
PROGRAMMING
AND
SAT
.
81
YUE
YANG,
GANESH
GOPALAKRISHNAN,
GARY
LINDSTROM,
KONRAD
SLIND
X
TABLE
OF
CONTENTS
AUTOMATA
BASED
METHODS
ON
COMPLEMENTING
NONDETERMINISTIC
BIICHI
AUTOMATA
.
96
SANKAR
GURUMURTHY,
OMA
KUPFERMAN,
FABIO
SOMENZI,
MOSHE
Y.
VARDI
COVERAGE
METRICS
FOR
FORMAL
VERIFICATION
.
ILL
HANA
CHOCKIER,
OMA
KUPFERMAN,
MOSHE
Y.
VARDI
"
MORE
DETERMINISTIC
"
VS.
"
SMALLER
"
BIICHI
AUTOMATA
FOR
EFFICIENT
LTL
MODEL
CHECKING
.
126
ROBERTO
SEBASTIANI,
STEFANO
TONETTA
SHORT
PAPERS
1
AN
OPTIMIZED
SYMBOLIC
BOUNDED
MODEL
CHECKING
ENGINE
.
141
RACHEL
TZOREF,
MARK
MATUSEVICH,
ELI
BERGER,
ILAN
BEER
CONSTRAINED
SYMBOLIC
SIMULATION
WITH
MATHEMATICA
AND
ACL2
.
150
GHIATH
AL
SAMMANE,
DIANA
TOMA,
JULIEN
SCHMALTZ,
PIERRE
OSTIER,
DOMINIQUE
BORRIONE
SEMI-FORMAL
VERIFICATION
OF
MEMORY
SYSTEMS
BY
SYMBOLIC
SIMULATION
.
158
HUSAM
ABU-HAIMED,
SERGEY
BEREZIN,
DAVID
L.
DILL
CTL
MAY
BE
AMBIGUOUS
WHEN
MODEL
CHECKING
MOORE
MACHINES
.
164
CEDRIC
ROUX,
EMMANUELLE
ENCRENAZ
SPECIFICATION
METHODS
REASONING
ABOUT
GSTE
ASSERTION
GRAPHS
.
170
ALAN
J.
HU,
JEREMY
CASAS,
JIN
YANG
TOWARDS
DIAGRAMMABILITY
AND
EFFICIENCY
IN
EVENT
SEQUENCE
LANGUAGES
.
185
KATHI
FISLER
EXECUTING
THE
FORMAL
SEMANTICS
OF
THE
ACCELLERA
PROPERTY
SPECIFICATION
LANGUAGE
BY
MECHANISED
THEOREM
PROVING
.
200
MIKE
GORDON,
JOE
HURD,
KONRAD
SLIND
PROTOCOL
VERIFICATION
ON
COMBINING
SYMMETRY
REDUCTION
AND
SYMBOLIC
REPRESENTATION
FOR
EFFICIENT
MODEL
CHECKING
.
216
E.
ALLEN
EMERSON,
THOMAS
WAHL
TABLE
OF
CONTENTS
XI
ON
THE
CORRECTNESS
OF
AN
INTRUSION-TOLERANT
GROUP
COMMUNICATION
PROTOCOL
.
231
MOHAMED
LAYOUNI,
JOZEF
HOOMAN,
SOFIENE
TAHAR
EXACT
AND
EFFICIENT
VERIFICATION
OF
PARAMETERIZED
CACHE
COHERENCE
PROTOCOLS
.
247
E.
ALLEN
EMERSON,
VINEET
KAHLON
SHORT
PAPERS
2
DESIGN
AND
IMPLEMENTATION
OF
AN
ABSTRACT
INTERPRETER
FOR
VHDL
.
263
CHARLES
HYMANS
A
PROGRAMMING
LANGUAGE
BASED
ANALYSIS
OF
OPERAND
FORWARDING
.
270
LENNART
BERINGER
INTEGRATING
RAM
AND
DISK
BASED
VERIFICATION
WITHIN
THE
MURTP
VERIFIER
.
277
GIUSEPPE
DELLA
PENNA,
BENEDETTO
INTRIGILA,
IGOR
MELATTI,
ENRICO
TROND,
MARISA
VENTURINI
ZILLI
DESIGN
AND
VERIFICATION
OF
CORECONNECTTM
IP
USING
ESTEREL
.
283
SATNAM
SINGH
THEOREM
PROVING
INDUCTIVE
ASSERTIONS
AND
OPERATIONAL
SEMANTICS
.
289
J
STROTHER
MOORE
A
COMPOSITIONAL
THEORY
OF
REFINEMENT
FOR
BRANCHING
TIME
.
304
PANAGIOTIS
MANOLIOS
LINEAR
AND
NONLINEAR
ARITHMETIC
IN
ACL2
.
319
WARREN
A.
HUNT,
JR.,
ROBERT
BELLARMINE
KRUG,
J
MOORE
BOUNDED
MODEL
CHECKING
EFFICIENT
DISTRIBUTED
SAT
AND
SAT-BASED
DISTRIBUTED
BOUNDED
MODEL
CHECKING
.
334
MALAY
K
GANAI,
AARTI
GUPTA,
ZIJIANG
YANG,
PRANAV
ASHAR
CONVERGENCE
TESTING
IN
TERM-LEVEL
BOUNDED
MODEL
CHECKING
.
348
RANDAL
E.
BRYANT,
SHUVENDU
K.
LAHIRI,
SANJIT
A.
SESHIA
THE
ROBDD
SIZE
OF
SIMPLE
CNF
FORMULAS
.
363
MICHAEL
LANGBERG,
AMIR
PNUELI,
YOAV
RODEH
XII
TABLE
OF
CONTENTS
MODEL
CHECKING
AND
APPLICATION
EFFICIENT
HYBRID
REACHABILITY
ANALYSIS
FOR
ASYNCHRONOUS
CONCURRENT
SYSTEMS
.
378
ENRIC
PASTOR,
MARCO
A.
PENA
FINITE
HORIZON
ANALYSIS
OF
MARKOV
CHAINS
WITH
THE
MUR
VERIFIER
.
394
GIUSEPPE
DELLA
PENNA,
BENEDETTO
INTRIGILA,
IGOR
MELATTI,
ENRICO
TROND,
MARISA
VENTURINI
ZILLI
IMPROVED
SYMBOLIC
VERIFICATION
USING
PARTITIONING
TECHNIQUES
.
410
SUBRAMANIAN
IYER,
DEBASHIS
SAHOO,
CHRISTIAN
STANGIER,
AMIT
NARAYAN,
JAWAHAR
JAIN
AUTHOR
INDEX
.
425 |
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| building | Verbundindex |
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| classification_rvk | SS 4800 |
| classification_tum | DAT 190f |
| ctrlnum | (OCoLC)53170443 (DE-599)BVBBV017599461 |
| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Conference Proceeding Book |
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| genre | (DE-588)1071861417 Konferenzschrift 2003 L'Aquila gnd-content |
| genre_facet | Konferenzschrift 2003 L'Aquila |
| id | DE-604.BV017599461 |
| illustrated | Not Illustrated |
| indexdate | 2025-01-10T15:07:32Z |
| institution | BVB |
| institution_GND | (DE-588)10066679-6 |
| isbn | 354020363X |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-010588824 |
| oclc_num | 53170443 |
| open_access_boolean | |
| owner | DE-384 DE-91G DE-BY-TUM DE-706 |
| owner_facet | DE-384 DE-91G DE-BY-TUM DE-706 |
| physical | XII, 426 S. |
| publishDate | 2003 |
| publishDateSearch | 2003 |
| publishDateSort | 2003 |
| publisher | Springer |
| record_format | marc |
| series | Lecture notes in computer science |
| series2 | Lecture notes in computer science |
| spelling | Correct hardware design and verification methods 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003 : proceedings Daniel Geist, Enrico Tronci, (Eds.) Berlin u.a. Springer 2003 XII, 426 S. txt rdacontent n rdamedia nc rdacarrier Lecture notes in computer science 2860 Includes bibliographical references and index Circuit intégré à très grande échelle rasuqam Circuit intégré rasuqam Circuits intégrés - Vérification - Congrès Circuits intégrés à très grande échelle - Conception assistée par ordinateur - Congrès Conception assistée par ordinateur rasuqam Hardware gtt Model-checking (Informatique) rasuqam Vormgeving gtt Vérification de logiciels rasuqam Integrated circuits Verification Congresses Integrated circuits Very large scale integration Computer-aided design Congresses Hardwareverifikation (DE-588)4214982-4 gnd rswk-swf Formale Methode (DE-588)4333722-3 gnd rswk-swf System-on-Chip (DE-588)4740357-3 gnd rswk-swf Model Checking (DE-588)4434799-6 gnd rswk-swf Entwurfssprache (DE-588)4295335-2 gnd rswk-swf Hardwareentwurf (DE-588)4159103-3 gnd rswk-swf Entwurfsautomation (DE-588)4312536-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 2003 L'Aquila gnd-content Hardwareentwurf (DE-588)4159103-3 s Formale Methode (DE-588)4333722-3 s DE-604 Hardwareverifikation (DE-588)4214982-4 s Model Checking (DE-588)4434799-6 s System-on-Chip (DE-588)4740357-3 s Entwurfsautomation (DE-588)4312536-0 s Entwurfssprache (DE-588)4295335-2 s Geist, Daniel Sonstige oth CHARME 12 2003 L'Aquila Sonstige (DE-588)10066679-6 oth Lecture notes in computer science 2860 (DE-604)BV000000607 2860 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=010588824&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Correct hardware design and verification methods 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003 : proceedings Lecture notes in computer science Circuit intégré à très grande échelle rasuqam Circuit intégré rasuqam Circuits intégrés - Vérification - Congrès Circuits intégrés à très grande échelle - Conception assistée par ordinateur - Congrès Conception assistée par ordinateur rasuqam Hardware gtt Model-checking (Informatique) rasuqam Vormgeving gtt Vérification de logiciels rasuqam Integrated circuits Verification Congresses Integrated circuits Very large scale integration Computer-aided design Congresses Hardwareverifikation (DE-588)4214982-4 gnd Formale Methode (DE-588)4333722-3 gnd System-on-Chip (DE-588)4740357-3 gnd Model Checking (DE-588)4434799-6 gnd Entwurfssprache (DE-588)4295335-2 gnd Hardwareentwurf (DE-588)4159103-3 gnd Entwurfsautomation (DE-588)4312536-0 gnd |
| subject_GND | (DE-588)4214982-4 (DE-588)4333722-3 (DE-588)4740357-3 (DE-588)4434799-6 (DE-588)4295335-2 (DE-588)4159103-3 (DE-588)4312536-0 (DE-588)1071861417 |
| title | Correct hardware design and verification methods 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003 : proceedings |
| title_auth | Correct hardware design and verification methods 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003 : proceedings |
| title_exact_search | Correct hardware design and verification methods 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003 : proceedings |
| title_full | Correct hardware design and verification methods 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003 : proceedings Daniel Geist, Enrico Tronci, (Eds.) |
| title_fullStr | Correct hardware design and verification methods 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003 : proceedings Daniel Geist, Enrico Tronci, (Eds.) |
| title_full_unstemmed | Correct hardware design and verification methods 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003 : proceedings Daniel Geist, Enrico Tronci, (Eds.) |
| title_short | Correct hardware design and verification methods |
| title_sort | correct hardware design and verification methods 12th ifip wg 10 5 advanced research working conference charme 2003 l aquila italy october 21 24 2003 proceedings |
| title_sub | 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003 : proceedings |
| topic | Circuit intégré à très grande échelle rasuqam Circuit intégré rasuqam Circuits intégrés - Vérification - Congrès Circuits intégrés à très grande échelle - Conception assistée par ordinateur - Congrès Conception assistée par ordinateur rasuqam Hardware gtt Model-checking (Informatique) rasuqam Vormgeving gtt Vérification de logiciels rasuqam Integrated circuits Verification Congresses Integrated circuits Very large scale integration Computer-aided design Congresses Hardwareverifikation (DE-588)4214982-4 gnd Formale Methode (DE-588)4333722-3 gnd System-on-Chip (DE-588)4740357-3 gnd Model Checking (DE-588)4434799-6 gnd Entwurfssprache (DE-588)4295335-2 gnd Hardwareentwurf (DE-588)4159103-3 gnd Entwurfsautomation (DE-588)4312536-0 gnd |
| topic_facet | Circuit intégré à très grande échelle Circuit intégré Circuits intégrés - Vérification - Congrès Circuits intégrés à très grande échelle - Conception assistée par ordinateur - Congrès Conception assistée par ordinateur Hardware Model-checking (Informatique) Vormgeving Vérification de logiciels Integrated circuits Verification Congresses Integrated circuits Very large scale integration Computer-aided design Congresses Hardwareverifikation Formale Methode System-on-Chip Model Checking Entwurfssprache Hardwareentwurf Entwurfsautomation Konferenzschrift 2003 L'Aquila |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=010588824&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV000000607 |
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