Proceedings 2003: Anaheim Convention Center, Anaheim, CA, June 2 - 6, 2003
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| Format: | Conference Proceeding Book |
| Language: | English |
| Published: |
New York, NY
ACM Press
2003
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| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Physical Description: | XXXIV, 981 S. Ill., graph. Darst. |
| ISBN: | 1581136889 |
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| 111 | 2 | |a Design Automation Conference (Association for Computing Machinery) |n 40 |d 2003 |c Anaheim, Calif. |j Verfasser |0 (DE-588)10066218-3 |4 aut | |
| 245 | 1 | 0 | |a Proceedings 2003 |b Anaheim Convention Center, Anaheim, CA, June 2 - 6, 2003 |c Design Automation Conference, 40th DAC Conference |
| 246 | 1 | 3 | |a DAC 2003 |
| 246 | 1 | 3 | |a Proceedings of the 40th Design Automation Conference |
| 246 | 1 | 3 | |a Proceedings |
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Table
of
Contents
General Chair's Welcome
.
і
Executive Committee
.xix
Technical Program Committee
.xxi
Panel Sub-Committee
.xxiii
Student Design Contest Judges
.xxiv
Exhibitor Liaison Committee
.xxiv
Opening Keynote Address
-
Sir Robin Saxby
.xxv
Thursday Keynote Address
-
Alberto L. Sangiovanni-Vincentelli
.xvii
Marie R.
Pistilli
Women in EDA Achievement Award
.xxix
Phil Kaufman Award
.xxix
2003
IEEE Fellows
.xxix
IEEE CAS Society Awards
.xxix
Mac Van
Valkenburg
Award
.xxix
Emanuel
R.
Piore
Award
.xxix
Guillemin-Cauer Award
.xxix
CAD Transactions Best Paper Award
.xxx
VLSI Transactions Best Paper Award
.xxx
ACM/SIGDA Distinguished Service Award
.xxx
2002
DAC
P.O.
Pistilli
Undergraduate Scholarships
.xxx
Design Automation Conference Graduate Scholarships
.xxxi
DAC
2003
Student Design Contest Winners
.xxxii
Reviewers
.xxxiii
2004
Call for Papers
.xxxv
SESSION
1 :
Special Session
—
Real Challenges and Solutions
for Validating System-on-Chip
Chair:
&
Organizer: Wolfgang
Rosenstiel
(University of Tubingen)
1.1
High Level Formal Verification of Next-Generation Microprocessors
.1
T. Schubert (Intel Corporation)
1.2
Verification Strategy for Integration 3G Baseband SoC
.7
Y. Mathys, A. Châtelain
(Motorola)
1.3
Improvements in Functional Simulation Addressing Challenges
in Large, Distributed Industry Projects
.11
■
K.-D. Schubert (IBM Corporation)
SESSION
2:
Panel
—
Reshaping EDA for Power
.15
Chair: Jan Rabaey (University of California at Berkeley)
Organizers: Dennis Sylvester, David Blaauw (University of Michigan)
Panelists: K. Bernstein (IBM Corporation), J. Frenkil (Sequence Design Incorporated),
M. Horowitz (Stanford University), W.
Nebel
(Oldenburg University),
T. Sakurai (University of Tokyo), A. Yang (Apache Design Solutions)
in
SESSION
3:
Design
for Man
ufactu
rabi lity
and Global
Routing
Chair: Martin
Wong (University of
Illinois)
Organizers: Charles
J. Alpert,
Dennis Sylvester, Raymond Nijssen
3.1
A Cost-Driven Lithographic Correction Methodology Based
on Off-the-Shelf Sizing Tools
.
16
P. Gupta, A. B. Kahng (University of California at San Diego),
D. Sylvester, J. Yang, (University of Michigan at Ann Arbor)
3.2
Performance-Impact Limited Area Fill Synthesis
22
Y. Chen (University of California at Los Angeles),
P. Gupta, A. B. Kahng (Univiversity of California at San Diego)
3.3
Improved Global Routing through Congestion Estimation
.28
R. T. Hadsell, P. H. Madden (State University of New York)
3.4
Microarchitecture
Evaluation With Physical Planning
.32
J. Cong, A. Jagannathan, G. Reinman, M. Romesis (University of California at Los Angeles)
SESSION
4:
Design Analysis Techniques
Chair: Michael Kishinevsky (Intel Corporation)
Organizers: Ahmed A. Jerraya, Steven Haynal
4.1
Energy-Aware Design Techniques for Differential Power Analysis Protection
.36
L.
Benini
(Universita
di
Bologna),
A. Macii,
E.
Macii
(Politecnico di Torino),
E. Omerbegovic (BullDASTs.r.l.), M. Poncino (Università di Verona), F. Pro (BullDASTs.r.l.)
4.2
A
Timing-Accurate Modeling and Simulation Environment
for Networked Embedded Systems
.42
F.
Fummi (Università di
Verona), P.
Gallo
(Telecom Italia Laboratory),
S. Martini, G. Perbellini, M. Poncino
(Università di
Verona),
F. Ricciato
(Telecom Italia Laboratory)
4.3
Application of Design Patterns for Hardware Design
.48
R. Damaševicius,
G. Majauskas,
V.
Štuikys
(Kaunas University of Technology)
SESSION
5:
Embedded Hardware Design Case Studies
Chair: Chris Rowen (Tensilica, Incorporated)
Organizers: Grant E. Martin, Kurt Keutzer,
Pai
Chou
5.1
A Fully-Programmable Memory Management System Optimizing
Queue Handling at
Multi
Gigabit Rates
.54
G. Komaros, I. Papaefstathiou, A. Nikologiannis,
N.
Zervos
(Ellemedia
Technologies)
5.2
Design Flow for HW/SW Acceleration Transparency
in the ThumbPod Secure Embedded System
.60
D. Hwang, P. Schaumont, Y. Fan, A. Hodjat, B.-C. Lai, K. Sakiyama,
S. Yang, I. Verbauwhede (University of California at Los Angeles)
5.3
Design Techniques for Sensor Appliances: Foundations
and Light Compass Case Study
.66
J. L. Wong, S. Megerian, M. Potkonjak (University of California at Los Angeles)
SESSION
6:
Spec/a/ Session
—
Emerging Design and Tool Challenges
in RF and Wireless Applications
Chair Georges Gielen
(Katholieke
University)
Organizer. Limor Fix
6.1
Seamless Multi-Radio Integration Challenges
U.
Barkái
(Intel Corporation)
6.2
RF Front End Application and Technology Trends
. 73
P. W. Hooijmans (Philips Research Laboratories)
iv
6.3
4G
Terminals:
How are We Going to Design Them?
.79
J. Craninckx, S. Donnay (IMEC)
6.4
New Techniques for Non-Linear Behavioral Modeling of Miocrowave/RF ICs
from Simulation and Nonlinear Microwave Measurements
.85
D. E. Root, J. Wood (Agilent Technologies),
N.
Tufillaro (Agilent Laboratories)
SESSION
7:
Panel
—
COT-Customer Owned Trouble
.91
Chair: Bob
Dahlberg
(Reshape Incorporated)
Organizers: Shishpal Rawat (Intel Corporation)
&
Jen Bernier (Armstrong Kendall)
Panelists: G.
Głoski
(eSilicon Corporation), A. Khan, (Cadence Design Systems, Incorporated),
K.
Patel
(Azanda Network Devices), P. Ruddy (Cisco Systems),
N.
Sherwani (Intel Corporation),
R. Vasishta (LSI Logic Corporation)
SESSION
8:
Power Grid Analysis and Optimization
Chair:
Sani Nassif
(IBM Corporation)
Organizers: Jen Bernier, Shishpal Rawat
8.1
Random Walks in a Supply Network
.93
H. Qian (Unviersity of Minnesota), S. R. Nassif (IBMAustin Research Laboratories),
S. S. Sapatnekar (University of Minnesota)
8.2
A Static Pattern-Independent Technique for Power Grid Voltage
Integrity Verification
.99
D. Kouroussis, F.
N.
Najm (University of Toronto)
8.3
Power Network Analysis Using an Adaptive Algebraic Multigrid Approach
.105
Z. Zhu, B. Yao, C.-K. Cheng (University of California at San Diego)
8.4
Power Grid Reduction Based on Algebraic Multigrid Principles
.109
H.
Su, E.
Acar,
S. R. Nassif (IBM
Austin
Research Laboratories)
8.5
On-chip Power
Supply
Network
Optimization using Multigrid-based
Technique.
.113
K. Wang, M. Marek-Sadowska
(University of California at Santa Barbara)
SESSION
9:
Low-Power Embedded System Design
Chair: Rajesh K. Gupta (University of California at San Diego)
Organizers: Diederik Verkest, Taewhan Kim
9.1
Scalable Modeling and Optimization of Mode Transitions
Based on Decoupled Power Management Architecture
.119
D. Li, Q. Xie, P.
H. Chou
(University of California at Irvine)
9.2
Optimal Voltage Allocation Techniques for Dynamically
Variable Voltage Processors
.125
W.-C. Kwon (Samsung Electronics Company), T. Kim (Korea Advanced Institute of Science
&
Technology)
9.3
Energy Reduction Techniques for Multimedia Applications
with Tolerance to Deadline Misses
.131
S. Hua, G.
Qu,
S. S.
Bhattacharyya (University of
Marylandot
College Park)
9.4
Xtream-Fit: An Energy-Delay Efficient Data Memory Subsystem
for Embedded Media Processing
.137
A. Ramachandran,
M. F.
Jacome (University of Texas at Austin)
SESSION
10:
Cyclic and Non-Cyclic Combinational Circuit Synthesis
Chair: Victor
Kravets
(IBM Corporation)
Organizers:
Marek Perkowski,
Soha Hassoun
10.1
A New Enhanced Constructive Decomposition and Mapping Algorithm
.143
A. Mishchenko (University of California at Berkeley), X. Wang, T.
Kam
(Intel Corporation)
10.2
Large-Scale SOP Minimization Using Decomposition
and Functional Properties
.
149
A. Mishchenko (University of California at Berkeley), T. Sasao (Kyushu Institute of Technology)
10.3
Generalized Cofactoring for Logic Function Evaluation
155
Y. Jiang, S.
Matic,
R. K.
Brayton (University of California at Berkeley)
10.4
Making Cyclic Circuits Acyclic
.: 159
S. A. Edwards (Columbia University)
10.5
The Synthesis of Cyclic Combinational Circuits
.163
M. D.
Riedel, J.
Brack (California Institute of Technology)
SESSION
11:
Managing Leakage Power
Chair: Siva
Narendra
(Intel Corporation)
Organizers:
Marek
Perkowski,
Soha
Hassoun
11.1
Accurate Estimation of Total Leakage Current in Scaled CMOS
Logic Circuits Based on Compact Current Modeling
.169
S. Mukhopadhyay, A. Raychowdhury, K. Roy (Purdue University)
11.2
Analysis and Minimization Techniques for Total Leakage
Considering Gate Oxide Leakage
.175
D. Lee, W. Kwong, D. Blaauw, D. Sylvester (University of Michigan)
11.3
Distributed Sleep Transistor Network for Power Reduction
.181
C. Long (University of Wisconsin at Madison), L. He (University of California at Los Angeles)
11.4
Implications of Technology Scaling on Leakage Reduction Techniques
.187
Y-F. Tsai (Penn State University),
D. Duarte
(Intel Corporation),
N.
Vijaykrishnan, M. J.
Irwin (Penn
State University)
11.5
Static Leakage Reduction through Simultaneous Threshold
Voltage and State Assignment
.191
D. Lee, D. Blaauw (University of Michigan)
SESSION
12:
Panel
—
Emerging Markets: Design Goes Global
.195
Chair. C.-F. Chan (Synopsys, Incorporated)
Organizers: Deirdre Hanford,
Jian Yue
Pan,
Narendra Shenoy
Panelists: M. Mehendale (Texas Instruments), A. Vasudevan (Wipro Technologies),
S. Wei (Beijing Datang Telecom Ltd.), Wei-Ping Liu
CEC (Huada
Electronics Design Company, Ltd.)
SESSION
13:
Timing-Oriented Placement
Chair: Ralph Otten (Eindhoven University of Technology)
Organizers: Deirdre Hanford,
Jian Yue
Pan,
Narendra
Shenoy
13.1
Timing Optimization of FPGA Placements by Logic Replication
.196
G. Beraudo, J. Lillis (University of Illinois at Chicago)
13.2
Delay Budgeting in Sequential Circuit with Application on FPGA Placement
.202
C.-Y. Yeh, M. Marek-Sadowska (University of California at Santa Barbara)
13.3
Multilevel Global Placement with Retiming
.208
J. Cong, X. Yuan (University of California at Los Angeles)
13.4
Force Directed Mongrel with Physical Net Constraints
.214
S.-W. Hut (Donga University), T.
Cao,
К.
Rajagopal,
Y.
Parasuram, A. Chowdhary, V. Tiourin
(Intel Corporation), B. Halpin (Syracuse University, Intel Corporation)
vi
SESSION 14: Model Order
Reduction
Chair:
Ying (Frank)
Liu
(IBM Corporation)
Organizers:
C. Y.
Roger
Chen,
Carl Sechen
14.1
Realizable Parasitic Reduction Using Generalized
Υ-Δ
Transformation
.220
Z. Qin (Synopsys, Incorporated), C.-K. Cheng (University of California at San Diego)
14.2
Realizable RLCK Circuit Crunching
.226
С
S.
Amin,
M. H. Chowdhury, Y.
I. Ismail
(Northwestern
University)
14.3
Efficient
Model Order Reduction Including Skin Effect
.232
S.
Mei,
С.
Amin,
Y.
I. Ismail (Northwestern University)
14.4
Model Order Reduction of
Nonuniform
Transmission Lines Using Integrated
Congruence Transform
.238
E. Gad, M. Nakhla
(Carleton
University)
SESSION
15:
Issues in Partitioning
&
Design Space Exploration for Codesign
Chair: Nikil Dutt (University of California at Irvine)
Organizer:
Sachin
S.
Sapatnekar
15.1
Partial Task Assignment of Task Graphs under Heterogeneous Resource
Constraints
.244
R. Szymanek, K. Kuchcinski (Lund University)
15.2
Dynamic Hardware/Software Partitioning: A First Approach
.250
G. Stitt, R. Lysecky, F. Vahid (University of California at Riverside)
15.3
Automatic Application-Specific Instruction-Set Extensions
under
Microarchitectural
Constraints
.256
K. Atasu, L.
Pozzi,
P.
lenne
(Swiss Federal Institute of Technology Lausanne (EPFL))
15.4
Instruction Encoding Synthesis for Architecture Exploration
using Hierarchical Processor Models
.262
A. Nohl, V. Greive, G.
Braun,
A. Hoffmann
(CoWare, Incorporated),
R. Leupers, O. Schliebusch, H. Meyr (Aachen University of Technology (RWTH))
SESSION
16:
Special Session
—
Nano
Technology: Design Implications
and CAD Challenges
Chair: Rolf Ernst (Technical University of Braunsweig)
Organizers: Xiaobo Sharon Hu, Wolfgang
Porod
16.1
Quantum-dot Cellular Automata: Computing by Field Polarization
.268
G. H. Bernstein (University of Notre Dame)
16.2
Recent Advances and Future Prospects in Single-Electronics
.274
C. Wasshuber (Texas Instruments)
16.3
Manipulation and Characterization of Molecular Scale Components
.276
I. Amlani, R. Zhang, J.
Tresek,
L.
Nagahara,
R. K.
Tsui (Motorola)
SESSION
17:
Panel
—
Mixed Signals on Mixed-Signal:
the Right Next Technology
.278
Chair: Rob A.
Rutenbar
(Carnegie Mellon University)
Organizers: James
Spoto,
Rob A.
Rutenbar
Panelists: Raminderpal Singh (IBM Corporation), K. Johnson (Cadence Design Systems, Incorporated),
P. Kempf (Jazz Semiconductor), T.
Meng
(Stanford University, Atheros Communications),
R. Rofougaran (Broadcom), J.
Spoto
(Applied Wave Research)
SESSION 18: Simulation
Coverage and
Generation
for Verification
Chair:
Umberto
Rossi (STMicroelectronics)
Organizers: Hikeung T.
Ma, Shin-ichi Minato
18.1
Coverage-Oriented Verification of
Banias
.280
A. Gluska (Intel Corporation)
18.2
Coverage Directed Test Generation for Functional Verification
using Bayesian Networks
.286
S. Fine, A. Ziv (IBMResearch Laboratory in Haifa)
18.3 Dos
and Don'ts of CTL State Coverage Estimation
.292
N.
Jayakumar, M.
Purandare, F. Somenzi
(University of Colorado at Boulder)
18.4
Constraint Synthesis for Environment Modeling in Functional Verification
.296
J. Yuan, K.
Albin (Mototola
Inc.), A. Aziz (University of Texas at Austin),
С
Pixley (Synopsys, Incorporated)
SESSION
19:
Tool Support for Architectural Decisions in Embedded Systems
Chair: Grant E. Martin (Cadence Design Systems, Incorporated)
Organizers: Grant E. Martin, Kurt Keutzer,
Pai
Chou
19.1
Automatic Communication Refinement for System Level Design
.300
S. Abdi, D. Shin, D. Gajski (University of California at Irvine)
19.2
CoCo: A Hardware/Software Platform for Rapid Prototyping
of Code Compression Technologies
.306
H. Lekatsas, J.
Henkel,
S.
Chakradhar, V. Jakkula, M. Sankaradass
(NEC Laboratories America, Incorporated)
19.3
A Tool for Describing and Evaluating Hierarchical Real-Time
Bus Scheduling Policies
.312
T. Meyerowitz, C. Pinello, A. Sangiovanni-Vincentelli (University of California at Berkeley)
SESSION
20:
New Topics in Logic Synthesis
Chair: Shigeru
Y
amashita (NTT Communication Science Laboratories)
Organizers:
Marek
Perkowski, Steven M. Nowick
20.1
A Transformation Based Algorithm for Reversible Logic Synthesis
.318
D. M. Miller (University of Victoria), D. Maslov,
G. W.
Dueck (University of New Brunswick)
20.2
An Arbitrary Two-qubit Computation in
23
Elementary Gates Or Less
.324
S. S. Bullock, I. L. Markov (University of Michigan at Ann Arbor)
20.3
Verilog HDL, Powered by
PLI: a
Suitable Framework for Describing
and Modeling Asynchronous Circuits at All Levels of Abstraction
.330
A. Saifhashemi, H. Pedram (Amirkabir University of Technology)
20.4
On-Chip Logic Minimization
.334
R. Lysecky (University of California at Riverside),
F. Vahid (University of California at Riverside)
SESSION
21:
Special Session
—
Coping with Variability: The End
of Deterministic Design
Chair. Michael Orshansky (University of California at Berkeley)
Organizer Kurt Keutzer
21.1
Parameter Variations and Impact on Circuits and
Microarchitecture
.338
S.
Borkar,
T.
Kamik,
S.
Narendra,
J. Tschanz, A.
Keshavarzi,
V.
De (Intel Laboratories)
VIH
21.2
Death, Taxes and Failing Chips
.343
С
Visweswariah (IBM Thomas J. Watson Research Center)
21.3
Computation and Refinement of Statistical Bounds on Circuit Delay
.348
A. Agarwal, D. Blaauw (University of Michigan), V. Zolotov (Motorola),
S. Vrudhula (University of Arizona at Tucson)
SESSION
22:
Panel
—
Fast, Cheap and Under Control: The Next
Implementation Fabric
.354
Chair: Abbas El Gamal (Stanford University)
Organizers: John Cohn,, Andrew B. Kahng
Panelists: I. Bolsens (Xilinx, Incorporated), A. Broom (AMI),
С
Hamlin (LSI Logic),
P. Magarshack (STMicroelectronics), Z. Or-Bach (eASIC), L. Pileggi (Carnegie Mellon University)
SESSION
23:
Testbench, Verification and Debugging: Practical Considerations
Chair: Michael Beaver (¡Ready Corporation)
Organizers: Carl Pixley, Rajeev Ranjan
23.1
Using a Formal Specification and a Model Checker to Monitor
and Direct Simulation
.356
S. Tasiran
(Кос
University), Y. Yu (Microsoft Research), B. Batson (Intel Corporation)
23.2
Advanced Techniques for
RTL
Debugging
.362
Y.-C. Hsu, B. Tabbara, Y.-A. Chen, F. Tsai (Novas Software Incorporated)
23.3
Behavioral Consistency of
С
and Verilog Programs Using Bounded
Model Checking
.368
E. Clarke, D. Kroening, K. Yorav (Carnegie Mellon University)
23.4
Re-Use-Centric Architecture for a Fully Accelerated Testbench Environment
.372
R. Henftling, A.
Zinn,
M.
Bauer,
M.
Zambaldi,
W.
Ecker
(Infineon Technologies
AG)
SESSION
24:
Delay and Noise Modeling in the Nanometer Regime
Chair: Vasant Rao (IBM Corporation)
Organizers: Chandu Visweswariah,
Narendra
V Shenoy
24.1
An Effective Capacitance Based Driver Output Model for On-Chip
RLC Interconnects
.376
K. Agarwal, D. Sylvester, D. Blaauw (University of Michigan)
24.2
Delay and Slew Metrics Using the
Lognormal
Distribution
.382
С
J. Alpert, F. Liu,
С
Kashyap, A. Devgan (IBM Corporation)
24.3
Blade
&
Razor: Cell and Interconnet Delay Analysis
Using Current-Based Models
.386
J.
F. Croix
(Silicon Metrics Corporation), D. F. Wong (University of Illinois at Urbana-Champaign)
24.4
Non-Iterative Switching Window Computation for Delay-Noise
.390
B. Thudi, D. Blaauw (University of Michigan)
SESSION
25:
Modeling Issues in the Design of Embedded Systems
Wolfgang
Rosenstiel
(University of Tubingen)
Organizers: Annette Reutter, Donatella Sciuto
25.1
Architecture-Level Performance Evaluation of Component-Based
Embedded Systems
.396
J. T. Russell,
M. F.
Jacome (University of Texas at Austin)
25.2
An IDF-based Trace Transformation Method for Communication Refinement
.402
A. D. Pimentel, C. Erbas (University of Amsterdam)
ix
25.3
Schedulers as Model-Based Design Elements
in Programmable Heterogeneous Multiprocessors
408
J. M. Paul, A. Bobrek, J. E. Nelson, J. J.
Pieper,
D. E.
Thomas (Carnegie Mellon University)
25.4
A Complexity Effective Communication Model for Behavioral Modeling
of Signal Processing Applications
.412
S. Kiran, M.
N.
Jayram (Indian Institute of Technology Delhi),
P. Rao, S. K.
Nandy
(Indian Institute of Science)
SESSION
26:
Special Session
—
How Application/Technology Evolutions Will
Shape Classical EDA?
Chair
&
Organizer: Ahmed Jerraya
(TIMA
Laboratory)
26.1
Leading-Edge and Future Design Challenges-Is the Classical EDA Ready?
416
G. Spirakis (Intel Corporation)
26.2
How to Make Efficient Communication, Collaboration,
and Optimization from System to Chip
.417
# A. Matsuzawa (Tokyo Institute of Technology)
26.3
System-on-Chip Beyond the Nanometer Wall
.419
P. Magarshack, P. G.
Paulin (STMicroelectronics)
26.4
Panel Discussion of Special Session
26:
Platform Based Design vs. Network on Chip
SESSION
27:
SAT and BDD Algorithms for Verification Tools
Chair: Robert
Damiano (Synopsys,
Incorporated)
Organizers: Carl Pixley, Hikeung T.
Ma, Shin-ichi Minato
27.1
A Hybrid SAT-Based Decision Procedure for Separation Logic
with Uninterpreted Functions
.425
S. A. Seshia, S. K. Lahiri, R. E. Bryant (Carnegie Mellon University)
П.2
Symbolic Representation with Ordered Function Templates
.431
A. Goel (Carnegie Mellon University), G. Hasteer (Innologic Systems),
R. E. Bryant (Carnegie Mellon University)
27.3
A Signal Correlation Guided ATPG Solver and Its Applications
for Solving Difficult Industrial Cases
.436
F. Lu, L.-C. Wang, K.-T.
Cheng (University of California at Santa Barbara),
J. Moondanos,
Z. Hanna
(Intel Corporation)
27.4
Solving the Latch Mapping Problem in an Industrial Setting
.442
K. Ng (University of British Columbia),
M. R.
Prasad,
R. Mukherjee, J.
Jain (Fujitsu Laboratories of America)
SESSION
28:
Elements of Functional and Performance Analysis
Chair: Rolf Emst (Technical University of Braunschweig)
Organizers: Annette Reutter,
Margarida Jacome
28.1
Static Analysis of Transaction-Level Models
.448
G.
Agosta,
F.
Bruschi,
D.
Sciuto (Politecnico di Milano
Italy)
28.2
Enabling Scheduling Analysis of Heterogeneous Systems
with Multi-Rate Data Dependencies and Rate Intervals
.454
M. Jersak, R.
Ernst
(Technical University of Braunschweig)
28.3
Automatic
Trace Analysis for Logic of Constraints
.460
X. Chen, H. Hsieh (Uniersity of California at Riverside),
F. Balarin, Y. Watanabe (Cadence Berkeley Laboratories)
28.4
Accurate Timing Analysis by Modeling Caches, Speculation
and Their Interaction
.466
X. Li, T.
Mitra,
A. Roychoudhury (National University of Singapore)
SESSION
29:
Nonlinear Model Order Reduction
Chair:
Luca
Daniel (Massachusetts Institute of Technology)
Organizer: Kartikeya Mayaram
29.1
NORM: Compact Model Order Reduction of Weakly Nonlinear Systems
.472
P. Li, L. T. Pileggi (Carnegie Mellon University)
29.2
Analog and RF Circuit Macromodels for System-Level Analysis
.478
X. Li, P. Li, Y. Xu, L. T. Pileggi (Carnegie Mellon University)
29.3
Piecewise Polynomial Nonlinear Model Reduction
.484
N.
Dong, J. Roychowdhury (University of Minnesota)
29.4
A TBR-based Trajectory Piecewise-Linear Algorithm for Generating
Accurate Low-order Models for Nonlinear Analog Circuits and MEMS
.490
D. Vasilyev, M.
Rewieński, J.
White (Massachusetts Institute of Technology)
SESSION
30:
Novel Techniques in High-Level Synthesis
Chair:
Christophe Wolinski (Los
Alamos National Laboratory)
Organizers:
Gila
Kamhi,
Krzysztof
Kuchcinski
30.1
Toward Efficient Static Analysis of Finite-Precision Effects
in DSP Applications via
Affine
Arithmetic Modeling
.496
C. F. Fang, R. A.
Rutenbar,
M.
Püschel,
T.
Chen
(Carnegie Mellon
University)
30.2
Automating the Design of an Asynchronous DLX Microprocessor
.502
M. Amde (Indian Institute of Technology), I. Blunno
(Politecnico di
Torino),
С.
P. Sotiriou (FORTH)
30.3
High-Level Synthesis of Asynchronous Systems
by Data-Driven Decomposition
.508
C. G. Wong, A. J. Martin (California Institute of Technology)
30.4
Using Estimates from Behavioral Synthesis Tools
in Compiler-Directed Design Space Exploration
.514
B. So, P. C. Diniz, M. W. Hall (University of Southern California at Los Angeles)
SESSION
31 :
Mixed-Signal Design and Simulation
Chair: Alan Mantooth (University of Arkansas)
Organizer: David
Allstot
31.1
A
1
6-Bit Mixed-Signal Microsystem with Integrated CMOS-MEMS
Clock Reference
.520
R. M. Senger, E. D.
Marsman,
M. S. McCorquodale, F. H. Gebara,
K. L.
Kräver,
M. R.
Guthaus,
R. B.
Brown (University of Michigan)
31.2
Fractional-N Frequency Synthesizer Design at the Transfer Function
Level Using a Direct Closed Loop Realization Algorithm
.526
C. Y.
Lau,
M. H. Perrott (Massachusetts
Institute
of
Technology)
31.3
Characterizing the Effects of Clock Jitter Due to Substrate Noise
in Discrete-Time
Δ/Σ
Modulators
.532
P. Heydari (University of California at Irvine)
xi
31.4
Computation of Noise Spectral Density in Switched Capacitor Circuits
using the Mixed-Frequency-Time Technique
538
V. Vasudevan, M. Ramakrishna (Indian Institute of Technology)
31.5
Symbolic Analysis of Analog Circuits with Hard Nonlinearity
542
A. Manthe, Z. Li, C.-J. R. Shi (University of Washington)
SESSION
32:
Panel
—
Nanometer Design: Place Your Bets
546
Chair: Andrew B. Kahng (University of California at San Diego)
Organizers: Gloria Nichols,
Bing
Sheu
Panelists: S. Borkar (Intel Corporation), J. Cohn (IBM Corporation),
A. Domic (Synopsys, Incorporated), P. Groeneveld (Magma Design Automation),
L. Scheffer (Cadence Design Systems, Incorporated),
Christophe Frey (STMicroelectronics)
SESSION
33:
Novel Self-Test Methods
Chair:
Janusz Rajski
(Mentor Graphics Corporation)
Organizers: Tim Cheng,
TM Mak
33.1
A Scalable Software-Based Self-Test Methodology
for Programmable Processors
.548
L. Chen (University of California at San Diego),
S. Ravi, A. Raghunathan (NEC Laboratories America, Inc.),
S. Dey
(University of California at San Diego)
33.2
A Scan BIST Generation Method Using A Markov Source
and Partial Bit-Fixing
.554
W. Li, C. Yu,
S. M.
Reddy (University of Iowa), I. Pomeranz (Purdue University)
33.3
Seed Encoding with LFSRs and Cellular Automata
.560
A. A. Al-Yamani, E. J. McCluskey (Stanford University)
33.4
Efficient Compression and Application of Deterministic Patterns
in a Logic BIST Architecture
.566
P.
Wohl,
J. A. Waicukauski, S.
Patel,
Μ. Β.
Amin (Synopsys,
Incorporated)
33.5
Ultimate Low Cost Analog BIST
.570
M.
Negreiros,
L.
Carro,
Α. Α.
Susin
(Universidade Federal
do Rio Grande do Sul)
SESSION 34:
Technology
Mapping, Buffering, and Bus
Design
Chair: John Lillis (University of
Illinois)
Organizers:
Charles
J.
Alpert,
Dennis Sylvester,
Raymond
Nijssen
34.1
Gain-Based Technology Mapping for Discrete-Size Cell Libraries
.574
B. Hu (University of California at Santa Barbara), Y. Watanabe, A. Kondratyev
(Cadence Berkeley Laboratories), M. Marek-Sadowska (University of California at Santa Barbara)
34.2
An O(nlogn) Time Algorithm for Optimal Buffer Insertion
.580
W. Shi, Z. Li (Texas A&M University)
34.3
Optimum Positioning of interleaved Repeaters in Bidirectional Buses
.586
M. Ghoneima, Y. Ismail (Northwestern University)
34.4
Synthesizing Optimal Filters for Crosstalk-cancellation for High-Speed Buses
.592
J. Ren, M. Greenstreet (University of British Columbia)
SESSION
35:
Compilation Techniques for
Reconfigurable
Devices
Chair.
Ryan Kastner
(University of California at Santa Barbara)
Organizers: Jens Palsberg, Scott Hauck
35.1
Fast Timing-driven Partitioning-based Placement for Island Style FPGAs
.598
P. Maidee, C. Ababei, K. Bazargan (University of Minnesota)
35.2
Global
Resource Sharing for Synthesis of Control Data Flow Graphs on FPGAs
.604
S. O. Memik, G. Memik, R. Jafari, E. Kursun (University of California at Los Angeles)
35.3
Compiler-Generated Communication for Pipelined FPGA Applications
.610
H. E. Ziegler, M. W. Hall, P.
С
Diniz (University of Southern California at Los Angeles)
35.4
Data Communication Estimation and Reduction for
Reconfigurable
Systems
.616
A. Kaplan, P. Brisk (University of California at Los Angeles),
R.
Kastner
(University of California at Santa Barbara)
SESSION
36:
Architectural Power Estimation and Optimization
Chair: Vijay Narayanan (Penn State University)
Organizer: Chaitali Chakrabarti
36.1
Clock-Tree Power Optimization based on
RTL
Clock-Gating
.622
M.
Dormo
(BullDASTs.r.l.), A. Ivaldi
(Politecnico de
Torino),
L.
Benini
(Università di Bologna),
E.
Macii
(Politecnico di Torino)
36.2
Low-Power
Design
Methodology for an On-chip Bus
with Adaptive Bandwidth Capability
.628
R.
Bashirullah (North Carolina State University), W. Liu (University of California at Santa Cruz),
R. K.
Cavin (Semiconductor Research Corporation)
36.3
Power-Aware Issue Queue Design for Speculative Instructions
.634
T. Moreshet, R. I. Bahar (Brown University)
36.4
State-Based Power Analysis for Systems-on-Chip
.638
R.
A. Bergamaschi
(IBM Thomas J. Watson Research Center),
Y. W.
Jiang (University of California at Berkeley)
SESSION
37:
Panel
—
Libraries: Lifejacket or Straitjacket
.642
Chair:
Carl Sechen
(University of Washington)
Organizers: Chandu Visweswariah, Gerard Mas
Panelists: B. Chappel (Intel
Corporation),
J. Hogan (Artisan Components, Incorporated),
A. Moore (TSMC), T. Nakamura (STARC), G. Northrop (IBM Corporation),
A. Thakar (Synopsys, Incorporated)
SESSION
38:
Techniques for
Reconfigurable
Logic Applications
Chair: Michael Butts (Cadence Design Systems, Incorporated)
Organizers: Majid
Sarrafžadeh,
Scott Hauck
38.1
Switch-Level Emulation
.644
A. Ejlali,
S. G.
Miremadi (Sharif University of Technology)
38.2
Designing Fault Tolerant Systems into SRAM-based FPGAs
.650
F. Lima
(Universidade
Federal do Rio Grande do
Sul
&
Universidade Estadual
do Rio Grande do Sol),
L.
Carro,
R.
Reis (Universidade Estadual do Rio Grande do Sul)
38.3
Determining Appropriate Precisions for Signals in Fixed-Point ilR Filters
.656
J.
Carletta,
R. Veillette, F. Krach, Z.
Fang (University of Akron)
SESSION
39:
Test and Diagnosis for Complex Designs
Chair: Rathish Jayabharathi, (Intel Corporation)
Organizers: Seiji
Kajihara, TM Mak
39.1
Test Generation for Designs with Multiple Clocks
.662
X. Lin, R. Thompson (Mentor Graphics Corporation)
39.2
Enhancing Diagnosis Resolution for Delay Defects Based Upon
Statistical Timing and Statistical Fault Models
.668
A. Krstić, L.-C.
Wang,
Κ.-Ί.
Cheng (University of California at Santa Barbara),
J.-J.
Liou
(Tsing-Hua University),
T. M. Mak
(Intel Corporation)
39.3
Using Embedded Infrastructure IP for
SOC
Post-Silicon Verification
674
Y. Huang, W.-T. Cheng (Mentor Graphics Corporation)
39.4
Using Satisfiability in Application-Dependent Testing of FPGA Interconnects
678
M. B. Tahoori (Stanford University)
SESSION
40:
Special Session
—
Highlights of ISSCC:
High-Speed Heterogenous Design Techniques
Chair: Paul Zuchowski (IBM Microelectronics)
Organizers: Limor Fix, Luciano Lavagno
40.1
Design of a "lOGHz Clock Distribution Network Using Coupled
Standing-Wave Oscillators
.
682
F. O'Mahony (Stanford University),
С
P. Yue (Aeluros, Incorporated),
M. A. Horowitz, S. S. Wong (Stanford University)
40.2
Self-Biased High-Bandwidth Low-Jitter i-to-4096 Multiplier
Clock Generator
PLL
.688
J. G. Maneatis, J. Kim, I. McClatchie (True Circuits, Incorporated),
J. Maxey, M. Shankaradas (Texas Instruments Incorporated)
40.3
A Reconfigurable
Signal Processing
1С
with Embedded FPGA
and Multi-Port Flash Memory
.691
M. Borgatti, L.
Cali,
G. De Sandre,
В.
Forêt, D.
lezzi,
F. Lertora, G. Muzzi,
M. Pasotti, M.
Poles, P.L. Rolandi (STMicroelectronics)
SESSION
41 :
Spec/a/ Session
—
Highlights of ISSCC
and The Design of State-of-the-Art Microprocessors
Chair: Noel
Menezes
(Intel Corporation)
Organizers: Limor Fix and Luciano Lavagno
41.1
Physical Synthesis Methodology for High Performance Microprocessors
.696
Y.-H. Chan (IBMServer Group), P. Kudva, L. Lacey, G. Northrop
(IBM Thomas J. Watson Research Center),
T. Rosser (IBM
Server Group)
41.2
A 1.3GHZ Fifth Generation SPARC64 Microprocessor
.702
H.
Ando,
Y.
Yoshida, A. Inoue, I. Sugiyama, T. Asakawa, K.
Monta, T. Muta, T.
Motokurumada,
S. Okada, H. Yamashita, Y. Satsukawa, A. Konmoto, R. Yamashita, H. Sugiyama (Fujitsu Ltd.)
41.3
A 1.5GHZ
Third Generation Itanium®
2
Processor.
706
J. Stinson, S.
Rusu
(Intel Corporation)
SESSION
42:
Panel
—
Formal Verification
—
Prove It or Pitch It
.710
Chair: Rajesh Gupta (University of California at San Diego)
Organizers: Shishpal Rawat (Intel Corporation), Sandeep Shukla (Virginia Technology)
Panelists: B. Bailey (Mentor Graphics Corporation), D. Beece (IBM Corporation),
M. Fujita (Tokyo University),
C. Pixley
(Synopsys, Incorporated),
J. O'Leary (Intel Corporation), F. Somenzi (University of Colorado at Boulder)
SESSION
43:
High Frequency Interconnect Modeling
Chair. Charlie
С. Р.
Chen (University of Wisconsin)
Organizers: Bernard
N
Sheehan, Byron L.
Krauter
43.1
Algorithms in Fastlmp: A Fast and Wideband Impedance Extraction
Program For Complicated
3-D
Geometries
.712
Z. Zhu, B. Song, J. White (Massachusetts Institute ofTechnology)
43.2
Vector Potential Equivalent Circuit Based on PEEC Inversion
.718
H. Yu, L. He (University of California at Los Angeles)
xiv
43.3
On-chip Interconnect-Aware Design
and Modeling Methodology,
Based on High Bandwidth Transmission Line Devices
.724
D.
Goren,
M.
Zelikson,
R.
Gordin, I. A. Wagner, A. Barger, A. Amir, B. Livshitz, A. Sherman
(IBMHaifa Research and Development Laboratories),
Y. Tretiakov
(IBM Design Automation),
R. Groves, J. Park (IBMSiGe Model Development), D. Jordan, S.
Strang,
R.
Singh,
С.
Dickey,
D. Harame
(IBM
Design Automation)
43.4
An Adaptive Window-Based Susceptance Extraction
and its
Efficient
Implementation
.728
G. Zhong, C.-K. Koh, V. Balakrishnan, K. Roy (Purdue University)
SESSION
44:
Novel Approaches in Test Cost Reduction
Chair: Yervant Zorian
(Virage
Logic)
Organizers: Erik Jan
Marinissen,
Seiji Kajihara
44.1
Test Application Time and Volume Compression through Seed Overlapping
.732
W. Rao (University of California at San Diego), I. Bayraktaroglu (Sun Microsystems),
A. Orailoglu (University of California at San Diego)
44.2
Test Cost Reduction for SOCs Using Virtual TAMs and
Lagrange
Multipliers
.738
A. Sehgal (Duke University), V. Iyengar (IBM Microelectronics),
M. D. Krasniewski, K. Chakrabarty (Duke University)
44.3
A Cost-Effective Scan Architecture for Scan Testing with Non-Scan
Test Power and Test Application Cost
.744
D. Xiang, S. Gu, J.-G. Sun (Tsinghua University), Y.-L. Wu (Chinese University of Hong Kong)
44.4
On Test Data Compression and n-Detection Test Sets
.748
I. Pomeranz (Purdue University), S. M. Reddy (University of Iowa)
SESSION
45:
Retargetable Tools for Embedded Software
Chair:
Heinrich
Meyr (RWTH)
Organizers: Anand Raghunathan,
Lothar Thiele
45.1
A Retargetable Micro-architecture Simulator
.752
W. S. Mong, J. Zhu (University of Toronto)
45.2
Instruction Set Compiled Simulation: A Technique for Fast
and Flexible Instruction Set Simulation
.758
M. Reshadi, P. Mishra,
N.
Dutt (University of California at Irvine)
45.3
Automated Synthesis of Efficient Binary Decoders
for Retargetable Software Toolkits
.764
W. Qin, S. Malik (Princeton University)
SESSION
46:
Special Session
—
ASIC Design in Nanometer Era
-
Dead or Alive?
Chair: Nancy Nettleton (Sun Microsystems)
Organizers: Abhijit Dharchoudhury,
Sachin
S.
Sapatnekar
46.1
Designing Mega-ASICs in Nanogate Technologies
.770
D. E. Lackey, P. S. Zuchowski, J. Koehl (IBMMicroelectronics Division)
46.2
Architecting ASIC Libraries and Flows in Nanometer Era
.776
C. Bittlestone, A. Hill, V. Singhal,
N.
V. Arvind (Texas Instruments Incorporated)
46.3
Exploring Regular Fabrics to Optimize the Performance-Cost Trade-Off'
.782
L. Pileggi, H. Schmit, A. J. Strqjwas, P. Gopalakrishnan, V. Kheterpal, A. Koorapaty,
С
Patel,
V. Rovner, K. Y.
Tong
(Carnegie Mellon
University)
46.4
Pushing ASIC Performance in a Power Envelope
.788
R.
Puri,
L. Stok
(IBM
Thomas J. Watson Research Center), J. Cohn (IBM Microelectronics),
D.
Kung,
D.
Pan (IBM Thomas J. Watson Research Center), D. Sylvester, A. Srivastava,
S.
Kulkami
(University of Michigan)
xv
SESSION 47: Floorplanning and
Placement
Chair:
Carl Sechen
(University of
Washington)
Organizers:
С
Y.
Roger
Chen,
Ralph Otten
47.1 An
Algebraic Multigrid Solver for Analytical Placement
with Layout Based Clustering
.
794
H. Chen, C.-K. Cheng (University of California at San Diego),
N.-C.
Chou
(Mentor Graphics Corporation), A. B. Kahng (University of California at San Diego),
J. F. MacDonald, P. Suaris (Mentor Graphics Corporation),
B. Yao, Z. Zhu (University of California at San Diego)
47.2
Wire Length Prediction based Clustering and its Application in Placement
800
B. Ни, М.
Marek-Sadowska (University of California at Santa Barbara)
47.3
Dynamic Global Buffer Planning Optimization Based
on Detail Block Locating and Congestion Analysis
.806
Y. Ma, X. Hong, S. Dong, S. Chen, Y.
Cai (Tsinghua
University),
С
K. Cheng (University of California at San Diego), J. Gu (University of Hong Kong)
47
A Multilevel Floorplanning/Placement for Large-Scale Modules Using BMrees
.812
H.-C. Lee (Synopsys, Incorporated), Y.-W. Chang (National Taiwan University),
J.-M. Hsu (National Center for High-Performance Computing),
H. H.
Yang (Intel Corporation)
SESSION
48:
Advances in SAT
Chair: Per Bjesse (Synopsys, Incorporated)
Organizers:
Karem
A. Sakallah, Rajeev Ranjan
48.1
Checking Satisfiability of a Conjunction of BDDs
.818
R.
Damiano,
J. Kukula (Synopsys, Incorporated)
48.2
Learning from BDDs in SAT-based Bounded Model Checking
.824
A. Gupta, M. Ganai (NEC Laboratories America, Incorporated),
C. Wang (University of Colorado at Boulder),
Z. Yang, P. Ashar (NEC Laboratories America, Incorporated)
48.3
A Fast Pseudo-Boolean Constraint Solver
.830
D.
Chai
(University of California at Berkeley)
A. Kuehlmann (Cadence Berkeley Laboratories)
48.4
Shatter: Efficient Symmetry-Breaking for Boolean Satisfiability
.836
F. A. Aloul, I. L. Markov, K. A. Sakallah (University of Michigan)
48.5
SAT-Based Unbounded Symbolic Model Checking
.840
H.-J. Kang, I.-C. Park (KAJST)
SESSION
49:
Novel Design Methodologies and Signal Integrity
Chair Shared Mehrotra (Sun Microsystems)
Organizers: Abhijit Dharchoudhury, Noel
Menezes
49.1
Design of a 17-million Gate Network Processor using a Design Factory
.844
G.-E. Descamps, S. Bagalkotkar, S. Ganesan, S. Iyengar,
A. Pirson
(Silicon Access Networte Incorporated)
49.2
Hybrid Hierarchical Timing Closure Methodology for a High Performance
and Low Power DSP
.
S50
K. Shi (Synopsys, Incorporated), G. Godwin (Texas Instruments, Incorporated)
49.3
Statistical Estimation of Leakage-induced Power Grid Voltage
Drop Considering Within-Die Process Variations
.856
I.
A. Fendi,
F. N. Najm
(University of
Toronto)
xvi
49.4
Temporofunctional Crosstalk Noise Analysis
.860
D.
Chai
(University of California at Berkeley), A. Kondratyev (Cadence Berkeley Laboratories),
Y. Ran (University of California at Santa Barbara),
K. H. Tseng (Cadence Design Systems, Incorporated),
Y. Watanabe (Cadence Berkeley Laboratories),
M. Marek-Sadowska (University of California at Santa Barbara)
49.5
Static Noise Analysis with Noise Windows
.864
K. Tseng, V. Kariat (Cadence Design Systems, Incorporated)
SESSION
50:
Memory Optimization for Embedded Systems
Chair:
Marcello Lajolo
(NEC Corporation)
Organizer: Anand Raghunathan
50.1
Embedded Intelligent SRAM
.869
P. Jain, G. E.
Suh,
S. Devadas
(Massachusetts Institute of Technology)
50.2
Improved Indexing for Cache Miss Reduction in Embedded Systems
.875
T. Givargis (University of California at Irvine)
50.3
Memory Layout Techniques for Variables Utilizing Efficient DRAM
Access Modes in Embedded System Design
.881
Y. Choi, T. Kim (Korea Advanced Institute of Science
&
Technology Research Center)
50.4
Interprocedural Optimizations for Improving Data Cache Performance
of Array-Intensive Embedded Applications
.887
W. Zhang, G. Chen, M. Kandemir (Pennsylvania State University), M. Karakoy (Imperial College)
SESSION
51 :
Special Session
—
Design Automation for Quantum Circuits
Andreas Kuehlmann (Cadence Berkeley Laboratories)
Organizers:
Soha
Hassoun, Igor L. Markov
51.1
Tutorial: Basic Concepts in Quantum Circuits
.893
J. P. Hayes (University of Michigan)
51.2
Designing and Implementing Small Quantum Circuits and Algorithms
.894
B. Travaglione (University of Cambridge)
SESSION
52:
Energy-Aware System Design
Chair: Sujit
Dey
(University of California at San Diego)
Organizers: Kaushik Roy,
Luca
Benini
52.1
A Survey of Techniques for Energy Efficient On-Chip Communication
.900
V. Raghunathan, M. B. Srivastava (University of California at Los Angeles)
R. K. Gupta (University of California at San Diego),
52.2
Extending the Lifetime of a Network of Battery-Powered Mobile Devices
by Remote Processing: A Markovian Decision-based Approach
.906
P. Rong, M. Pedram (University of Southern California at Los Angeles)
52.3
Energy-Aware MPEG-4 FGS Streaming
.912
K. Choi (University of Southern California at Los Angeles), K. Kim (Seoul National University),
M. Pedram (University of Southern California at Los Angeles)
52.4
A Low-Energy Chip-Set for Wireless Intercom
.916
M. J.
Ammer,
M.
Sheets,
T. Karalar,
M. Kuulusa,
J.
Rabaey (University of California at Berkeley)
xvii
SESSION 53:
Budgeting,
Simulation
and Statistical Timing
Chair: Louis Scheffer (Cadence Design Systems, Incorporated)
Organizers: Kenneth L. Shepard, Sudhakar
Bobba
53.1
Optimal Integer Delay Budgeting on Directed Acyclic Graphs
920
E. Bozorgzadeh, S. Ghiasi (University of California at Los Angeles),
A. Takahashi (Tokyo Institute of Technology), M. Sarrafzadeh (University of California at Los Angeles)
53.2
Optimizations for a Simulator Construction System Supporting
Reusable Components
.926
D.
А. Решу,
D.
I. August (Princeton University)
53.3
Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits
.932
J. A. G. Jess (Eindhoven University of Technology),
K. Kalafala
(IBM Microelectronics Division),
S. R. Naidu, R. H. J. M. Otten (Eindhoven University of Technology),
C. Visweswariah (IBM Thomas J. Watson Research Center)
SESSION
54:
Interconnect Noise Avoidance Methodologies
&
Slew Rate
Prediction
Chair:
Sani Nassif
(IBM Corporation)
Organizers: Byron L.
Krauter, Sachin
S.
Sapatnekar
54.1
Interconnect and Noise Immunity Design for the Pentium®
4
Processor
.938
R. Kumar (Intel Corporation)
54.2
Crosstalk Noise in FPGAs
.944
Y. Ran, M. Marek-Sadowska (University of California at Santa Barbara)
54.3
Simple Metrics for Slew Rate of RC Circuits Based on Two Circuit Moments
.950
K. Agarwal, D. Sylvester, D. Blaauw (University of Michigan)
54.4
Post-Route Gate Sizing for Crosstalk Noise Reduction
.954
M. R. Becer (Motorola, Incorporated), D. Blaauw (Universiyt of Michigan Ann Arbor),
I.
Algor,
R.
Panda,
C. Oh, V. Zolotov (Motorola),
I.
N. Hajj
(University of
Illinois Urbana-Champaign)
SESSION
55:
Analog
Design
Space Exploration
Chair: Richard Shi (University of Washington)
Organizer: Georges G. Gielen
55.1
Performance Trade-off Analysis of Analog Circuits
by Normal-Boundary Intersection
.958
G. Stehr, H. Graeb, K. Antreich (Technical University of Munich)
55.2
Support Vector Machines for Analog Circuit Performance Representation
.964
F. De
Bemardinis, M. I. Jordan, A. Sangiovanm-Vmcentelli (University of California at Berkeley)
55.3
Efficient Description of the Design Space of Analog Circuits
.970
M. del Mar Hershenson (Barcelona Design, Incorporated)
55.4
Architectural Selection of A/D Converters
.974
M.
Vogels,
G.
Gielen
(Katholieke Universiteit Leuven)
Author Index
.
97g
XV1H |
| any_adam_object | 1 |
| author_corporate | Design Automation Conference (Association for Computing Machinery) Anaheim, Calif |
| author_corporate_role | aut |
| author_facet | Design Automation Conference (Association for Computing Machinery) Anaheim, Calif |
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| discipline | Informatik |
| format | Conference Proceeding Book |
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| spelling | Design Automation Conference (Association for Computing Machinery) 40 2003 Anaheim, Calif. Verfasser (DE-588)10066218-3 aut Proceedings 2003 Anaheim Convention Center, Anaheim, CA, June 2 - 6, 2003 Design Automation Conference, 40th DAC Conference DAC 2003 Proceedings of the 40th Design Automation Conference Proceedings New York, NY ACM Press 2003 XXXIV, 981 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier (DE-588)1071861417 Konferenzschrift gnd-content Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=010380906&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Proceedings 2003 Anaheim Convention Center, Anaheim, CA, June 2 - 6, 2003 |
| subject_GND | (DE-588)1071861417 |
| title | Proceedings 2003 Anaheim Convention Center, Anaheim, CA, June 2 - 6, 2003 |
| title_alt | DAC 2003 Proceedings of the 40th Design Automation Conference Proceedings |
| title_auth | Proceedings 2003 Anaheim Convention Center, Anaheim, CA, June 2 - 6, 2003 |
| title_exact_search | Proceedings 2003 Anaheim Convention Center, Anaheim, CA, June 2 - 6, 2003 |
| title_full | Proceedings 2003 Anaheim Convention Center, Anaheim, CA, June 2 - 6, 2003 Design Automation Conference, 40th DAC Conference |
| title_fullStr | Proceedings 2003 Anaheim Convention Center, Anaheim, CA, June 2 - 6, 2003 Design Automation Conference, 40th DAC Conference |
| title_full_unstemmed | Proceedings 2003 Anaheim Convention Center, Anaheim, CA, June 2 - 6, 2003 Design Automation Conference, 40th DAC Conference |
| title_short | Proceedings 2003 |
| title_sort | proceedings 2003 anaheim convention center anaheim ca june 2 6 2003 |
| title_sub | Anaheim Convention Center, Anaheim, CA, June 2 - 6, 2003 |
| topic_facet | Konferenzschrift |
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