Optimized, highly parallel architectures for iterative decoding algorithms: = Optimierte hochparallele Architekturen für iterative Decodierverfahren
Saved in:
| Main Author: | |
|---|---|
| Format: | Thesis Book |
| Language: | English |
| Published: |
Kaiserslautern
Univ.
2003
|
| Edition: | Als Ms. gedr. |
| Series: | Forschungsberichte Mikroelektronik
5 |
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Physical Description: | X, 155 S. Ill., graph. Darst. |
| ISBN: | 3936890064 |
Staff View
MARC
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| 001 | BV017078308 | ||
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| 100 | 1 | |a Gilbert, Frank |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Optimized, highly parallel architectures for iterative decoding algorithms |b = Optimierte hochparallele Architekturen für iterative Decodierverfahren |c Frank Gilbert |
| 246 | 1 | 1 | |a Optimierte hochparallele Architekturen für iterative Decodierverfahren |
| 250 | |a Als Ms. gedr. | ||
| 264 | 1 | |a Kaiserslautern |b Univ. |c 2003 | |
| 300 | |a X, 155 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Forschungsberichte Mikroelektronik |v 5 | |
| 502 | |a Zugl.: Kaiserslautern, Univ., Diss., 2003 | ||
| 650 | 0 | 7 | |a Parallelverarbeitung |0 (DE-588)4075860-6 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Iterative Decodierung |0 (DE-588)4486066-3 |2 gnd |9 rswk-swf |
| 655 | 7 | |0 (DE-588)4113937-9 |a Hochschulschrift |2 gnd-content | |
| 689 | 0 | 0 | |a Iterative Decodierung |0 (DE-588)4486066-3 |D s |
| 689 | 0 | 1 | |a Parallelverarbeitung |0 (DE-588)4075860-6 |D s |
| 689 | 0 | |5 DE-604 | |
| 830 | 0 | |a Forschungsberichte Mikroelektronik |v 5 |w (DE-604)BV012925671 |9 5 | |
| 856 | 4 | 2 | |m DNB Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=010303917&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-010303917 | |
Record in the Search Index
| _version_ | 1808225937058168832 |
|---|---|
| adam_text |
CONTENTS
1
INTRODUCTION
1
1.1
THE
DEMANDS
OF
FUTURE
APPLICATIONS
.
1
1.1.1
LOW
POWER
CONSUMPTION
.
2
1.1.2
HIGH
THROUGHPUT
COMPUTATION
.
5
1.1.3
DESIGN
FOR
FLEXIBILITY
.
5
1.2
OBJECTIVES
AND
MAIN
CONTRIBUTIONS
.
7
1.3
CHAPTER
OVERVIEW
.
8
2
PARALLEL
ARCHITECTURES
11
2.1
FUTURE
SYSTEMS-ON-CHIP
ARCHITECTURES
.
11
2.1.1
THE
ENERGY-FLEXIBILITY
GAP .
12
2.1.2
CLOSING
THE
GAP
.
13
2.1.3
APPLICATION
SPECIFIC
MULTIPROCESSOR
SYSTEMS-ON-CHIP
.
19
2.2
DESIGN
METHODOLOGY
FOR
AP-MPSOC
ARCHITECTURES
.
20
3
ALGORITHM
SELECTION:
TUERBO
DECODING
23
3.1
TURBO-CODES
.
23
3.2
THE
MAP
ALGORITHM
.
26
3.2.1
LOG-MAP
IMPLEMENTATION
.
30
3.2.2
LOOP
TRANSFORMATION
.
33
3.3
INTERLEAVING
.
38
VIII
CONTENTS
4
ITERATION
CONTROL
41
4.1
MOTIVATION
.
41
4.2
RELATED
WORK
.
43
4.3
TURBO-DECODER
SYSTEM
MODEL
.
45
4.4
ITERATION
CONTROL
CRITERIA
DEFINITION
.
46
4.4.1
SOFT-DECISION
RULES
.
46
4.4.2
HARD-DECISION
RULES
.
47
4.4.3
ADDITIONAL
RULES
.
48
4.5
DECODING
PERFORMANCE
COMPARISON
.
48
4.5.1
COMMUNICATIONS
PERFORMANCE
.
49
4.5.2
AVERAGE
ITERATIONS
.
50
4.5.3
IMPLEMENTATION
COMPLEXITY
OF
STOPPING
RULES
.
53
4.6
A
COMBINED
SCHEME
FOR
ITERATION
CONTROL
.
55
5
PARALLELIZATION
59
5.1
PARALLELIZATION
LAYERS
.
59
5.1.1
DATA
TRANSFER
(I/O)
LAYER
.
60
5.1.2
MAP-DECODER
LAYER
.
62
5.1.3
INTERLEAVER
NETWORK
LAYER
.
62
5.2
DEDICATED
HARDWARE
SOLUTIONS
.
65
5.2.1
D AND
X
ARCHITECTURES
FOR
MAP
DECODING
.
66
5.2.2
A
SCALABLE
TURBO-DECODER
SYSTEM
ARCHITECTURE
.
67
5.3
TURBO
DECODING
ON
AP-MPSOC
ARCHITECTURES
.
68
5.3.1
ARCHITECTURE
OF
THE
PROCESSOR-NODES
.
70
5.3.2
ARCHITECTURE
TEMPLATE
.
70
5.3.3
AREA
AND
THROUGHPUT
RESULTS
.
78
5.3.4
COMPARISON
TO
PARALLELIZATION
ON
BLOCK
LEVEL
.
82
5.4
COMPARISON
OF
HARDWARE
AND
SOFTWARE
SOLUTIONS
.
82
CONTENTS
IX
6
VOLTAGE
SCALING
TECHNIQUES
85
6.1
ARCHITECTURE-DRIVEN
VOLTAGE
SCALING
.
85
6.2
VOLTAGE
SCHEDULING
TECHNIQUES
FOR
DVS-ENABLED
ARCHITECTURES
.
87
6.2.1
RELATEDWORK
.
88
6.2.2
VOLTAGE
SCHEDULING
ALGORITHMS
FOR
UMTS TURBO
DECODING
.
89
7
CONCLUSIONS
AND
FUTURE
WORK
93
8
ZUSAMMENFASSUNG
99
A
THE
ITERATIVE
TIIRBO-DECODER
107
A.L
CODED
TRANSMISSION
WITH
FORWARD-ERROR-CORRECTION
(FEC)
.
107
A.2
DECODING
PCCC
.
109
B
THE
MAP-DECODER
113
B.L
PROBABILITY
DOMAIN
.
113
B.1.1
OBJECTIVE
.
113
B.1.2
BRANCH
PROBABILITIES
.
114
B.1.3
PATH
PROBABILITIES
.
115
B.1.4
SOFT-OUTPUT
CALCULATION
.
116
B.2
LOGARITHM
DOMAIN
.
116
B.2.1
TRANSFORMATION
INTO
THE LOGARITHM
DOMAIN
.
117
B.2.2
BRANCH
METRICS
.
117
B.2.3
PATH
METRICS
.
118
B.2.4
SOFT-OUTPUT
CALCULATION
.
119
C
ITERATION
CONTROL
RESULTS
IN
AN
UMTS-COMPLIANT
SIMULATION
ENVIRONMENT
121
C.L
MULTI-PATH
FADING
CHANNEL
RESULTS
.
122
D
SYMBOLS
129
E
ABBREVIATIONS
133
X
CONTENTS
BIBLIOGRAPHY
139
LIST
OF
FIGURES
149
LIST
OF
TABLES
153
LIST
OF
ALGORITHMS
155 |
| any_adam_object | 1 |
| author | Gilbert, Frank |
| author_facet | Gilbert, Frank |
| author_role | aut |
| author_sort | Gilbert, Frank |
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| bvnumber | BV017078308 |
| classification_rvk | ZN 6045 |
| ctrlnum | (OCoLC)76446992 (DE-599)BVBBV017078308 |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | Als Ms. gedr. |
| format | Thesis Book |
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| genre | (DE-588)4113937-9 Hochschulschrift gnd-content |
| genre_facet | Hochschulschrift |
| id | DE-604.BV017078308 |
| illustrated | Illustrated |
| indexdate | 2024-08-24T00:17:14Z |
| institution | BVB |
| isbn | 3936890064 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-010303917 |
| oclc_num | 76446992 |
| open_access_boolean | |
| owner | DE-12 DE-91 DE-BY-TUM DE-29T DE-706 DE-634 DE-83 |
| owner_facet | DE-12 DE-91 DE-BY-TUM DE-29T DE-706 DE-634 DE-83 |
| physical | X, 155 S. Ill., graph. Darst. |
| publishDate | 2003 |
| publishDateSearch | 2003 |
| publishDateSort | 2003 |
| publisher | Univ. |
| record_format | marc |
| series | Forschungsberichte Mikroelektronik |
| series2 | Forschungsberichte Mikroelektronik |
| spelling | Gilbert, Frank Verfasser aut Optimized, highly parallel architectures for iterative decoding algorithms = Optimierte hochparallele Architekturen für iterative Decodierverfahren Frank Gilbert Optimierte hochparallele Architekturen für iterative Decodierverfahren Als Ms. gedr. Kaiserslautern Univ. 2003 X, 155 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Forschungsberichte Mikroelektronik 5 Zugl.: Kaiserslautern, Univ., Diss., 2003 Parallelverarbeitung (DE-588)4075860-6 gnd rswk-swf Iterative Decodierung (DE-588)4486066-3 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Iterative Decodierung (DE-588)4486066-3 s Parallelverarbeitung (DE-588)4075860-6 s DE-604 Forschungsberichte Mikroelektronik 5 (DE-604)BV012925671 5 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=010303917&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Gilbert, Frank Optimized, highly parallel architectures for iterative decoding algorithms = Optimierte hochparallele Architekturen für iterative Decodierverfahren Forschungsberichte Mikroelektronik Parallelverarbeitung (DE-588)4075860-6 gnd Iterative Decodierung (DE-588)4486066-3 gnd |
| subject_GND | (DE-588)4075860-6 (DE-588)4486066-3 (DE-588)4113937-9 |
| title | Optimized, highly parallel architectures for iterative decoding algorithms = Optimierte hochparallele Architekturen für iterative Decodierverfahren |
| title_alt | Optimierte hochparallele Architekturen für iterative Decodierverfahren |
| title_auth | Optimized, highly parallel architectures for iterative decoding algorithms = Optimierte hochparallele Architekturen für iterative Decodierverfahren |
| title_exact_search | Optimized, highly parallel architectures for iterative decoding algorithms = Optimierte hochparallele Architekturen für iterative Decodierverfahren |
| title_full | Optimized, highly parallel architectures for iterative decoding algorithms = Optimierte hochparallele Architekturen für iterative Decodierverfahren Frank Gilbert |
| title_fullStr | Optimized, highly parallel architectures for iterative decoding algorithms = Optimierte hochparallele Architekturen für iterative Decodierverfahren Frank Gilbert |
| title_full_unstemmed | Optimized, highly parallel architectures for iterative decoding algorithms = Optimierte hochparallele Architekturen für iterative Decodierverfahren Frank Gilbert |
| title_short | Optimized, highly parallel architectures for iterative decoding algorithms |
| title_sort | optimized highly parallel architectures for iterative decoding algorithms optimierte hochparallele architekturen fur iterative decodierverfahren |
| title_sub | = Optimierte hochparallele Architekturen für iterative Decodierverfahren |
| topic | Parallelverarbeitung (DE-588)4075860-6 gnd Iterative Decodierung (DE-588)4486066-3 gnd |
| topic_facet | Parallelverarbeitung Iterative Decodierung Hochschulschrift |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=010303917&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV012925671 |
| work_keys_str_mv | AT gilbertfrank optimizedhighlyparallelarchitecturesforiterativedecodingalgorithmsoptimiertehochparallelearchitekturenfuriterativedecodierverfahren AT gilbertfrank optimiertehochparallelearchitekturenfuriterativedecodierverfahren |