Trade-offs in analog circuit design: the designer's companion
Gespeichert in:
| Format: | Buch |
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| Sprache: | English |
| Veröffentlicht: |
Boston [u.a.]
Kluwer Academic Publishers
2002
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| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XXXV, 1048 Ill., graph. Darst. |
| ISBN: | 1402070373 |
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| 245 | 1 | 0 | |a Trade-offs in analog circuit design |b the designer's companion |c ed. by Chris Toumazou ... |
| 264 | 1 | |a Boston [u.a.] |b Kluwer Academic Publishers |c 2002 | |
| 300 | |a XXXV, 1048 |b Ill., graph. Darst. | ||
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| adam_text | IMAGE 1
TRADE-OFFS IN ANALOG
CIRCUIT DESIGN THE DESIGNER S COMPANION
EDITED BY
CHRIS TOUMAZOU IMPERIAL COLLEGE, UK GEORGE MOSCHYTZ
ETH-ZENTRUM, SWITZERLAND
AND
BARRIE GILBERT ANALOG DEVICES, USA
EDITING ASSISTANCE
GANESH KATHIRESAN
L4
KLUWER ACADEMIC PUBLISHERS BOSTON / DORDRECHT / LONDON
IMAGE 2
CONTENTS
FOREWORD XXIII
LIST OF CONTRIBUTORS XXIX
DESIGN METHODOLOGY
1
INTUITIVE ANALOG CIRCUIT DESIGN 1
CHRIS TOUMAZOU 1.1 INTRODUCTION 1
1.2 THE ANALOG DILEMMA 2
REFERENCES 6
2
DESIGN FOR MANUFACTURE 7
BARRIE GILBERT 2.1 MASS-PRODUCTION OF MICRODEVICES 7
2.1.1 PRESENT OBJECLIVES 9
2.2 UNIQUE CHALLENGES OF ANALOG DESIGN 11
2.2.1 ANALOG IS NEWTONIAN 13
2.3 DESIGNING WITH MANULACTURE IN MIND 14
2.3.1 CONFLICL.S AND COMPROMISES 15
2.3.2 COPING WITH SCNSITIVITIES: DAPS, TAPS AND STMS 16
2.4 ROBUSTNESS, OPTIMI/AIION AND TRADE-OFFS 22
2.4.1 CHOICE OF ARCHIIEETURE 25
2.4.2 CHOICE OL TECHNOLOGY AND TOPOLOGY 27
2.4.3 REMEDICS FOR NON-ROBUST PRACTICES 32
2.4.4 TURNING IHC TABLES ON A NON-ROBUST CIRCUIT: A CASE STUDY 34
HOLISTIC OPTIMI/AIION OF THE LNA 39
A FURTHER EXAMPLC OL BIASING SYNERGY 44
2.4.5 ROBUSTNESS IN VOLTAGE REFERENCES 50
2.4.6 THE COST OL ROBUSTNESS 54
2.5 TOWARD DESIGN MASTERY 55
2.5.1 FIRST, THE FINALE 56
2.5.2 CONSIDER ALL DELIVERABLES 57
2.5.3 DESIGN COMPRESSION 58
2.5.4 FUNDAMENTALS BEFORE FINESSE 61
2.5.5 RE-UTILIZATION OF PROVEN CELLS 62
2.5.6 TRY TO BREAK YOUR CIRCUITS 63
2.5.7 USE CORNER MODELING JUDICIOUSLY 64
2.5.8 USE LARGE-SIGNAL TIME-DOMAIN METHODS 68
2.5.9 USE BACK-ANNOTATION OF PARASITICS 68
2.5.10 MAKE YOUR INTENTIONS CLEAR 69
2.5.11 DUBIOUS VALUE OF CHECK LISTS 70
2.5.12 USE THE TEN THINGS THAT WILL FAIL TEST 72
2.6 CONCLUSION 73
IMAGE 3
VI
CONTENTS
GENERAL PERFORMANCE
3
TRADE-OFFS IN CMOS VLSI CIRCUITS 75
ANDREY V. MEZHIBA AND EBY G. FRIEDMAN 3.1 INTRODUCTION 75
3.2 DESIGN CRITERIA 78
3.2.1 AREA 78
3.2.2 SPEED 79
3.2.3 POWER 79
3.2.4 DESIGN PRODUCTIVITY 80
3.2.5 TESTABILITY 81
3.2.6 RELIABILITY 81
3.2.7 NOISE TOLERANCE 82
3.2.8 PACKAGING 83
3.2.9 GENERAL CONSIDERATIONS 83
POWER DISSIPATION IN CMOS VLSI CIRCUITS 84
TECHNOLOGY SCALING 85
VLSI DESIGN METHODOLOGIES 86
3.3 STRUCTURAL LEVEL 86
3.3.1 PARALLEL ARCHITECTURE 87
3.3.2 PIPELINING 88
3.4 CIRCUIT LEVEL 89
3.4.1 STATIC VERSUS DYNAMIC 90
3.4.2 TRANSISTOR SIZING 91
3.4.3 TAPERED BUFFERS 95
3.5 PHYSICAL LEVEL 99
3.6 PROCESS LEVEL 102
3.6.1 SCALING 103
3.6.2 THRESHOLD VOLTAGE 103
3.6.3 POWER SUPPLY 103
3.6.4 IMPROVED INTERCONNECT AND DIELECTRIC MATERIALS 104
3.7 FUTURE TRENDS 104
GLOSSARY 107
REFERENCES 108
4
FLOATING-GATE CIRCUITS AND SYSTEMS 115
TOR SVERRE LANDE 4.1 INTRODUCTION 115
4.2 DEVICE PHYSICS 115
4.2.1 THIN DIOXIDE 116
4.2.2 CAPACITIVE CONNECTIONS 116
4.2.3 SPECIAL PROCESS REQUIREMENTS 117
4.3 PROGRAMMING 117
4.3.1 UV-CONDUCTANCE 118
4.3.2 FOWLER-NORDHEIM TUNNELING 118
4.3.3 HOT CARRIER INJECTION 119
IMAGE 4
CONTENTS
VN
4.4 CIRCUIT ELEMENTS 119
4.4.1 PROGRAMMING CIRCUITS 120
INTER-POLY TUNNELING 120
EXAMPLE: FLOATING-GATE ON-CHIP KNOBS 121
INTER-POLY UV-PROGRAMMING 121
MOS-TRANSISTOR UV-CONDUCTANCE 122
EXAMPLE: MOS TRANSISTOR THRESHOLD TUNING 123
COMBINED PROGRAMMING TECHNIQUES 124
EXAMPLE: SINGLE TRANSISTOR SYNAPSE 126
HIGH-VOL TAGE DRIVERS 127
4.5 FGMOS CIRCUITS AND SYSTEMS 128
4.5.1 AUTOZERO FLOATING-GATE AMPLIFIER 128
4.5.2 LOW-POWER/LOW-VOLTAGE RAIL-TO-RAIL CIRCUITS USING FGUVMOS 130
DIGITAL FGUVMOS CIRCUITS 130
LOW-VOLTAGE RAIL-TO-RAIL FGUVMOS AMPLIFIER 130
4.5.3 ADAPTIVE RETINA 132
4.5.4 OTHER CIRCUITS 134
4.6 RETENTION 134
4.7 CONCLUDING REMARKS 134
REFERENCES 135
5
BANDGAP REFERENCE DESIGN 139
ARIE VAN STAVEREN, MICHIEL H. L. KOUWENHOVEN, WOUTERA, SERDIJN AND CHRIS
J. M. VERHOEVEN 5.1 INTRODUCTION 139
5.2 THE BASIC FUNCTION 140
5.3 TEMPERATURE BEHAVIOR OF VSSE 140
5.4 GENERAL TEMPERATURE COMPENSATION 141
5.5 A LINEAR COMBINATION OF BASE-EMITTER VOLTAGES 142
5.5.1 FIRST-ORDER COMPENSATION 143
5.5.2 SECOND-ORDER COMPENSATION 144
5.6 THE KEY PARAMETERS 146
5.7 TEMPERATURE-DEPENDENT RESISTORS 147
5.8 NOISE 148
5.8.1 NOISE OF THE IDEALIZED BANDGAP REFERENCE 150
5.8.2 NOISE OF A FIRST-ORDER COMPENSATED REFERENCE 151
5.8.3 NOISE OF A SECOND-ORDER COMPENSATED REFERENCE 152
5.8.4 POWER-SUPPLY REJECTION 153
5.9 SIMPLIFIED STRUCTURES 155
5.9.1 FIRST-ORDER COMPENSATED REFERENCE 155
5.9.2 SECOND-ORDER COMPENSATED REFERENCE 156
5.10 DESIGN EXAMPLE 157
5.10.1 FIRST-ORDER COMPENSATED BANDGAP REFERENCE 157
5.10.2 SECOND-ORDER COMPENSATED BANDGAP REFERENCE 159
5.11 CONCLUSIONS 163
REFERENCES 164
IMAGE 5
VM
CONTENTS
6
GENERALIZED FEEDBACK CIRCUIT ANALYSIS , 169
SCOTT K. BURGESS AND JOHN CHOMA, JR. 6.1 INTRODUCTION 169
6.2 FUNDAMENTAL PROPERTIES OF FEEDBACK LOOPS 171
6.2.1 OPEN LOOP SYSTEM ARCHITECTURE AND PARAMETERS 171
6.2.2 CLOSED LOOP SYSTEM PARAMETERS 173
6.2.3 PHASE MARGIN 176
6.2.4 SETTLING TIME 179
6.3 CIRCUIT PARTITIONING 182
6.3.1 GENERALIZED CIRCUIT TRANSFER FUNCTION 183
6.3.2 GENERALIZED DRIVING POINT I/O IMPEDANCES 189
6.3.3 SPECIAL CONTROLLING/CONTROLLED PORT CASES 191
CONTROLLING FEEDBACK VARIABLE IS THE CIRCUIT OUTPUT VARIABLE 192
GLOBAL FEEDBACK 193
CONTROLLING FEEDBACK VARIABLE IS THE BRANCH VARIABLE OF THE CONTROLLED
PORT 195 REFERENCES 204
7
ANALOG AMPLIFIERS ARCHITECTURES: GAIN BANDWIDTH TRADE-OFFS 207
ALISON J. BURDETT AND CHRIS TOUMAZOU 7.1 INTRODUCTION 207
7.2 EARLY CONCEPTS IN AMPLIFIER THEORY 208
7.2.1 THE IDEAL AMPLIFIER 208
7.2.2 RECIPROCITY AND ADJOINT NETWORKS 209
7.2.3 THE IDEAL AMPLIFIER SET 210
7.3 PRACTICAL AMPLIFIER IMPLEMENTATIONS 211
7.3.1 VOLTAGE OP-AMPS 211
7.3.2 BREAKING THE GAIN-BANDWIDTH CONFLICT 213
CURRENT-FEEDBACK OP-AMPS 213
FOLLOWER-BASED AMPLIFIERS 214
CUNENT-CONVEYOR AMPLIFIERS 214
7.3.3 PRODUCING A CONTROLLED OUTPUT CURRENT 215
7.4 CLOSED-LOOP AMPLIFIER PERFORMANCE 217
7.4.1 IDEAL AMPLIFIERS 217
7.4.2 REAL AMPLIFIERS 218
7.5 SOURCE AND LOAD ISOLATION 222
7.6 CONCLUSIONS 224
REFERENCES 225
NOISE, GAIN AND BANDWIDTH IN ANALOG DESIGN 227
ROBERT G. MEYER 8.1 GAIN-BANDWIDTH CONCEPTS 227
8.1.1 GAIN-BANDWIDTH SHRINKAGE 230
8.1.2 GAIN-BANDWIDTH TRADE-OFFS USING INDUCTORS 232
8.2 DEVICE NOISE REPRESENTATION 234
8.2.1 EFFECT OF INDUCTORS ON NOISE PERFORMANCE 238
8.3 TRADE-OFFS IN NOISE AND GAIN-BANDWIDTH 240
IMAGE 6
CONTENTS
IX
8.3.1 METHODS OF TRADING GAIN FOR BANDWIDTH AND THE ASSOCIATED NOISE
PERFORMANCE IMPLICATIONS [8] 240
8.3.2 THE USE OF SINGLE-STAGE FEEDBACK FOR THE NOISE-GAIN-BANDWIDTH
TRADE-OFF 243
8.3.3 USE OF MULTI-STAGE FEEDBACK TO TRADE-OFF GAIN, BANDWIDTH AND NOISE
PERFORMANCE 248
REFERENCES 255
9
FREQUENCY COMPENSATION ARIE VAN STAVEREN, MICHIEL H. L. KOUWENHOVEN,
WOUTERA. SERDIJN AND CHRIS J. M. VERHOEVEN 9.1
9.2 9.3 9.4
9.5
9.6 9.7 9.8
INTRODUCTION DESIGN OBJECTIVE THE ASYMPTOTIC-GAIN MODEL THE MAXIMUM
ATTAINABLE BANDWIDTH 9.4.1 THELPPRODUCT
9.4.2 THE GROUP OF DOMINANT POLES POLE PLACEMENT 9.5.1 RESISTIVE
BROADBANDING 9.5.2 POLE-ZERO CANCELATION 9.5.3 POLE SPLITTING 9.5.4
PHANTOM ZEROS 9.5.5 ORDER OF PREFERENCE ADDING SECOND-ORDER EFFECTS
EXAMPLE DESIGN CONCLUSION REFERENCES
257
257 258 260 260 261 263 265 268 270 272 275 277 277 278 281 281
10 FREQUENCY-DYNAMIC RANGE-POWER 283
ERIC A. VITTOZ AND YANNIS P. TSIVIDIS 10.1 INTRODUCTION 283
10.2 FUNDAMENTAL LIMITS OF TRADE-OFF 284
10.2.1 ABSOLUTE LOWER BOUNDARY 284
10.2.2 FILTERS 286
10.2.3 OSCILLATORS 288
10.2.4 VOLTAGE-TO-CURRENT AND CURRENT-TO-VOLTAGE CONVERSION 292
10.2.5 CURRENT AMPLIFIERS 295
10.2.6 VOLTAGE AMPLIFIERS 297
10.3 PROCESS-DEPENDENT LIMITATIONS 299
10.3.1 PARASITIC CAPACITORS 299
10.3.2 ADDITIONAL SOURCES OF NOISE 300
10.3.3 MISMATCH OF COMPONENTS 301
10.3.4 CHARGE INJECTION 301
10.3.5 NON-OPTIMUM SUPPLY VOLTAGE 302
10.4 COMPANDING AND DYNAMIC BIASING 303
10.4.1 SYLLABIC COMPANDING 303
10.4.2 DYNAMIC BIASING 306
IMAGE 7
X
CONTENTS
10.4.3 PERFORMANCE IN THE PRESENCE OF BLOCKERS 308
10.4.4 INSTANTANEOUS COMPANDING 309
10.5 CONCLUSION 310
REFERENCES 311
FILTERS
11 TRADE-OFFS IN SENSITIVITY, COMPONENT SPREAD AND COMPONENT TOLERANCE
IN ACTIVE FILTER DESIGN 315
GEORGE MOSCHYTZ 11.1 INTRODUCTION 315
11.2 BASICS OF SENSITIVITY THEORY 316
11.3 THE COMPONENT SENSITIVITY OF ACTIVE FILTERS 319
11.4 FILTER SELECTIVITY, POLE Q AND SENSITIVITY 325
11.5 MAXIMIZING THE SELECTIVITY OF RC NETWORKS 328
11.6 SOME DESIGN EXAMPLES 332
11.7 SENSITIVITY AND NOISE 337
11.8 SUMMARY AND CONCLUSIONS 339
REFERENCES 339
12 CONTINUOUS-TIME FILTERS 341
ROBERT FOX 12.1 INTRODUCTION 341
12.2 FILTER-DESIGN TRADE-OFFS: SELECTIVITY, FILTER ORDER, POLE Q AND
TRANSIENT RESPONSE 341
12.3 CIRCUIT TRADE-OFFS 342
12.3.1 LINEARITY VS TUNEABILITY 342
12.3.2 PASSIVE COMPONENTS 342
12.3.3 TUNEABLE RESISTANCE USING MOSFETS: THE MOSFET-C APPROACH 343 12.4
THE TRANSCONDUCTANCE-C (GM-C) APPROACH 344
12.4.1 TRIODE-REGION TRANSCONDUCTORS 345
12.4.2 SATURATION-REGION TRANSCONDUCTORS 346
12.4.3 MOSFETS USED FOR DEGENERATION 346
12.4.4 BJT-BASED TRANSCONDUCTORS 347
12.4.5 OFFSET DIFFERENTIAL PAIRS 347
12.5 DYNAMIC RANGE 347
12.6 DIFFERENTIAL OPERATION 349
12.7 LOG-DOMAIN FILTERING 349
12.8 TRANSCONDUCTOR FREQUENCY-RESPONSE TRADE-OFFS 350
12.9 TUNING TRADE-OFFS 351
NO TUNING 352
OFF-CHIP TUNING 352
ONE-TIME POST-FABRICATION TUNING 352
AUTOMATIC TUNING 352
12.10 SIMULATION ISSUES 353
REFERENCES 353
IMAGE 8
CONTENTS
XI
13 INSIGHTS IN LOG-DOMAIN FILTERING 355
EMMANUEL M. DRAKAKIS ANDALISON J. BUERDEN 13.1 GENERAL 355
13.2 SYNTHESIS AND DESIGN OF LOG-DOMAIN FILTERS 360
13.3 IMPACT OF BJT NON-IDEALITIES UPON LOG-DOMAIN TRANSFER FUNCTIONS:
THE LOWPASS BIQUAD EXAMPLE 374
13.4 FLOATING CAPACITOR-BASED REALIZATION OF FINITE TRANSMISSION ZEROS
IN LOG-DOMAIN: THE IMPACT UPON LINEARITY 380
13.5 EFFECT OF MODULATION INDEX UPON INTERNAL LOG-DOMAIN CURRENT
BANDWIDTH 383 13.6 DISTORTION PROPERTIES OF LOG-DOMAIN CIRCUITS: THE
LOSSY INTEGRATOR CASE 390 13.7 NOISE PROPERTIES OF LOG-DOMAIN CIRCUITS:
THE LOSSY INTEGRATOR CASE 393
13.8 SUMMARY 401
REFERENCES 401
SWITCHED CIRCUITS
14 TRADE-OFFS IN THE DESIGN OF CMOS COMPARATORS 407
A. RODRIGUEZ-VAEZQUEZ, M. DELGADO-RESTITUTO, R. DOMINGUEZ-CASTRO, F.
MEDEIRO AND J.M. DE LA ROSA 14.1 INTRODUCTION 407
14.2 OVERVIEW OF BASIC CMOS VOLTAGE COMPARATOR ARCHITECTURES 408
14.2.1 SINGLE-STEP VOLTAGE COMPARATORS 409
14.2.2 MULTISTEP COMPARATORS 412
14.2.3 REGENERATIVE POSITIVE-FEEDBACK COMPARATORS 417
14.2.4 PRE-AMPLIFIED REGENERATIVE COMPARATORS 421
14.3 ARCHITECTURAL SPEED VS RESOLUTION TRADE-OFFS 423
14.3.1 SINGLE-STEP COMPARATORS 423
14.3.2 MULTISTEP COMPARATORS 425
14.3.3 REGENERATIVE COMPARATORS 426
14.4 ON THE IMPACT OF THE OFFSET 429
14.5 OFFSET-COMPENSATED COMPARATORS 432
14.5.1 OFFSET-COMPENSATION THROUGH DYNAMIC BIASING 433
14.5.2 OFFSET COMPENSATION IN MULTISTEP COMPARATORS 435
14.5.3 RESIDUAL OFFSET AND GAIN DEGRADATION IN SELF-BIASED COMPARATORS
436 14.5.4 TRANSIENT BEHAVIOR AND DYNAMIC RESOLUTION IN SELF-BIASED
COMPARATORS 437
14.6 APPENDIX. SIMPLIFIED MOST MODEL 438
REFERENCES 439
15 SWITCHED-CAPACITOR CIRCUITS 443
ANDREA BASCHIROTTO 15.1 INTRODUCTION 443
15.2 TRADE-OFF DUE TO SCALED CMOS TECHNOLOGY 445
15.2.1 REDUCTION OF THE MOS OUTPUT IMPEDANCE (R 0 ) 446
15.2.2 INCREASE OF THE FLICKER NOISE 447
15.2.3 INCREASE OF THE MOS LEAKAGE CURRENT 447
15.2.4 REDUCTION OF THE SUPPLY VOLTAGE 448
IMAGE 9
XU
CONTENTS
15.3 TRADE-OFF IN HIGH-FREQUENCY SC CIRCUITS 451
15.3.1 TRADE-OFF BETWEEN AN HR AND A FIR FREQUENCY RESPONSE 452
15.3.2 TRADE-OFF IN SC PARALLEL SOLUTIONS 453
15.3.3 TRADE-OFF IN THE FREQUENCY CHOICE 454
15.4 CONCLUSIONS 456
ACKNOWLEDGMENTS 456
REFERENCES 457
16 COMPATIBILITY OF SC TECHNIQUE WITH DIGITAL VLSI TECHNOLOGY 461
KRITSAPON LEELAVATTANANON AND CHRIS TOUMAZOU 16.1 INTRODUCTION 461
16.2 MONOLITHIC MOS CAPACITORS AVAILABLE IN DIGITAL VLSI PROCESSES 461
16.2.1 POLYSILICON-OVER-POLYSILICON (OR DOUBLE-POLY) STRUCTURE 462
16.2.2 POLYSILICON-OVER-DIFFUSION STRUCTURE 462
16.2.3 METAL-OVER-METAL STRUCTURE 463
16.2.4 METAL-OVER-POLYSILICON STRUCTURE 464
16.2.5 MOSFET GATE STRUCTURE 464
16.3 OPERATIONAL AMPLIFIERS IN STANDARD VLSI PROCESSES 466
16.3.1 OPERATIONAL AMPLIFIER TOPOLOGIES 466
SINGLE-STAGE (TELESCOPIC) AMPLIFIER 466
FOLDED CASCODE AMPLIFIER 466
GAIN-BOOSTING AMPLIFIER 467
TWO-STAGE AMPLIFIER 468
16.3.2 FREQUENCY COMPENSATION 469
MILLER COMPENSATION 469
MILLER COMPENSATION INCORPORATING SOURCE FOLLOWER 470
CASCODE MILLER COMPENSATION 471
16.3.3 COMMON-MODE FEEDBACK 472
16.4 CHARGE-DOMAIN PROCESSING 474
16.5 LINEARITY ENHANCED COMPOSITE CAPACITOR BRANCHES 477
16.5.1 SERIES COMPENSATION CAPACITOR BRANCH 480
16.5.2 PARALLEL COMPENSATION CAPACITOR BRANCH 482
16.5.3 BALANCED COMPENSATION CAPACITOR BRANCH 483
16.6 PRACTICAL CONSIDERATIONS 485
16.6.1 BIAS VOELTAGE MISMATCH 485
16.6.2 CAPACITOR MISMATCH 485
16.6.3 PARASITIC CAPACITANCES 486
16.7 SUMMARY 487
REFERENCES 488
17 SWITCHED-CAPACITORS OR SWITCHED-CURRENTS - WHICH WILL SUCCEED? 491
JOHN HUGHES ANDAPISAK WORAPISHET 17.1 INTRODUCTION 491
17.2 TEST VEHICLES AND PERFORMANCE CRITERIA 492
17.3 CLOCK FREQUENCY 494
17.3.1 SWITCHED-CAPACITOR SETTLING 495
17.3.2 SWITCHED-CURRENTS CLASS A SETTLING 497
17.3.3 SWITCHED-CURRENTS CLASS AB SETTLING 498
IMAGE 10
CONTENTS XIII
17.4 POWER CONSUMPTION 499
17.4.1 SWITCHED-CAPACITORS AND SWITCHED-CURRENTS CLASS A POWER
CONSUMPTION 499
17.4.2 SWITCHED-CURRENTS CLASS AB POWER CONSUMPTION 499
17.5 SIGNAL-TO-NOISE RATIO 499
17.5.1 SWITCHED-CAPACITORS NOISE 500
17.5.2 SWITCHED-CURRENTS CLASS A NOISE 503
17.5.3 SWITCHED-CURRENT CLASS AB NOISE 506
17.5.4 COMPARISON OF SIGNAL-TO-NOISE RATIOS 507
17.6 FIGURE-OF-MERIT 509
17.6.1 SWITCHED-CAPACITORS 509
17.6.2 SWITCHED-CURRENTS CLASS A 510
17.6.3 SWITCHED-CURRENTS CLASS AB 510
17.7 COMPARISON OF FIGURES-OF-MERIT 510
17.8 CONCLUSIONS 514
REFERENCES 514
OSCILLATORS
18 DESIGN OF INTEGRATED LC VCOS 517
DONHEE HARN 18.1 INTRODUCTION 517
18.2 GRAPHICAL NONLINEAR PROGRAMMING 518
18.3 LC VCO DESIGN CONSTRAINTS AND AN OBJECTIVE FUNCTION 519
18.3.1 DESIGN CONSTRAINTS 522
18.3.2 PHASE NOISE AS AN OBJECTIVE FUNCTION 522
18.3.3 PHASE NOISE APPROXIMATION 523
18.3.4 INDEPENDENT DESIGN VARIABLES 525
18.4 LC VCO OPTIMIZATION VIA GNP 526
18.4.1 EXAMPLE OF DESIGN CONSTRAINTS 527
18.4.2 GNP WITH A FIXED INDUCTOR 527
18.4.3 GNP WITH A FIXED INDUCTANCE VALUE 530
18.4.4 INDUCTANCE AND CURRENT SELECTION 533
18.4.5 SUMMARY OF THE OPTIMIZATION PROCESS 535
18.4.6 REMARKS ON FINAL ADJUSTMENT AND ROBUST DESIGN 536
18.5 DISCUSSION ON LC VCO OPTIMIZATION 537
18.6 SIMULATION 540
18.7 EXPERIMENTAL RESULTS 541
18.8 CONCLUSION 545
ACKNOWLEDGMENTS 546
REFERENCES 546
19 TRADE-OFFS IN OSCILLATOR PHASE NOISE 551
ALI HAJIMIRI 19.1 MOTIVATION 551
19.2 MEASURES OF FREQUENCY INSTABILITY 551
19.2.1 PHASE NOISE 554
19.2.2 TIMING JITTER 556
IMAGE 11
XIV
CONTENTS
19.3 PHASE NOISE MODELING 557
19.3.1 UP-CONVERSION OF 1//NOISE 562
19.3.2 TIME-VARYING NOISE SOURCES 563
19.4 PHASE NOISE TRADE-OFFS IN LC OSCILLATORS 565
19.4.1 TANK VOLTAGE AMPLITUDE 565
19.4.2 NOISE SOURCES 570
STATIONARY NOISE APPROXIMATION 570
CYCLOSTATIONARY NOISE SOURCES 572
19.4.3 DESIGN IMPLICATIONS 573
19.5 PHASE NOISE TRADE-OFFS FOR RING OSCILLATORS 574
19.5.1 THE IMPULSE SENSITIVITY FUNCTION FOR RING OSCILLATORS 574
19.5.2 EXPRESSIONS FOR PHASE NOISE IN RING OSCILLATORS 579
19.5.3 SUBSTRATE AND SUPPLY NOISE 582
19.5.4 DESIGN TRADE-OFFS IN RING OSCILLATORS 584
REFERENCES 585
DATA CONVERTERS
20 SYSTEMATIC DESIGN OF HIGH-PERFORMANCE DATA CONVERTERS 591
GEORGES GIELEN, JAN VANDENBUSSCHE, GEERT VAN DER PIAS, WALTER DAEMS,
ANNE VAN DEN BOSCH, MICHIEL STEYAERT AND WILLY SANSEN 20.1 INTRODUCTION
591
20.2 SYSTEMATIC DESIGN FLOW FOR D/A CONVERTERS 592
20.3 CURRENT-STEERING D/A CONVERTER ARCHITECTURE 594
20.4 GENERIC BEHAVIORAL MODELING FOR THE TOP-DOWN PHASE 597
20.5 SIZING SYNTHESIS OF THE D/A CONVERTER 599
20.5.1 ARCHITECTURAL-LEVEL SYNTHESIS 600
STARK PERFORMANCE 600
DYNAMIC PERFORMANCE 601
20.5.2 CIRCUIT-LEVEL SYNTHESIS 602
STATIC PERFORMANCE 602
DYNAMIC PERFORMANCE 603
20.5.3 FUELL DECODER SYNTHESIS 603
20.5.4 CLOCK DRIVER SYNTHESIS 603
20.6 LAYOUT SYNTHESIS OF THE D/A CONVERTER 603
20.6.1 FLOORPLANNING 604
20.6.2 CIRCUIT AND MODULE LAYOUT GENERATION 604
CURRENT-SOURCE ARRAY LAYOUT GENERATION 604
SWATCH ARRAY LAYOUT GENERATION 605
FUELL DECODER STANDARD CELL PLACE AND ROUTE 605
20.6.3 CONVERTER LAYOUT ASSEMBLY 606
20.7 EXTRACTED BEHAVIORAL MODEL FOR BOTTOM-UP VERIFICATION 606
20.8 EXPERIMENTAL RESULTS 607
20.9 CONCLUSIONS 610
ACKNOWLEDGMENTS 610
REFERENCES 610
IMAGE 12
CONTENTS
XV
21 ANALOG POWER MODELING FOR DATA CONVERTERS AND FILTERS 613
GEORGES GIELEN AND ERIK LAUWERS 21.1 INTRODUCTION 613
21.2 APPROACHES FOR ANALOG POWER ESTIMATORS 614
21.3 A POWER ESTIMATION MODEL FOR HIGH-SPEED NYQUIST-RATE ADCS 616
21.3.1 THE POWER ESTIMATOR DERIVATION 616
21.3.2 RESULTS OF THE POWER ESTIMATOR 619
21.4 A POWER ESTIMATION MODEL FOR ANALOG CONTINUOUS-TIME FILTERS 620
21.4.1 THE ACTIF APPROACH 620
21.4.2 DESCRIPTION OF THE FILTER SYNTHESIS PART 621
21.4.3 OTA BEHAVIORAL MODELING AND OPTIMIZATION FOR MINIMAL POWER
CONSUMPTION 624
MODELING OF THE TRANSCONDUCTANCES 624
THE DISTORTION MODEL 625
OPTIMIZATION 626
21.4.4 EXPERIMENTAL RESULTS 627
21.5 CONCLUSIONS 627
ACKNOWLEDGMENT 628
REFERENCES 628
22 SPEED VS. DYNAMIC RAENGE TRADE-OFF IN OVERSAMPLING DATA CONVERTERS 631
RICHARD SCHREIER, JESPER STEENSGAARD AND GABOR C. TEMES 22.1
INTRODUCTION 631
22.2 OVERSAMPLING DATA CONVERTERS 632
22.2.1 QUANTIZATION ERROR 632
22.2.2 FEEDBACK QUANTIZERS 633
22.2.3 OVERSAMPLING D/A CONVERTERS 636
22.2.4 OVERSAMPLING A/D CONVERTERS 639
22.2.5 MULTIBIT QUANTIZATION 640
22.3 MISMATCH SHAPING 644
22.3.1 ELEMENT ROTATION 644
22.3.2 GENERALIZED MISMATCH-SHAPING 645
22.3.3 OTHER MISMATCH-SHAPING ARCHITECTURES 649
22.3.4 PERFORMANCE COMPARISON 650
22.4 RECONSTRUCTING A SAMPLED SIGNAL 653
22.4.1 THE INTERPOLATION PROCESS 654
AN INTERPOLATION SYSTEM EXAMPLE 654
22.4.2 FUNDAMENTAL ARCHITECTURES FOR PRACTICAL IMPLEMENTATIONS 656
SINGLE-BIT DELTA-SIGMA MODULATION 657
MULTIBIT DELTA-SIGMA MODULATION 657
HIGH-RESOLUTION OVERSAMPLED D/A CONVERTERS 658
22.4.3 HIGH-RESOLUTION MISMATCH-SHAPING D/A CONVERTERS 659
A FRESH LOOK ON MISMATCH SHAPING 659
PRACTICAL IMPLEMENTATIONS 660
REFERENCES 662
IMAGE 13
XVI
CONTENTS
TRANSCEIVERS
23 POWER-CONSCIOUS DESIGN OF WIRELESS CIRCUITS AND SYSTEMS 665
ASADA. ABIDI 23.1 INTRODUCTION 665
23.2 LOWERING POWER ACROSS THE HIERARCHY 667
23.3 POWER CONSCIOUS RF AND BASEBAND CIRCUITS 668
23.3.1 DYNAMIC RANGE AND POWER CONSUMPTION 668
23.3.2 LOWERING POWER IN TUNED CIRCUITS 670
23.3.3 IMPORTANCE OF PASSIVES QUALITY IN RESONANT CIRCUITS 671
23.3.4 LOW NOISE AMPLIFIERS 673
23.3.5 OSCILLATORS 678
23.3.6 MIXERS 681
23.3.7 FREQUENCY DIVIDERS 685
23.3.8 BASEBAND CIRCUITS 686
23.3.9 ON-CHIP INDUCTORS 689
23.3.10 EXAMPLES OF LOW POWER RADIO IMPLEMENTATIONS 691
23.3.11 CONCLUSIONS: CIRCUITS 692
REFERENCES 692
24 PHOTORECEIVER DESIGN 697
MARK FORBES 24.1 INTRODUCTION 697
24.2 REVIEW OF RECEIVER STRUCTURE 698
24.3 FRONT-END SMALL-SIGNAL PERFORMANCE 700
24.3.1 SMALL-SIGNAL ANALYSIS 700
24.3.2 SPEED/SENSITIVITY TRADE-OFF 702
24.3.3 CALCULATIONS, FOR EXAMPLE, PARAMETERS 706
24.4 NOISE LIMITS 707
24.5 POST-AMPLIFIER PERFORMANCE 709
24.6 FRONT-END AND POST-AMPLIFIER COMBINED TRADE-OFF 712
24.7 MISMATCH 714
24.8 CONCLUSIONS 718
ACKNOWLEDGMENTS 718
REFERENCES 719
25 ANALOG FRONT-END DESIGN CONSIDERATIONS FOR DSL 723
NIANXIONG NICK TAN 25.1 INTRODUCTION 723
25.2 SYSTEM CONSIDERATIONS 725
25.2.1 DIGITAL VS ANALOG PROCESS 725
25.2.2 ACTIVE VS PASSIVE FILTERS 726
25.3 DATA CONVERTER REQUIREMENTS FOR DSL 728
25.3.1 OPTIMUM DATA CONVERTERS FOR ADSL 732
OPTIMUM ADCS FOR ADSL 732
OPTIMUM ADC FOR ADSL-CO 734
OPTIMUM ADC FOR ADSL-CP 735
IMAGE 14
CONTENTS
XVII
OPTIMUM DACS 735
OPTIMUM DAC FOR ADSL-CO 737
OPTIMUM DAC FOR ADSL-CP 737
25.3.2 FUNCTION OFFILTERING 738
25.4 CIRCUIT CONSIDERATIONS 740
25.4.1 OVERSAMPLING VS NYQUIST DATA CONVERTERS 740
25.4.2 SI VS SC 743
25.4.3 SAMPLED-DATA VS CONTINUOUS-TIME FILTERS 743
25.4.4 GM-C VS RC FILTERE 744
25.5 CONCLUSIONS 744
ACKNOWLEDGMENTS 745
REFERENCES 745
26 LOW NOISE DESIGN 747
MICHIEL H. L KOUWENHOVEN, ARIE VAN STAVEREN, WOUTERA. SERDIJN AND CHRIS
J. M. VERHOEVEN 26.1 INTRODUCTION 747
26.2 NOISE ANALYSIS TOOLS 747
26.2.1 EQUIVALENT NOISE SOURCE 748
26.2.2 TRANSFORM-I: VOLTAGE SOURCE SHIFT 749
26.2.3 TRANSFORM-II: CURRENT SOURCE SHIFT 749
26.2.4 TRANSFORM-III: NORTON-THEVENIN TRANSFORM 749
26.2.5 TRANSFORM-IV: SHIFT THROUGH TWOPORTS 750
26.3 LOW-NOISE AMPLIFIER DESIGN 751
26.3.1 DESIGN OF THE FEEDBACK NETWORK 752
NOISE PRODUCTION BY THE FEEDBACK NETWORK 753
MAGNIFICATION OF NULLOR NOISE 754
DISTORTION INCREMENT AND BANDWIDTH REDUCTION 755
26.3.2 DESIGN OF THE ACTIVE PART FOR LOW NOISE 756
26.3.3 NOISE OPTIMIZATIONS 757
NOISE MATCHING TO THE SOURCE 757
OPTIMIZATION OF THE BIAS CURRENT 759
CONNECTING STAGES IN SERIES/PARALLEL 760
SUMMARY OF OPTIMIZATIONS 761
26.4 LOW NOISE HARMONIE RESONATOR OSCIUATOR DESIGN 762
26.4.1 GENERAL STRUCTURE OF A RESONATOR OSCIUATOR 762
26.4.2 NOISE CONTRIBUTION OF THE RESONATOR 763
26.4.3 DESIGN OF THE UNDAMPING CIRCUIT FOR LOW NOISE 764
PRINCIPLE IMPLEMENTATION OF THE UNDAMPING CIREUIT 765
AMPLITUDE CONTROL 765
NOISE PERFORMANCE 766
DRIVING THE OSCILLATOR LOAD 766
26.4.4 NOISE MATCHING OF THE RESONATOR AND UNDAMPING CIRCUIT: TAPPING
767 26.4.5 POWER MATCHING 769
26.4.6 COUPLED RESONATOR OSCILLATORS 770
26.5 LOW-NOISE RELAXATION OSCILLATOR DESIGN 772
26.5.1 PHASE NOISE IN RELAXATION OSCILLATORS 773
SIMPLE PHASE NOISE MODEL 773
IMAGE 15
XV111
CONTENTS
INFLUENCE OF THE MEMORY ON THE OSCILLATOR PHASE NOISE 774
INFLUENCE OF COMPARATORS ON THE OSCILLATOR PHASE NOISE 776
26.5.2 IMPROVEMENT OF THE NOISE BEHAVIOR BY ALTERNATIVE TOPOLOGIES 777
RELAXATION OSCILLATORS WITH MEMORY BYPASS 778
COUPLED RELAXATION OSCILLATORS 780
REFERENCES 784
27 TRADE-OFFS IN CMOS MIXER DESIGN 787
GANESH KATHIRESAN AND CHRIS TOUMAZOU 27.1 INTRODUCTION 787
27.1.1 THE RF RECEIVER RE-VISITED 788
27.2 SOME MIXER BASICS 789
27.2.1 MIXERS VS MULTIPLIERS 789
27.2.2 MIXERS: NONLINEAR OR LINEAR-TIME-VARIANT? 791
27.3 MIXER FIGURES OF MERIT 792
27.3.1 CONVERSION GAIN AND BANDWIDTH 793
27.3.2 1 DB COMPRESSION POINT 794
27.3.3 THIRD-ORDER INTERCEPT POINT 796
27.3.4 NOISE FIGURE 797
27.3.5 PORT-TO-PORT ISOLATION 799
27.3.6 COMMON MODE REJECTION, POWER SUPPLY, ETC 799
27.4 MIXER ARCHITECTURES AND TRADE-OFFS 800
27.4.1 SINGLE BALANCED DIFFERENTIAL PAIR MIXER 800
27.4.2 DOUBLE-BALANCED MIXER AND ITS CONVERSION GAIN 803
27.4.3 SUPPLY VOLTAGE 805
ACTIVE LOADS 805
INDUCTIVE CURRENT SOURCE 805
TWO STACK SOURCE COUPLED MIXER 806
BULK DRIVEN TOPOLOGIES 807
27.4.4 LINEARITY 809
SOURCE DEGENERATION 809
S WITCHED MOSFET DEGENERATION 811
27.4.5 LO FEEDTHROUGH 812
27.4.6 MIXER NOISE 813
NOISE DUE TO THE LOAD 814
NOISE DUE TO THE INPUT TRANSCONDUCTOR 814
NOISE DUE TO THE SWITCHES 815
27.5 CONCLUSION 817
REFERENCES 817
28 A HIGH-PERFORMANCE DYNAMIC-LOGIC PHASE-FREQUENCY DETECTOR 821
SHENGGAO LI AND MOHAMMED ISMAIL 28.1 INTRODUCTION 821
28.2 PHASE DETECTORS REVIEW 822
28.2.1 MULTIPLIER 822
28.2.2 EXCLUSIVE-OR GATE 823
IMAGE 16
CONTENTS
XIX
28.2.3 JK-FLIPFLOP 825
28.2.4 TRI-STATE PHASE DETECTOR 825
28.3 DESIGN ISSUES IN PHASE-FREQUENCY DETECTORS 827
28.3.1 DEAD-ZONE 827
28.3.2 BLIND-ZONE 829
28.4 DYNAMIC LOGIC PHASE-FREQUENCY DETECTORS 831
28.5 A NOVEL DYNAMIC-LOGIC PHASE-FREQUENCY DETECTOR 835
28.5.1 CIRCUIT OPERATION 836
28.5.2 PERFORMANCE EVALUATION 837
28.6 CONCLUSION 842
REFERENCES 842
29 TRADE-OFFS IN POWER AMPLIFIERS 843
CHUNG KEI THOMAS CHAN, STEVE HUNG-LUNG TU AND CHRIS TOUMAZOU 29.1
INTRODUCTION 843
29.2 CLASSIFICATION OF POWER AMPLIFIERS 845
29.2.1 CURRENT-SOURCE POWER AMPLIFIERS 845
29.2.2 SWITCH-MODE POWER AMPLIFIERS 848
CLASS D POWER AMPLILIER 848
CLASS E POWER AMPUTIER 849
CLASS F POWER AMPUTIER 850
29.2.3 BANDWIDTH ELLICIENCY. POWER EFFICIENCY AND LINEARITY 852
29.3 EFFECT OF LOADED SS-FACIOR ON CLASS E POWER AMPLIFIERS 853
29.3.1 CIRCUIT ANAKSIS 853
29.3.2 POWER ELLICIENCY 857
29.3.3 CIRCUIT SIMULATION AND DISCUSSION 858
29.4 CLASS E POWER AMPLIFIERS WITH NONLINEAR SHUNT CAPACITANCE 861
29.4.1 NUMERICAL C OMPULATION OF OPTIMUM COMPONENT VALUES 863
BASIC EQUATIONS 863
OPTIMUM OPERATION ALINIKULA S METHOD [16]) 865
FOURIER ANALYSIS 869
NORMALIZED POWER CAPAHILITY 869
29.4.2 GENERALI/ED NUMERICAL METHOD 870
DESIGN EXAMPLE 872
SMALL LINEAR SHUNL CAPACITOR 872
29.5 CONCLUSION 878
REFERENCES 880
NEURAL PROCESSING
30 TRADE-OFFS IN STANDARD AND UNIVERSAL CNN CELLS 883
MARTIN HAENGGI, RADU DOGARU AND LEON O. CHUA 30.1 INTRODUCTION 883
30.2 THE STANDARD CNN 884
30.2.1 CIRCUIT IMPLEMENTATION OFCNNS 886
30.3 STANDARD CNN CELLS: ROBUSTNESS VS PROCESSING SPEED 887
30.3.1 RELIABILITY OF A STANDARD CNN 887
IMAGE 17
XX
CONTENTS
INTRODUCTION 887
ABSOLUTE AND RELATIVE ROBUSTNESS 888
THE ROBUSTNESS OF A CNN TEMPLATE SET 888
TEMPLATE SCALING 890
TEMPLATE DESIGN 890
30.3.2 THE SETTLING TIME OF A STANDARD CNN 892
INTRODUCTION 892
THE EXACT APPROACH FOR UNCOUPLED CNNS 893
30.3.3 ANALYSIS OF PROPAGATION-TYPE TEMPLATES 893
INTRODUCTION 893
EXAMPLES OF PROPAGATION-TYPE TEMPLATES 894
30.3.4 ROBUST CNN ALGORITHMS FOR HIGH-CONNECTIVITY TASKS 897
TEMPLATE CLASSES 898
ONE-STEP VS ALGORITHMIC PROCESSING 900
30.3.5 CONCLUDING REMARKS 901
30.4 UNIVERSAL CNN CELLS AND THEIR TRADE-OFFS 902
30.4.1 PRELIMINARIES 902
30.4.2 PYRAMIDAL CNN CELLS 904
ARCHITECTURE 904
TRADE-OFFS 905
30.4.3 CANONICAL PIECEWISE-LINEAR CNN CELLS 906
CHARACTERIZATION AND ARCHITECTURE 906
TRADE-OFFS 907
EXAMPLE 908
30.4.4 THE MULTI-NESTED UNIVERSAL CNN CELL 909
ARCHITECTURE AND CHARACTERIZATION 909
TRADE-OFFS 910
30.4.5 AN RTD-BASED MULTI-NESTED UNIVERSAL CNN CELL CIRCUIT 914
30.4.6 CONCLUDING REMARKS 917
REFERENCES 918
ANALOG CAD
31 TOP-DOWN DESIGN METHODOLOGY FOR ANALOG CIRCUITS USING MATLAB AND
SIMULINK 923 NAVEEN CHANDRA AND GORDON W. ROBERTS 31.1 INTRODUCTION 923
31.2 DESIGN METHODOLOGY MOTIVATION 925
31.2.1 OPTIMIZATION PROCEDURE 926
31.3 SWITCHED CAPACITOR DELTA-SIGMA DESIGN PROCEDURE 927
31.3.1 SWITCHED SAMPLED CAPACITOR (KT/C) NOISE 928
31.3.2 OTA PARAMETERS 929
31.4 MODELING OF A S MODULATORS IN SIMULINK 929
31.4.1 SAMPLED CAPACITOR (KT/C) NOISE 930
31.4.2 OTA NOISE 931
31.4.3 SWITCHED CAPACITOR INTEGRATOR NON-IDEALITIES 932
31.5 OPTIMIZATION SETUP 938
31.5.1 IMPLEMENTATION IN MATLAB 941
31.5.2 INITIAL CONDITIONS 943
31.5.3 ADDITIONAL FACTORS 945
IMAGE 18
CONTENTS
XXI
31.6 SUMMARY OF SIMULATION RESULTS 945
31.7 A FULLY CODED A E MODULATOR DESIGN EXAMPLE 946
31.8 CONCLUSION 950
REFERENCES 951
32 TECHNIQUES AND APPLICATIONS OF SYMBOLIC ANALYSIS FOR ANALOG
INTEGRATED CIRCUITS 953 GEORGES GIELEN 32.1 INTRODUCTION 953
32.2 WHAT IS SYMBOLIC ANALYSIS? 953
32.2.1 DEFINITION OF SYMBOLIC ANALYSIS 953
32.2.2 BASIC METHODOLOGY OF SYMBOLIC ANALYSIS 956
32.3 APPLICATIONS OF SYMBOLIC ANALYSIS 958
32.3.1 INSIGHT INTO CIRCUIT BEHAVIOR 958
32.3.2 ANALYTIC MODEL GENERATION FOR AUTOMATED ANALOG CIRCUIT SIZING 960
32.3.3 INTERACTIVE CIRCUIT EXPLORATION 961
32.3.4 REPETITIVE FORMULA EVALUATION 961
32.3.5 ANALOG FAULT DIAGNOSIS 962
32.3.6 BEHAVIORAL MODEL GENERATION 963
32.3.7 FORMAL VERIFICATION 964
32.3.8 SUMMARY OF APPLICATIONS 965
32.4 PRESENT CAPABILITIES AND LIMITATIONS OF SYMBOLIC ANALYSIS 965
32.4.1 SYMBOLIC APPROXIMATION 966
32.4.2 IMPROVING COMPUTATIONAL EFFICIENCY 968
32.4.3 SIMPLIFICATION DURING GENERATION 969
32.4.4 SIMPLIFICATION BEFORE GENERATION 971
32.4.5 HIERARCHICAL DECOMPOSITION 971
32.4.6 SYMBOLIC POLE-ZERO ANALYSIS 974
32.4.7 SYMBOLIC DISTORTION ANALYSIS 974
32.4.8 OPEN RESEARCH TOPICS 976
32.5 COMPARISON OF SYMBOLIC SIMULATORS 976
32.6 CONCLUSIONS 977
ACKNOWLEDGMENTS 979
REFERENCES 979
33 TOPICS IN IC LAYOUT FOR MANUFACTURE 985
BARRIE GILBERT 33.1 LAYOUT: THE CRUCIAL NEXT STEP 985
33.1.1 AN ARCHITECTURAL ANALOGY 988
33.1.2 IC LAYOUT: A MATTER OF DRAFTING ? 989
33.1.3 A SHARED UNDERTAKING 992
33.1.4 WHAT INPUTS SHOULD THE LAYOUTEER EXPECT? 993
33.2 INTERCONNECTS 996
33.2.1 METAL LIMITATIONS 998
33.2.2 OTHER METALIZATION TRADE-OFFS 1000
33.3 SUBSTRATES AND THE MYTH OF GROUND 1006
33.3.1 DEVICE-LEVEL SUBSTRATE NODES 1009
33.4 STARTING AN ANALOG LAYOUT 1010
IMAGE 19
XX11
CONTENTS
33.5 DEVICE MATCHING 1012
33.5.1 THE BIGGEST-OF-ALL LAYOUT TRADE-OFF 1015
33.5.2 MATCHING RULES FOR SPECIFIC COMPONENTS 1016
33.5.3 CAPACITOR MATCHING 1018
33.5.4 CIRCUIT/LAYOUT SYNERGY 1020
33.6 LAYOUT OF SILICON-ON-INSULATOR PROCESSES 1024
33.6.1 CONSEQUENCES OF HIGH THERMAL RESISTANCE 1028
33.7 REFLECTIONS ON SUPERINTEGRATED LAYOUT 1029
INDEX 1033
|
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| id | DE-604.BV014547859 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T19:03:22Z |
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| language | English |
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| physical | XXXV, 1048 Ill., graph. Darst. |
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| spelling | Trade-offs in analog circuit design the designer's companion ed. by Chris Toumazou ... Boston [u.a.] Kluwer Academic Publishers 2002 XXXV, 1048 Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Electronic circuit design Engineering economy Analoge integrierte Schaltung (DE-588)4112519-8 gnd rswk-swf Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf Analoge integrierte Schaltung (DE-588)4112519-8 s Schaltungsentwurf (DE-588)4179389-4 s DE-604 Toumazou, Chris Sonstige oth Moschytz, George S. Sonstige oth Gilbert, Barrie Sonstige oth GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009892044&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Trade-offs in analog circuit design the designer's companion Electronic circuit design Engineering economy Analoge integrierte Schaltung (DE-588)4112519-8 gnd Schaltungsentwurf (DE-588)4179389-4 gnd |
| subject_GND | (DE-588)4112519-8 (DE-588)4179389-4 |
| title | Trade-offs in analog circuit design the designer's companion |
| title_auth | Trade-offs in analog circuit design the designer's companion |
| title_exact_search | Trade-offs in analog circuit design the designer's companion |
| title_full | Trade-offs in analog circuit design the designer's companion ed. by Chris Toumazou ... |
| title_fullStr | Trade-offs in analog circuit design the designer's companion ed. by Chris Toumazou ... |
| title_full_unstemmed | Trade-offs in analog circuit design the designer's companion ed. by Chris Toumazou ... |
| title_short | Trade-offs in analog circuit design |
| title_sort | trade offs in analog circuit design the designer s companion |
| title_sub | the designer's companion |
| topic | Electronic circuit design Engineering economy Analoge integrierte Schaltung (DE-588)4112519-8 gnd Schaltungsentwurf (DE-588)4179389-4 gnd |
| topic_facet | Electronic circuit design Engineering economy Analoge integrierte Schaltung Schaltungsentwurf |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009892044&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT toumazouchris tradeoffsinanalogcircuitdesignthedesignerscompanion AT moschytzgeorges tradeoffsinanalogcircuitdesignthedesignerscompanion AT gilbertbarrie tradeoffsinanalogcircuitdesignthedesignerscompanion |