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VHDL: programming by example

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Bibliographische Detailangaben
1. Verfasser:	Perry, Douglas L. (VerfasserIn)
Format:	Buch
Sprache:	English
Veröffentlicht:	New York [u.a.] McGraw-Hill 2002
Ausgabe:	4. ed.
Schlagworte:	VHDL (Computer hardware description language) VHDL
Online-Zugang:	Publisher description Table of contents Inhaltsverzeichnis
Beschreibung:	Includes index.
Beschreibung:	XVII, 476 S. graph. Darst. 1 CD-ROM (12 cm)
ISBN:	0071400702

Internformat

MARC


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Datensatz im Suchindex

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adam_text	Titel: VHDL Autor: Perry, Douglas L Jahr: 2002 1 2 3 3 4 5 6 6 7 8 9 9 9 10 10 11 11 12 15 16 20 20 21 22 23 23 27 27 28 29 31 35 CONTENTS Foreword xiii Preface xv Acknowledgments xviii Chapter 1 Introduction to VHDL VHDL Terms Describing Hardware in VHDL Entity Architectures Concurrent Signal Assignment Event Scheduling Statement Concurrency Structural Designs Sequential Behavior Process Statements Process Declarative Region Process Statement Part Process Execution Sequential Statements Architecture Selection Configuration Statements Power of Configurations Chapter 2 Behavioral Modeling Introduction to Behavioral Modeling Transport Versus Inertial Delay Inertial Delay Transport Delay Inertial Delay Model Transport Delay Model Simulation Deltas Drivers Driver Creation Bad Multiple Driver Model Generics Block Statements Guarded Blocks Contents Chapter 3 Sequential Processing Process Statement Sensitivity List Process Example Signal Assignment Versus Variable Assignment Incorrect Mux Example Correct Mux Example Sequential Statements t IF Statements CASE Statements LOOP Statements NEXT Statement EXIT Statement ASSERT Statement Assertion BNF WAIT Statements WAIT ON Signal WAIT UNTIL Expression WAIT FOR time_expression Multiple WAIT Conditions WAIT Time-Out Sensitivity List Versus WAIT Statement Concurrent Assignment Problem Passive Processes Chapter 4 Data Types Object Types Signal Variables Constants Data Types Scalar Types Composite Types Incomplete Types File Types File Type Caveats Subtypes Chapter 5 Subprograms and Packages Subprograms Function 39 40 40 40 42 43 45 46 47 48 50 53 54 56 57 59 62 62 62 63 64 66 67 70 73 74 74 76 77 78 79 86 98 102 105 105 109 110 110 Contents yjj Conversion Functions 1i3 Resolution Functions 119 Procedures 133 Packages 135 Package Declaration 136 Deferred Constants 136 Subprogram Declaration 137 Package Body 138 Chapter 6 Predefined Attributes 143 Value Kind Attributes 144 Value Type Attributes 144 Value Array Attributes 147 Value Block Attributes 149 Function Kind Attributes 151 Function Type Attributes 151 Function Array Attributes 154 Function Signal Attributes 156 Attributes EVENT and LAST.VALUE 157 Attribute LAST_EVENT 158 Attribute ACTIVE and LAST_ACTIVE 160 Signal Kind Attributes 160 Attribute DELAYED 161 Attribute STABLE 164 Attribute QUIET 166 Attribute TRANSACTION 168 Type Kind Attributes 169 Range Kind Attributes 170 Chapter 7 Configurations 173 Default Configurations 174 Component Configurations 176 Lower-Level Configurations 179 Entity-Architecture Pair Configuration 180 Port Maps 181 Mapping Library Entities 183 Generics in Configurations 185 Generic Value Specification in Architecture 188 Generic Specifications in Configurations 190 Board-Socket-Chip Analogy 195 Block Configurations 199 Architecture Configurations 201 viii Contents Chapter 8 Advanced Topics Overloading 206 Subprogram Overloading 206 Overloading Operators 2,0 Aliases 215 Qualified Expressions 2 5 User-Defined Attributes 2 ® Generate Statements 220 Irregular Generate Statement 222 TextIO 224 Chapter 9 Synthesis 231 Register Transfer Level Description 232 Constraints 237 Timing Constraints 238 Clock Constraints 238 Attributes 239 Load 240 Drive 240 Arrival Time 240 Technology Libraries 241 Synthesis 243 Translation 243 Boolean Optimization 244 Flattening 245 Factoring 246 Mapping to Gates 247 Chapter 10 VHDL Synthesis 251 Simple Gate — Concurrent Assignment 252 IF Control Flow Statements 253 Case Control Flow Statements 256 Simple Sequential Statements 257 Asynchronous Reset 259 Asynchronous Preset and Clear 261 More Complex Sequential Statements 262 Four-Bit Shifter 264 State Machine Example 266 Contents Chapter 11 High Level Design Flow 273 RTL Simulation 275 VHDL Synthesis 277 Functional Gate-Level Verification 283 Place and Route 284 Post Layout Timing Simulation 286 Static Timing 287 Chapter 12 Top-Level System Design 289 CPU Design 290 Top-Level System Operation 290 Instructions 291 Sample Instruction Representation 292 CPU Top-Level Design 293 Block Copy Operation 299 Chapter 13 CPU: Synthesis Description 303 ALU 306 Comp 309 Control 311 Reg 321 Regarray 322 Shift 324 Trireg 326 Chapter 14 CPU: RTL Simulation 329 Testbenches 330 Kinds of Testbenches 331 Stimulus Only 333 Full Testbench 337 Simulator Specific 340 Hybrid Testbenches 342 Fast Testbench 345 CPU Simulation 349 Chapter 15 CPU Design: Synthesis Results 357 X Chapter 16 Place and Route Place and Route Process Placing and Routing the Device Setting up a project Chapter 17 CPU: VITAL Simulation VITAL Library VITAL Simulation Process Overview VITAL Implementation Simple VITAL Model VITAL Architecture Wire Delay Section Flip-Flop Example SDF File VITAL Simulation Back-Annotated Simulation Chapter 18 At Speed Debugging Techniques Instrumentor Debugger Debug CPU Design Create Project Specify Top-Level Parameters Specify Project Parameters Instrument Signals Write Instrumented Design Implement New Design Start Debug Enable Breakpoint Trigger Position Waveform Display Set Watchpoint Complex Triggers Appendix A Standard Logic Package Appendix B VHDL Reference Tables Appendix C Reading VHDL BNF Contents 369 370 373 373 379 381 382 382 383 386 386 388 392 394 397 399 401 401 401 402 403 403 404 405 405 406 406 408 408 409 410 413 435 445 Contents ^j Appendix D VHDL93 Updates 449 Alias 449 Attribute Changes 450 Bit String Literal 452 DELAYJ.ENGTH Subtype 452 Direct Instantiation 452 Extended Identifiers 453 File Operations 454 Foreign Interface 455 Generate Statement Changes 456 Globally Static Assignment 456 Groups 457 Incremental Binding 458 Postponed Process 459 Pure and Impure Functions 460 Pulse Reject 460 Report Statement 461 Shared Variables 461 Shift Operators 463 SLL—shift left logical 463 SRL—shift right logical 463 SLA—shift left arithmetic 463 SRA—shift right arithmetic 463 ROL—rotate left 464 ROR — rotate right 464 Syntax Consistency 464 Unaffected 466 XIMOR Operator 466 Index 469 About the Author 477
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dewey-full	621.39/2
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discipline	Informatik Elektrotechnik / Elektronik / Nachrichtentechnik
edition	4. ed.
format	Book
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spelling	Perry, Douglas L. Verfasser aut VHDL programming by example Douglas L. Perry 4. ed. New York [u.a.] McGraw-Hill 2002 XVII, 476 S. graph. Darst. 1 CD-ROM (12 cm) txt rdacontent n rdamedia nc rdacarrier Includes index. VHDL (Computer hardware description language) VHDL (DE-588)4254792-1 gnd rswk-swf VHDL (DE-588)4254792-1 s DE-604 http://www.loc.gov/catdir/description/mh022/2002070962.html Publisher description http://www.loc.gov/catdir/toc/mh023/2002070962.html Table of contents HBZ Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009883420&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis
spellingShingle	Perry, Douglas L. VHDL programming by example VHDL (Computer hardware description language) VHDL (DE-588)4254792-1 gnd
subject_GND	(DE-588)4254792-1
title	VHDL programming by example
title_auth	VHDL programming by example
title_exact_search	VHDL programming by example
title_full	VHDL programming by example Douglas L. Perry
title_fullStr	VHDL programming by example Douglas L. Perry
title_full_unstemmed	VHDL programming by example Douglas L. Perry
title_short	VHDL
title_sort	vhdl programming by example
title_sub	programming by example
topic	VHDL (Computer hardware description language) VHDL (DE-588)4254792-1 gnd
topic_facet	VHDL (Computer hardware description language) VHDL
url	http://www.loc.gov/catdir/description/mh022/2002070962.html http://www.loc.gov/catdir/toc/mh023/2002070962.html http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009883420&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
work_keys_str_mv	AT perrydouglasl vhdlprogrammingbyexample

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