Proceedings: December 1 - 5, 2001, Austin, Texas, USA
Gespeichert in:
Körperschaft: | |
---|---|
Format: | Tagungsbericht Buch |
Sprache: | English |
Veröffentlicht: |
Los Alamitos, Calif. [u.a.]
IEEE Computer Soc.
2001
|
Schlagworte: | |
Online-Zugang: | Inhaltsverzeichnis |
Beschreibung: | XV, 340 S. Ill., graph. Darst. |
ISBN: | 0769513697 |
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Datensatz im Suchindex
_version_ | 1804129098486775808 |
---|---|
adam_text | 34th Annual International Symposium on Microarchitecture
—
MICRO-34
Message from the General Chair
...............................................................................................................................ix
Message from the Program Chairs
.......................................................................................................*......................
χ
Committees
................................................................................................................................................................xi
Reviewers
................................................................................................................................................................xiii
Keynote
Fifty Years of Microarchitecture
................................................................................................................................2
H. Cragon
Session I
:
Novel Ideas
Skipper: A Microarchitecture for Exploiting Control-Flow Independence
................................................................4
С
Cher and
T.
Vijaykumar
Performance Characterization of a Hardware Mechanism for Dynamic Optimization
............................................16
B. Fahs, S.
Bose,
M.
Crum,
В.
Šlechta,
F.
Spadini,
T. Tung,
S.
Patel,
and S.
Lametta
Using
Variable-MHz
Microprocessors to Efficiently Handle Uncertainty in Real-Time Systems
...........................28
E.
Rotenberg
A Design Space Evaluation of Grid Processor Architectures
...................................................................................40
R. Nagarajan, K. Sankaralingam, D. Burger, and S. Keckler
Session
2:
Memory Hierarchies
Reducing Set-Associative Cache Energy via Way-Prediction and Selective Direct-Mapping
.................................54
M. Powell, A. Agrawal, T. Vijaykumar, B. Falsafi, and K. Roy
A Code Decompression Architecture for VLIW Processors
....................................................................................66
Y. Xie, W. Wolf, and H. Lekatsas
Direct Load: Dependence-Linked Dataflow Resolution of Load Address and Cache Coordinate
...........................76
B. Chung, J. Zhang, J. Peir, S. Lai, and K. Lai
Session
3:
Energy Efficient
Architectures
Reducing Power Requirements of Instruction Scheduling through Dynamic Allocation of Multiple
Datapath Resources
..................................................................................................................................................90
D. Ponomarev, G. Kucuk, and K. Ghose
Exploiting VLIW Schedule Slacks for Dynamic and Leakage Energy Reduction
.................................................102
W. Zhang,
N.
Vijaykrishnan, M. Kandemir, M.
Irwin,
D. Duarte,
and
Y. Tsai
Reducing Power with Dynamic Critical Path Information
.....................................................................................1
14
J. Seng, E. Tune, and D. Tullsen
Direct Addressed Caches for Reduced Power Consumption
..................................................................................124
E. Witchel, S. Larsen,
С
Ananian, and K.
Asanović
Keynote
Emerging Applications for the Connected Home
...................................................................................................136
A. Wolfe
Session
4:
Modulo Scheduling
Modulo Schedule Buffers
.......................................................................................................................................138
M.
Merten
and W. Hwu
Graph-Partitioning Based Instruction Scheduling for Clustered Processors
...........................................................150
A. Aletà,
J.
Codina,
J.
Sánchez,
and A. Gonzalez
Modulo Scheduling with Integrated Register Spilling for Clustered VLIW Architectures
....................................160
J.
Zalamea,
J.
Llosa,
E
Ay
guade, and
M. Valero
Session
5:
Compilation
Efficient Static
Single
Assignment Form for Predication
.......................................................................................172
A. Stoutchinin and
F. de Fernere
The Impact of
If-Conversion
and Branch Prediction on Program Execution on the Intel® Itanium™ Processor...
182
Y. Choi, A.
Knies,
L
Gerke, and T. Ngai
Mapping Reference Code to Irregular DSPs within the Retargetable, Optimizing Compiler COGENCT)
.............192
G. GréwalandC.
Wilson
Session
6:
Superscalar Architectures
Select-Free Instruction Scheduling Logic
...............................................................................................................204
M. Brown, J. Stark, and Y.
Patt
Dual Use of Superscalar Datapath for Transient-Fault Detection and Recovery
....................................................214
J. Ray, J. Hoe, and B. Falsafi
A High-Speed Dynamic Instruction Scheduling Scheme for Superscalar Processors
............................................225
M. Goshima, K. Nishino, Y. Nakashima, S. Mori, T. Kitamura, and S.
Tornita
Reducing the Complexity of the Register File in Dynamic Superscalar Processors
...............................................237
R. Balasubramonian, S. Dwarkadas, and D. Albonesi
Session Tz Multimedia and Graphics
Saving Energy with Architectural and Frequency Adaptations for Multimedia Applications
................................250
С
Hughes, J. Srinivasan, and S. Adve
vi
Enhancing Loop Buffering of Media and Telecommunications Applications using
Low-Overhead Predication
.....................................................................................................................................262
J.
Sias,
H.
Hunter, and W. Hwu
Cool-Cache for Hot Multimedia
.............................................................................................................................274
O. Unsal, R. Ashok, I.
Koren, C.
Krishna, and
C. Moritz
7R: A
3D
API Transparent Technology for Chunk Rendering
..............................................................................284
E. Hsieh, V. Pentkovski, and T. Piazza
ision
8:
Multithreading and
Value Prediction
Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution
................................................294
R. Rajwar and J. Goodman
Dynamic Speculative Precomputation
....................................................................................................................306
J. Collins, D. Tullsen, H. Wang, andJ. Shen
Handling Long-latency Loads in a Simultaneous Multithreading Processor
..........................................................318
D. Tullsen and J. Brown
Correctly Implementing Value Prediction in Microprocessors that
Support Multithreading or Multiprocessing
............................................................................................................328
M. Martin, D.
Sorin,
H.
Cain,
M.
Hill, and
M.
Upasti
Index of Authors
.....................................................................................................................................................339
VII
|
any_adam_object | 1 |
author_corporate | Micro Austin, Tex |
author_corporate_role | aut |
author_facet | Micro Austin, Tex |
author_sort | Micro Austin, Tex |
building | Verbundindex |
bvnumber | BV014213729 |
classification_rvk | SS 2001 ST 150 |
classification_tum | DAT 200f |
ctrlnum | (OCoLC)635710816 (DE-599)BVBBV014213729 |
discipline | Informatik |
format | Conference Proceeding Book |
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spelling | Micro 34 2001 Austin, Tex. Verfasser (DE-588)10034230-9 aut Proceedings December 1 - 5, 2001, Austin, Texas, USA 34th ACM IEEE International Symposium on Microarchitecture MICRO-34 Proceedings of the 34th Annual International Symposium on Microarchitecture Los Alamitos, Calif. [u.a.] IEEE Computer Soc. 2001 XV, 340 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Mikroprogrammierung (DE-588)4039231-4 gnd rswk-swf Mikroarchitektur (DE-588)4139308-9 gnd rswk-swf Computerarchitektur (DE-588)4048717-9 gnd rswk-swf Mikroprozessor (DE-588)4039232-6 gnd rswk-swf Parallelverarbeitung (DE-588)4075860-6 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 2001 Austin Tex. gnd-content Mikroarchitektur (DE-588)4139308-9 s DE-604 Mikroprozessor (DE-588)4039232-6 s 1\p DE-604 Computerarchitektur (DE-588)4048717-9 s 2\p DE-604 Mikroprogrammierung (DE-588)4039231-4 s 3\p DE-604 Parallelverarbeitung (DE-588)4075860-6 s 4\p DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009745612&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 4\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
spellingShingle | Proceedings December 1 - 5, 2001, Austin, Texas, USA Mikroprogrammierung (DE-588)4039231-4 gnd Mikroarchitektur (DE-588)4139308-9 gnd Computerarchitektur (DE-588)4048717-9 gnd Mikroprozessor (DE-588)4039232-6 gnd Parallelverarbeitung (DE-588)4075860-6 gnd |
subject_GND | (DE-588)4039231-4 (DE-588)4139308-9 (DE-588)4048717-9 (DE-588)4039232-6 (DE-588)4075860-6 (DE-588)1071861417 |
title | Proceedings December 1 - 5, 2001, Austin, Texas, USA |
title_alt | MICRO-34 Proceedings of the 34th Annual International Symposium on Microarchitecture |
title_auth | Proceedings December 1 - 5, 2001, Austin, Texas, USA |
title_exact_search | Proceedings December 1 - 5, 2001, Austin, Texas, USA |
title_full | Proceedings December 1 - 5, 2001, Austin, Texas, USA 34th ACM IEEE International Symposium on Microarchitecture |
title_fullStr | Proceedings December 1 - 5, 2001, Austin, Texas, USA 34th ACM IEEE International Symposium on Microarchitecture |
title_full_unstemmed | Proceedings December 1 - 5, 2001, Austin, Texas, USA 34th ACM IEEE International Symposium on Microarchitecture |
title_short | Proceedings |
title_sort | proceedings december 1 5 2001 austin texas usa |
title_sub | December 1 - 5, 2001, Austin, Texas, USA |
topic | Mikroprogrammierung (DE-588)4039231-4 gnd Mikroarchitektur (DE-588)4139308-9 gnd Computerarchitektur (DE-588)4048717-9 gnd Mikroprozessor (DE-588)4039232-6 gnd Parallelverarbeitung (DE-588)4075860-6 gnd |
topic_facet | Mikroprogrammierung Mikroarchitektur Computerarchitektur Mikroprozessor Parallelverarbeitung Konferenzschrift 2001 Austin Tex. |
url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009745612&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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