Analysis and design of analog integrated circuits:
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| Format: | Book |
|---|---|
| Language: | English |
| Published: |
New York [u.a.]
Wiley
2001
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| Edition: | 4. ed. |
| Subjects: | |
| Online Access: | Inhaltsverzeichnis Inhaltsverzeichnis |
| Physical Description: | XVIII, 875 S. graph. Darst. |
| ISBN: | 0471321680 |
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| 245 | 1 | 0 | |a Analysis and design of analog integrated circuits |c Paul R. Gray ... |
| 250 | |a 4. ed. | ||
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| 300 | |a XVIII, 875 S. |b graph. Darst. | ||
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| adam_text |
ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS FOURTH EDITION PAUL R.
GRAY UNIVERSITY OF CALIFORNIA, BERKELEY PAUL J. HURST UNIVERSITY OF
CALIFORNIA, DAVIS STEPHEN H. LEWIS UNIVERSITY OF CALIFORNIA, DAVIS
ROBERT G.MEYER UNIVERSITY OF CALIFORNIA, BERKELEY JOHN WILEY& SONS,
INC. NEW YORK / CHICHESTER / WEINHEIM / BRISBANE / SINGAPORE / TORONTO
CONTENTS CHAPTER 1 MODELS FOR INTEGRATED-CIRCUIT ACTIVE DEVICES L 1.1
INTRODUCTION 1 » 1.2 DEPLETION REGION OF A PN JUNCTION 1 1.2.1
DEPLETION-REGION CAPACITANCE 5 1.2.2 JUNCTION BREAKDOWN 6 1.3
LARGE-SIGNAL BEHAVIOR OF BIPOLAR TRANSISTORS 8 1.3.1 LARGE-SIGNAL MODELS
IN THE FORWARD-ACTIVE REGION 9 1.3.2 EFFECTS OF COLLECTOR VOLTAGE ON
LARGE-SIGNAL CHARACTERISTICS IN THE FORWARD-ACTIVE REGION 14 1.3.3
SATURATION AND INVERSE ACTIVE REGIONS 16 1.3.4 TRANSISTOR BREAKDOWN
VOLTAGES 20 1.3.5 DEPENDENCE OF TRANSISTOR CURRCNT GAIN SS F ON OPERATING
CONDITIONS 23 1.4 SMALL-SIGNAL MODELS OF BIPOLAR TRANSISTORS 26 1.4.1
TRANSCONDUCTANCE 27 1.4.2 BASE-CHARGING CAPACITANCE 28 1.4.3 INPUT
RESISTANCE 29 1.4.4 OUTPUT RESISTANCE 29 1.4.5 BASIC SMALL-SIGNAL MODEL
OF THE BIPOLAR TRANSISTOR 30 1.4.6 COLLECTOR-BASE RESISTANCE 30 1.4.7
PARASITIC ELEMENTS IN THE SMALL-SIGNAL MODEL 31 1.4.8 SPECIFICATION OF
TRANSISTOR FREQUENCY RESPONSE 34 1.5 LARGE SIGNAL BEHAVIOR OF
METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS 38 1.5.1 TRANSFER
CHARACTERISTICS OF MOS DEVICES 38 1.5.2 COMPARISON OF OPERATING REGIONS
OF BIPOLAR AND MOS TRANSISTORS 45 1.5.3 DECOMPOSITION OF GATE-SOURCE
VOLTAGE 47 1.5.4 THRESHOLD TEMPERATURE DEPENDENCE 47 1.5.5 MOS DEVICE
VOLTAGE LIMITATIONS 48 1.6 SMALL-SIGNAL MODELS OF THE MOS TRANSISTORS 49
1.6.1 TRANSCONDUCTANCE 50 1.6.2 INTRINSIC GATE-SOURCE AND GATE-DRAIN
CAPACITANCE 51 1.6.3 INPUT RESISTANCE 52 1.6.4 OUTPUT RESISTANCE 52
1.6.5 BASIC SMALL-SIGNAL MODEL OF THE MOS TRANSISTOR 52 1.6.6 BODY
TRANSCONDUCTANCE 53 1.6.7 PARASITIC ELEMENTS IN THE SMALL-SIGNAL MODEL
54 1.6.8 MOS TRANSISTOR FREQUENCY RESPONSE 55 1.7 SHORT-CHANNEL EFFECTS
IN MOS TRANSISTORS 58 1.7.1 VELOCITY SATURATION FROM THE HORIZONTAL
FIELD 59 1.7.2 TRANSCONDUCTANCE AND TRANSITION FREQUENCY 63 1.7.3
MOBILITY DEGRADATION FROM THE VERTICAL FIELD 65 1.8 WEAK INVERSION IN
MOS TRANSISTORS 65 1.8.1 DRAIN CURRENT IN WEAK INVERSION 66 1.8.2
TRANSCONDUCTANCE AND TRANSITION FREQUENCY IN WEAK INVERSION 68 1.9
SUBSTRATE CURRENT FLOW IN MOS TRANSISTORS 71 A.L.L SUMMARY OF
ACTIVE-DEVICE PARAMETERS 73 X CONTENTS XI CHAPTER 2 BIPOLAR, MOS, AND
BICMOS INTEGRATED-CIRCUIT TECHNOLOGY 78 2.1 INTRODUCTION 78 2.2 BASIC
PROCESSES IN INTEGRATED-CIRCUIT FABRICATION 79 2.2.1 ELECTRICAL
RESISTIVITY OF SILICON 79 2.2.2 SOLID-STATE DIFFUSION 80 2.2.3
ELECTRICAL PROPERTIES OF DIFFUSED LAYERS 82 2.2.4 PHOTOLITHOGRAPHY 84
2.2.5 EPITAXIAL GROWTH 85 2.2.6 ION IMPLANTATION 87 2.2.7 LOCAL
OXIDATION 87 2.2.8 POLYSILICON DEPOSITION 87 2.3 HIGH-VOLTAGE BIPOLAR
INTEGRATED-CIRCUIT FABRICATION 88 2.4 ADVANCED BIPOLAR
INTEGRATED-CIRCUIT FABRICATION 92 2.5 ACTIVE DEVICES IN BIPOLAR ANALOG
INTEGRATED CIRCUITS 95 2.5.1 INTEGRATED-CIRCUIT NPN TRANSISTOR 96 2.5.2
INTEGRATED-CIRCUIT PNP TRANSISTORS 107 2.6 PASSIVE COMPONENTS IN BIPOLAR
INTEGRATED CIRCUITS 115 2.6.1 DIFFUSED RESISTORS 115 2.6.2 EPITAXIAL AND
EPITAXIAL PINCH RESISTORS 119 2.6.3 INTEGRATED-CIRCUIT CAPACITORS 120
2.6.4 ZENER DIODES 121 2.6.5 JUNCTION DIODES 122 2.7 MODIFICATIONS TO
THE BASIC BIPOLAR PROCESS 123 2.7.1 DIELECTRIC ISOLATION 123 2.7.2
COMPATIBLE PROCESSING FOR HIGH-PERFORMANCE ACTIVE DEVICES 124 2.7.3
HIGH-PERFORMANCE PASSIVE COMPONENTS 127 2.8 MOS INTEGRATED-CIRCUIT
FABRICATION 127 2.9 ACTIVE DEVICES IN MOS INTEGRATED CIRCUITS 131 2.9.1
N-CHANNEL TRANSISTORS 131 2.9.2 P-CHANNCL TRANSISTORS 141 2.9.3
DEPLETION DEVICES 142 2.9.4 BIPOLAR TRANSISTORS 142 2.10 PASSIVE
COMPONENTS IN MOS TECHNOLOGY 144 2.10.1 RESISTORS 144 2.10.2 CAPACITORS
IN MOS TECHNOLOGY 145 2.10.3 LATCHUP IN CMOS TECHNOLOGY 148 2.11 BICMOS
TECHNOLOGY 150 2.12 HETEROJUNCTION BIPOLAR TRANSISTORS 152 2.13
INTERCONNECT DELAY 153 2.14 ECONOMICS OF INTEGRATED-CIRCUIT FABRICATION
154 2.14.1 YIELD CONSIDERATIONS IN INTEGRATED-CIRCUIT FABRICATION 154
2.14.2 COST CONSIDERATIONS IN INTEGRATED-CIRCUIT FABRICATION 157 2.15
PACKAGING CONSIDERATIONS FOR INTEGRATED CIRCUITS 159 2.15.1 MAXIMUM
POWER DISSIPATION 159 2.15.2 RELIABILITY CONSIDERATIONS IN
INTEGRATED-CIRCUIT PACKAGING 162 A.2.1 SPICE MODEL-PARAMETER FILES 163
CHAPTER 3 SINGLE-TRANSISTOR AND MULTIPLE-TRANSISTOR AMPLIFIERS 170 3.1
DEVICE MODEL SELECTION FOR APPROXIMATE ANALYSIS OF ANALOG CIRCUITS 171
3.2 TWO-PORT MODELING OF AMPLIFIERS 172 3.3 BASIC SINGLE-TRANSISTOR
AMPLIFIER STAGES 174 3.3.1 COMMON-EMITTER CONFIGURATION 175 3.3.2
COMMON-SOURCC CONFIGURATION 179 3.3.3 COMMON-BASE CONFIGURATION 183
3.3.4 COMMON-GATE CONFIGURATION 186 XII CONTENTS 3.3.5 COMMON-BASE AND
COMMON-GATE CONFIGURATIONS WITH FINITE R* 188 3.3.5.1 COMMON-B ASE AND
COMMON-GATE INPUT RESISTANCE 188 3.3.5.2 COMMON-BASE AND COMMON-GATE
OUTPUT RESISTANCE 190 3.3.6 COMMON-COLLECTOR CONFIGURATION (EMITTER
FOLIO WER) 191 3.3.7 COMMON-DRAIN CONFIGURATION (SOURCE FDLLOWER) 195
3.3.8 COMMON-ERRTITTER AMPLIFIER WITH EMITTER DEGENERATION 197 3.3.9
COMMON-SOURCE AMPLIFIER WITH SOURCE DEGENERATION 200 3.4
MULTIPLE-TRANSISTOR AMPLIFIER STAGES 202 3.4.1 THE CC-CE, CC-CC, AND
DARLINGTON CONFIGURATIONS 202 3.4.2 THE CASCODE CONFIGURATION 206
3.4.2.1 THE BIPOLAR CASCODE 206 3.4.2.2 THE MOS CASCODE 208 3.4.3 THE
ACTIVE CASCODE 211 3.4.4 THE SUPER SOURCE FOLLOWER 213 3.5 DIFFERENTIAL
PAIRS 215 3.5.1 THE DE TRANSFER CHARACTERISTIC OF AN EMITTER-COUPLED
PAIR 215 3.5.2 THE DE TRANSFER CHARACTERISTIC WITH EMITTER DEGENERATION
217 3.5.3 THE DE TRANSFER CHARACTERISTIC OF A SOURCE-COUPLED PAIR 218
3.5.4 INTRODUCTION TO THE SMALL-SIGNAL ANALYSIS OF DIFFERENTIAL
AMPLIFIERS 221 3.5.5 SMALL-SIGNAL CHARACTERISTICS OF BALANCCD
DIFFERENTIAL AMPLIFIERS 224 3.5.6 DEVICE MISMATCH EFFECTS IN
DIFFERENTIAL AMPLIFIERS 231 3.5.6.1 INPUT OFFSET VOLTAGE AND CURRENT 231
3.5.6.2 INPUT OFFSET VOLTAGE OF THE EMITTER-COUPLCD PAIR 232 3.5.6.3
OFFSET VOLTAGE OF THE EMITTER-COUPLED PAIR: APPROXIMATE ANALYSIS 232
3.5.6.4 OFFSET VOLTAGE DRIFT IN THE EMITTER-COUPLED PAIR 234 3.5.6.5
INPUT OFFSET CURRENT OF THE EMITTER-COUPLED PAIR 235 3.5.6.6 INPUT
OFFSET VOLTAGE OF THE SOURCE-COUPLED PAIR 236 3.5.6.7 OFFSET VOLTAGE OF
THE SOURCE-COUPLED PAIR: AP- PROXIMATE ANALYSIS 236 3.5.6.8 OFFSET
VOLTAGE DRIFT IN THE SOURCE-COUPLED PAIR 238 3.5.6.9 SMALL-SIGNAL
CHARACTERISTICS OF UNBALANCED DIFFERENTIAL AMPLIFIERS 238 A.3.1
ELEMENTARY STATISTICS AND THE GAUSSIAN DISTRIBUTION 246 CHAPTER 4
CURRENT MIRRORS, ACTIVE LOADS, AND REFERENCES 253 4.1 INTRODUCTION 253
4.2 CURRENT MIRRORS 253 4.2.1 GENERAL PROPERTIES 253 4.2.2 SIMPLE
CURRENT MIRROR 255 4.2.2.1 BIPOLAR 255 4.2.2.2 MOS 257 4.2.3 SIMPLE
CURRENT MIRROR WITH BETA HELPER 260 4.2.3.1 BIPOLAR 260 4.2.3.2 MOS 262
4.2.4 SIMPLE CURRENT MIRROR WITH DEGENERATION 262 4.2.4.1 BIPOLAR 262
4.2.4.2 MOS 263 4.2.5 CASCODE CURRENT MIRROR 263 4.2.5.1 BIPOLAR 263
4.2.5.2 MOS 266 4.2.6 WILSON CURRENT MIRROR 274 4.2.6.1 BIPOLAR 274
4.2.6.2 MOS 277 4.3 ACTIVE LOADS 278 4.3.1 MOTIVATION 278 4.3.2
COMMON-EMITTER/COMRNON-SOURCE AMPLIFIER WITH COMPLEMENTARY LOAD 279
4.3.3 COMMON-EMITTER/COMMON-SOURCE AMPLIFIER WITH DEPLETION LOAD 282
CONTENTS XIII 4.3.4 COMMON-EMITTER/COMMON-SOURCE AMPLIFIER WITH
DIODE-CONNECTED LOAD 284 4.3.5 DIFFERENTIAL PAIR WITH CURRENT-MIRROR
LOAD 287 4.3.5.1 LARGE-SIGNAL ANALYSIS 287 4.3.5.2 SMALL-SIGNAL ANALYSIS
288 4.3.5.3 COMMON-MODE REJECTION RATIO 293 , 4.4 VOLTAGE AND CURRENT
REFERENCES 299 4.4.1 LOW-CURRENT BIASING 299 4.4.1.1 BIPOLAR WIDLAR
CURRENT SOURCE 299 4.4.1.2 MOS WIDLAR CURRENT SOURCE 302 4.4.1.3 BIPOLAR
PEAKING CURRENT SOURCE 303 4.4.1.4 MOS PEAKING CURRENT SOURCE 304 4.4.2
SUPPLY-INSENSITIVE BIASING 306 4.4.2.1 WIDLAR CURRENT SOURCES 306
4.4.2.2 CURRENT SOURCES USING OTHER VOLTAGE STANDARDS 307 4.4.2.3 SEIF
BIASING 309 4.4.3 TEMPERATURE-INSENSITIVE BIASING 317 4.4.3.1
BAND-GAP-REFERENCED BIAS CIRCUITS IN BIPOLAR TECHNOLOGY 317 4.4.3.2
BAND-GAP-REFERENCED BIAS CIRCUITS IN CMOS TECHNOLOGY 323 A.4.1 MATCHING
CONSIDERATIONS IN CURRENT MIRRORS 327 A.4.1.1 BIPOLAR 327 A.4.1.2MOS 329
A.4.2 INPUT OFFSET VOLTAGE OF DIFFERENTIAL PAIR WITH ACTIVE LOAD 332
A.4.2.1 BIPOLAR 332 A.4.2.2 MOS 334 CHAPTER 5 OUTPUT STAGES 344 5.1
INTRODUCTION 344 5.2 THE EMITTER FOLIO WER AS AN OUTPUT STAGE 344 5.2.1
TRANSFER CHARACTERISTICS OF THE EMITTER-FOLLOWER 344 5.2.2 POWER OUTPUT
AND EFFICIENCY 347 5.2.3 EMITTER-FOLLOWER DRIVE REQUIREMENTS 354 5.2.4
SMALL-SIGNAL PROPERTIES OF THE EMITTER FOLLOWER 355 5.3 THE SOURCE
FOLLOWER AS AN OUTPUT STAGE 356 5.3.1 TRANSFER CHARACTERISTICS OF THE
SOURCE FOLLOWER 356 5.3.2 DISTORTION IN THE SOURCE FOLLOWER 358 5.4
CLASS B PUSH-PULL OUTPUT STAGE 362 5.4.1 TRANSFER CHARACTERISTIC OF THE
CLASS B STAGE 363 5.4.2 POWER OUTPUT AND EFFICIENCY OF THE CLASS B STAGE
365 5.4.3 PRACTICAL REALIZATIONS OF CLASS B COMPLEMENTARY OUTPUT STAGES
369 5.4.4 ALL-/? CLASS B OUTPUT STAGE 376 5.4.5 QUASI-COMPLEMENTARY
OUTPUT STAGES 379 5.4.6 OVERLOAD PROTECTION 380 5.5 CMOS CLASS AB OUTPUT
STAGES 382 5.5.1 COMMON-DRAIN CONFIGURATION 383 5.5.2 COMMON-SOURCE
CONFIGURATION WITH ERROR AMPLIFIERS 384 5.5.3 ALTERNATIVE CONFIGURATIONS
391 5.5.3.1 COMBINED COMMON-DRAIN COMMON-SOURCE CONFIGURATION 391
5.5.3.2 COMBINED COMMON-DRAIN COMMON-SOURCE CONFIGURATION WITH HIGH
SWING 393 5.5.3.3 PARALLEL COMMON-SOURCE CONFIGURATION 394 CHAPTER 6
OPERATIONAL AMPLIFIERS WITH SINGLE-ENDED OUTPUTS 404 6.1 APPLICATIONS OF
OPERATIONAL AMPLIFIERS 405 XIV CONTENTS 6.1.1 BASIC FEEDBACK CONCEPTS
405 6.1.2 INVERTING AMPLIFIER 406 6.1.3 NONINVERTING AMPLIFIER 408 6.1.4
DIFFERENTIAL AMPLIFIER 408 6.1.5 NONLINEAR ANALOG OPERATIONS 409 6.1.6
INTEGRATOR, DIFFERENTIATOR 410 6.1.7 INTERNAL AMPLIFIERS 411 6.1.7.1
SWITCHED-CAPACITOR AMPLIFIER 411 6.1.7.2 SWITCHED-CAPACITOR INTEGRATOR
416 6.2 DEVIATIONS FROM IDEALITY IN REAL OPER- ATIONAL AMPLIFIERS 419
6.2.1 INPUT BIAS CURRENT 419 6.2.2 INPUT OFFSET CURRENT 420 6.2.3 INPUT
OFFSET VOLTAGE 421 6.2.4 COMMON-MODE INPUT RANGE 421 6.2.5 COMMON-MODE
REJECTION RATIO (CMRR) 421 6.2.6 POWER-SUPPLY REJECTION RATIO (PSRR) 422
6.2.7 INPUT RESISTANCE 424 6.2.8 OUTPUT RESISTANCE 424 6.2.9 FREQUENCY
RESPONSE 424 6.2.10 OPERATIONAL-AMPLIFIER EQUIVALENT CIRCUIT 424 6.3
BASIC TWO-STAGE MOS OPERATIONAL AMPLIFIERS 425 6.3.1 INPUT RESISTANCE,
OUTPUT RESISTANCE, AND OPEN-CIRCUIT VOLTAGE GAIN 426 6.3.2 OUTPUT SWING
428 6.3.3 INPUT OFFSET VOLTAGE 428 6.3.4 COMMON-MODE REJECTION RATIO 431
6.3.5 COMMON-MODE INPUT RANGE 432 6.3.6 POWER-SUPPLY REJECTION RATIO
(PSRR) 434 6.3.7 EFFECT OF OVERDRIVE VOLTAGES 439 6.3.8 LAYOUT
CONSIDERATIONS 439 6.4 TWO-STAGE MOS OPERATIONAL AMPLIFIERS WITH
CASCODES 442 6.5 MOS TELESCOPIC-CASCODE OPERATIONAL AMPLIFIERS 444 6.6
MOS FOLDED-CASCODE OPERATIONAL AMPLIFIERS 446 6.7 MOS ACTIVE-CASCODE
OPERATIONAL AMPLIFIERS 450 6.8 BIPOLAR OPERATIONAL AMPLIFIERS 453 6.8.1
THE DE ANALYSIS OF THE 741 OPERATIONAL AMPLIFIER 456 6.8.2 SMALL-SIGNAL
ANALYSIS OF THE 741 OPERATIONAL AMPLIFIER 461 6.8.3 INPUT OFFSET
VOLTAGE, INPUT OFFSET CURRENT, AND COMMON-MODE REJECTION RATIO OF THE
741 470 6.9 DESIGN CONSIDERATIONS FOR BIPOLAR MONOLITHIC OPERATIONAL
AMPLIFIERS 472 6.9.1 DESIGN OF LOW-DRIFT OPERATIONAL AMPLIFIERS 474
6.9.2 DESIGN OF LOW-INPUT-CURRENT OPERATIONAL AMPLIFIERS 476 CHAPTER 7
FREQUENCY RESPONSE OF INTEGRATED CIRCUITS 488 7.1 INTRODUCTION 488 7.2
SINGLE-STAGE AMPLIFIERS 488 7.2.1 SINGLE-STAGE VOLTAGE AMPLIFIERS AND
THE MILLER EFFECT 488 7.2.1.1 THE BIPOLAR DIFFERENTIAL AMPLIFIER:
DIFFERENTIAL- MODE GAIN 493 7.2.1.2 THE MOS DIFFERENTIAL AMPLIFIER:
DIFFERENTIAL- MODE GAIN 496 7.2.2 FREQUENCY RESPONSE OF THE COMMON-MODE
GAIN FOR A DIFFERENTIAL AMPLIFIER 499 7.2.3 FREQUENCY RESPONSE OF
VOLTAGE BUFFERS 502 7.2.3.1 FREQUENCY RESPONSE OF THE EMITTER FOLLOWER
503 7.2.3.2 FREQUENCY RESPONSE OF THE SOURCE FOLLOWER 509 7.2.4
FREQUENCY RESPONSE OF CURRENT BUFFERS 511 7.2.4.1 COMMON-BASE-AMPLIFIER
FREQUENCY RESPONSE 514 7.2.4.2 COMMON-GATE-AMPLIFIER FREQUENCY RESPONSE
515 CONTENTS XV 7.3 MULTISTAGE AMPLIFIER FREQUENCY RESPONSE 516 7.3.1
DOMINANT-POLC APPROXIMATION 516 7.3.2 ZERO-VALUE TIME CONSTANT ANALYSIS
517 7.3.3 CASCODE VOLTAGE-AMPLIFIER FREQUENCY RESPONSE 522 7.3.4 CASCODE
FREQUENCY RESPONSE 525 » 7.3.5 FREQUENCY RESPONSE OF A CURRENT MIRROR
LOADING A DIFFERENTIAL PAIR 532 7.3.6 SHORT-CIRCUIT TIME CONSTANTS 533
7.4 ANALYSIS OF THE FREQUENCY RESPONSE OF THE 741 OP AMP 537 7.4.1
HIGH-FREQUENCY EQUIVAIENT CIRCUIT OF THE 741 537 7.4.2 CALCULATION OF
THE -3-DB FREQUENCY OF THE 741 538 7.4.3 NONDOMINANT POLES OF THE 741
540 7.5 RELATION BETWEEN FREQUENCY RESPONSE AND TIME RESPONSE 542
CHAPTER 8 FEEDBACK 553 8.1 IDEAL FEEDBACK EQUATION 553 8.2 GAIN
SENSITIVITY 555 8.3 EFFECT OF NEGATIVE FEEDBACK ON DISTORTION 555 8.4
FEEDBACK CONFIGURATIONS 557 8.4.1 SERIES-SHUNT FEEDBACK 557 8.4.2
SHUNT-SHUNT FEEDBACK 560 8.4.3 SHUNT-SERIES FEEDBACK 561 8.4.4
SERIES-SERIES FEEDBACK 562 8.5 PRACTICAL CONFIGURATIONS AND THE EFFECT
OF LOADING 563 8.5.1 SHUNT-SHUNT FEEDBACK 563 8.5.2 SERIES-SERIES
FEEDBACK 569 8.5.3 SERIES-SHUNT FEEDBACK 579 8.5.4 SHUNT-SERIES FEEDBACK
583 8.5.5 SUMMARY 587 8.6 SINGLE-STAGE FEEDBACK 587 8.6.1 LOCAL SERIES
FEEDBACK 587 8.6.2 LOCAL SHUNT FEEDBACK 591 8.7 THE VOLTAGE REGULATOR AS
A FEEDBACK CIRCUIT 593 8.8 FEEDBACK CIRCUIT ANALYSIS USING RETURN RATIO
599 8.8.1 CLOSED-LOOP GAIN USING RETURN RATIO 601 8.8.2 CLOSED-LOOP
IMPEDANCE FORMULA USING RETURN RATIO 607 8.8.3 SUMMARY*RETURN-RATIO
ANALYSIS 612 8.9 MODELING INPUT AND OUTPUT PORTS IN FEEDBACK CIRCUITS
613 CHAPTER 9 FREQUENCY RESPONSE AND STABILITY OF FEEDBACK AMPLIFIERS
624 9.1 INTRODUCTION 624 9.2 RELATION BETWEEN GAIN AND BANDWIDTH IN
FEEDBACK AMPLIFIERS 624 9.3 INSTABILITY AND THE NYQUIST CRITERION 626
9.4 COMPENSATION 633 9.4.1 THEORY OF COMPENSATION 633 9.4.2 METHODS OF
COMPENSATION 637 9.4.3 TWO-STAGE MOS AMPLIFIER COMPENSATION 644 9.4.4
COMPENSATION OF SINGLE-STAGE CMOS OP AMPS 652 9.4.5 NESTED MILLER
COMPENSATION 656 9.5 ROOT-LOCUS TECHNIQUES 664 9.5.1 ROOT LOCUS FOR A
THREE-POLE TRANSFER FUNCTION 664 9.5.2 RULES FOR ROOT-LOCUS CONSTRUCTION
667 9.5.3 ROOT LOCUS FOR DOMINANT-POLC COMPENSATION 675 9.5.4 ROOT LOCUS
FOR FECDBACK-ZERO COMPENSATION 676 9.6 SLEW RATE 680 9.6.1 ORIGIN OF
SLEW-RATE LIMITATIONS 680 9.6.2 METHODS OF IMPROVING SLEW-RATE 684 XVI
CONTENTS 9.6.3 IMPROVING SLEW-RATE IN BIPOLAR OP AMPS 685 9.6.4
IMPROVING SLEW-RATE IN MOS OP AMPS 686 9.6.5 EFFECT OF SLEW-RATE
LIMITATIONS ON LARGE-SIGNAL SINUSOIDAL PERFORMANCE 690 A.9.1 ANALYSIS IN
TERMS OF RETURN-RATIO PARAMETERS 691 A.9.2 ROOTS OF A QUADRATIC EQUATION
692 CHAPTER 10 NONLINEAR ANALOG CIRCUITS 702 10.1 INTRODUCTION 702 10.2
PRECISION RECTIFICATION 702 10.3 ANALOG MULTIPLIERS EMPLOYING THE
BIPOLAR TRANSISTOR 708 10.3.1 THE EMITTER-COUPLED PAIR AS A SIMPLE
MULTIPLIER 708 10.3.2 THE DE ANALYSIS OF THE GILBERT MULTIPLIER CELL 710
10.3.3 THE GILBERT CELL AS AN ANALOG MULTIPLIER 712 10.3.4 A COMPLETE
ANALOG MULTIPLIER 715 10.3.5 THE GILBERT MULTIPLIER CELL AS A BALANCED
MODULATOR AND PHASE DECTECTOR 716 10.4 PHASE-LOCKED LOOPS (PLL) 720
10.4.1 PHASE-LOCKED LOOP CONCEPTS 720 10.4.2 THE PHASE-LOCKED LOOP IN
THE LOCKED CONDITION 722 10.4.3 INTEGRATED-CIRCUIT PHASE-LOCKED LOOPS
731 10.4.4 ANALYSIS OF THE 560B MONOLITHIC PHASE-LOCKED LOOP 735 10.5
NONLINEAR FUNCTION SYMBOLS 743 CHAPTER 11 NOISE IN INTEGRATED CIRCUITS
748 11.1 INTRODUCTION 748 11.2 SOURCES OF NOISE 748 11.2.1 SHOT NOISE
748 11.2.2 THERMAL NOISE 752 11.2.3 FLICKER NOISE (L/F NOISE) 753 11.2.4
BURST NOISE (POPCORN NOISE) 754 11.2.5 AVALANCHE NOISE 755 11.3 NOISE
MODELS OF INTEGRATED-CIRCUIT COMPONENTS 756 11.3.1 JUNCTION DIODE 756
11.3.2 BIPOLAR TRANSISTOR 757 11.3.3 MOS TRANSISTOR 758 11.3.4 RESISTORS
759 11.3.5 CAPACITORS AND INDUCTORS 759 11.4 CIRCUIT NOISE CALCULATIONS
760 11.4.1 BIPOLAR TRANSISTOR NOISE PERFORMANCE 762 11.4.2 EQUIVALENT
INPUT NOISE AND THE MINIMUM DETECTABLE SIGNAL 766 11.5 EQUIVALENT INPUT
NOISE GENERATORS 768 11.5.1 BIPOLAR TRANSISTOR NOISE GENERATORS 768
11.5.2 MOS TRANSISTOR NOISE GENERATORS 773 11.6 EFFECT OF FEEDBACK ON
NOISE PERFORMANCE 776 11.6.1 EFFECT OF IDEAL FEEDBACK ON NOISE
PERFORMANCE 776 11.6.2 EFFECT OF PRACTICAL FEEDBACK ON NOISE PERFORMANCE
776 11.7 NOISE PERFORMANCE OF OTHER TRANSISTOR CONFIGURATIONS 783 11.7.1
COMMON-BASE STAGE NOISE PERFORMANCE 783 11.7.2 EMITTER-FOLLOWER NOISE
PERFORMANCE 784 11.7.3 DIFFERENTIAL-PAIR NOISE PERFORMANCE 785 11.8
NOISE IN OPERATIONAL AMPLINERS 788 11.9 NOISE BANDWIDTH 794 11.10 NOISE
FIGURE AND NOISE TEMPERATURE 799 11.10.1 NOISE FIGURE 799 11.10.2 NOISE
TEMPERATURE 802 CONTENTS XVII CHAPTER 12 FULLY DIFFERENTIAL OPERATIONAL
AMPLIFIERS 808 12.1 INTRODUCTION 808 12.2 PROPERTIES OF FULLY
DIFFERENTIAL AMPLIFIERS 808 12.3 SMALL-SIGNAL MODELS FOR BALANCED
DIFFERENTIAL AMPLIFIERS 811 12.4 COMMON-MODE FEEDBACK 816 12.4.1
COMMON-MODE FEEDBACK AT LOW FREQUENCIES 817 12.4.2 STABILITY AND
COMPENSATION CONSIDERATIONS IN A CMFB LOOP 822 12.5 CMFB CIRCUITS 823
12.5.1 CMFB USING RESISTIVE DIVIDER AND AMPLIFIER 824 12.5.2 CMFB USING
TWO DIFFERENTIAL PAIRS 828 12.5.3 CMFB USING TRANSISTORS IN THE TRIODE
REGION 830 12.5.4 SWITCHED-CAPACITOR CMFB 832 12.6 FULLY DIFFERENTIAL OP
AMPS 835 12.6.1 A FULLY DIFFERENTIAL TWO-STAGE OP AMP 835 12.6.2 FULLY
DIFFERENTIAL TELESCOPIC CASCODE OP AMP 845 12.6.3 FULLY DIFFERENTIAL
FOLDED-CASCODE OP AMP 846 12.6.4 A DIFFERENTIAL OP AMP WITH TWO
DIFFERENTIAL INPUT STAGES 847 12.6.5 NEUTRALIZATION 849 12.7 UNBALANCED
FULLY DIFFERENTIAL CIRCUITS 850 12.8 BANDWIDTH OF THE CMFB LOOP 856
INDEX 865 |
| any_adam_object | 1 |
| building | Verbundindex |
| bvnumber | BV013895218 |
| callnumber-first | T - Technology |
| callnumber-label | TK7874 |
| callnumber-raw | TK7874 |
| callnumber-search | TK7874 |
| callnumber-sort | TK 47874 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ZN 4920 |
| classification_tum | ELT 346f |
| ctrlnum | (OCoLC)247725293 (DE-599)BVBBV013895218 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | 4. ed. |
| format | Book |
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| id | DE-604.BV013895218 |
| illustrated | Illustrated |
| indexdate | 2024-10-17T14:01:39Z |
| institution | BVB |
| isbn | 0471321680 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-009508085 |
| oclc_num | 247725293 |
| open_access_boolean | |
| owner | DE-703 DE-92 DE-91 DE-BY-TUM DE-706 DE-29T DE-861 DE-898 DE-BY-UBR DE-634 DE-83 |
| owner_facet | DE-703 DE-92 DE-91 DE-BY-TUM DE-706 DE-29T DE-861 DE-898 DE-BY-UBR DE-634 DE-83 |
| physical | XVIII, 875 S. graph. Darst. |
| publishDate | 2001 |
| publishDateSearch | 2001 |
| publishDateSort | 2001 |
| publisher | Wiley |
| record_format | marc |
| spelling | Analysis and design of analog integrated circuits Paul R. Gray ... 4. ed. New York [u.a.] Wiley 2001 XVIII, 875 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf MOS-Schaltung (DE-588)4135571-4 gnd rswk-swf Analoge integrierte Schaltung (DE-588)4112519-8 gnd rswk-swf Analoge integrierte Schaltung (DE-588)4112519-8 s DE-604 MOS-Schaltung (DE-588)4135571-4 s Integrierte Schaltung (DE-588)4027242-4 s 1\p DE-604 Gray, Paul R. Sonstige oth http://www3.ub.tu-berlin.de/ihv/000782299.pdf Inhaltsverzeichnis GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009508085&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Analysis and design of analog integrated circuits Integrierte Schaltung (DE-588)4027242-4 gnd MOS-Schaltung (DE-588)4135571-4 gnd Analoge integrierte Schaltung (DE-588)4112519-8 gnd |
| subject_GND | (DE-588)4027242-4 (DE-588)4135571-4 (DE-588)4112519-8 |
| title | Analysis and design of analog integrated circuits |
| title_auth | Analysis and design of analog integrated circuits |
| title_exact_search | Analysis and design of analog integrated circuits |
| title_full | Analysis and design of analog integrated circuits Paul R. Gray ... |
| title_fullStr | Analysis and design of analog integrated circuits Paul R. Gray ... |
| title_full_unstemmed | Analysis and design of analog integrated circuits Paul R. Gray ... |
| title_short | Analysis and design of analog integrated circuits |
| title_sort | analysis and design of analog integrated circuits |
| topic | Integrierte Schaltung (DE-588)4027242-4 gnd MOS-Schaltung (DE-588)4135571-4 gnd Analoge integrierte Schaltung (DE-588)4112519-8 gnd |
| topic_facet | Integrierte Schaltung MOS-Schaltung Analoge integrierte Schaltung |
| url | http://www3.ub.tu-berlin.de/ihv/000782299.pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009508085&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT graypaulr analysisanddesignofanalogintegratedcircuits |
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