Proceedings 2001: Las Vegas Convention Center, Las Vegas, NV, June 18 - 22, 2001
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| Corporate Author: | |
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| Format: | Conference Proceeding Book |
| Language: | English |
| Published: |
New York, NY
ACM Press
2001
|
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Physical Description: | XXXIII, 868 S. Ill., graph. Darst. |
| ISBN: | 1581132972 |
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| 111 | 2 | |a Design Automation Conference (Association for Computing Machinery) |n 38 |d 2001 |c Las Vegas, Nev. |j Verfasser |0 (DE-588)6033467-8 |4 aut | |
| 245 | 1 | 0 | |a Proceedings 2001 |b Las Vegas Convention Center, Las Vegas, NV, June 18 - 22, 2001 |c 38th Design Autmation Conference, DAC |
| 246 | 1 | 3 | |a DAC 2001 |
| 246 | 1 | 3 | |a Proceedings of the 38th Design Automation Conference |
| 264 | 1 | |a New York, NY |b ACM Press |c 2001 | |
| 300 | |a XXXIII, 868 S. |b Ill., graph. Darst. | ||
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Table
of Contents
General Chair's Welcome
.
¡
Executive Committee
.
¡Ü
Technical Program Committee
.
v
Panel Sub-Committee
.
vii
Student Design Contest Judges
.viii
Opening Keynote Address
-
Henry
Samueli
.ix
Thursday Keynote Address
-
Willem
P. Roelandts
.
x
2001
Best Paper Award
.xi
2001
IEEE Fellows
.xii
CAD Transactions Best Paper Award
.xii
VLSI Transactions Best Paper Award
.xii
Outstanding Young Author Award
.xii
CAS Industrial Pioneer Award
.xii
Marie R.
Pistilli
Women in EDA Achievement Award
.xii
The P.O.
Pistilli
Scholarship for Advancement in Computer Science
.xiii
2000
DAC
P.O.
Pistilli
Undergraduate Scholarships
.xiii
Design Automationn Conference Graduate Scholarships
.xiii
ACM/SIGDA Distinguished Service Award
.xiii
DAC
2001
Student Design Content Winners
.xiv
Reviewers
.xv
Call for Papers
.xix
Session
1
Panel: The Electronics Industry Supply Chain: Who Will Do What?
Chair and Organizer: Rita Glover
Panel Members: Marc Halpern, Rich Becks, Richard Kubin, Henry
Jürgens,
Rick Cassidy,
Ted Vucurevich
.1
Session
2
Nanometer Futures
Chair: Andrew B. Kahng
Organizers: Andrew B. Kahng, Kurt Keutzer
2.1
Future Performance Challenges in Nanometer Design
Dennis Sylvester, Himcmshu Kaul.
.3
2.2 1С
Design in High-Cost Nanometer-Technologies Era
Wojciech
Maly
.
Session
3
System-Level Configurability: Bus, Interface, and Processor Design
Chair:
Pieter
van
der Wolf
Organizers:
Kees Vissers,
Kurt Keutzer
3.1
LOTTERYBUS: A New High-Performaiice Communication Architecture for System-on-Chip Designs
Kanbhka Lahiri,
Ananá
Raghunathm, Ganesh Lakshminarayana
.15
XXI
3.2 Robust Interfaces
for Mixed-Timing
Systems
with
Application
to Latency-Insensitive Protocols
Tiberiu Chelcea, Steven M. Nowick
.21
3.3
Latency-Driven Design of Multi-Purpose Systems-On-Chip
Seapahn Meguerdichian,
Milenko
Drinic, Darko Kirovski
.27
3.4
Estimation of Speed, Area, and Power of Parameterizable, Soft IP
Jagesh Sanghavi, Albert Wang
.31
Session
4
Making Verification More Efficient
Chair: Masahiro Fujita
Organizers: Limor Fix, Timothy
Kam
4.1
Formal Property Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines
Dong Wang, Pei-Hsin Ho, Jiang Long, James Kukula, Yunshan Zhu, Tony Ma, Robert
Damiano.35
4.2
Scalable Hybrid Verification of Complex Microprocessors
Maher Mneimneh, FadiAloul, Chris Weaver, Saugata Chatterjee,
Karem
Sakallah, Todd
Austin
.41
43
Symbolic
RTL
Simulation
Alfred
Kölbl,
James Kukula, Robert
Damiano.47
Session
5
SoC and High-Level DFT
Chair: Yervant Zorian
Organizers: Anand Raghunathan, Irith Pomeranz
5.1
A Unified DFT Architecture for Use with IEEE
1149.1
and VSIA/IEEE P1500 Compliant Test Access
Controllers
Bulent I. Dervisoglu
.53
5.2
Instruction-Level DFT for Testing Processor and IP Cores in System-on-a-Chip
Wei-Cheng Lai, Kwang-Ting (Tim) Cheng.
.59
53
Test Strategies for BIST at the Algorithmic and Register-Transfer Levels
Kelly A. Ockunzzi, Chris Papachristou
.65
Session
6
Panel: The Next HDL: If
C
-н-
is the Answer, What was the Question?
Chair: Rajesh K. Gupta
Organizers: Shishpal Rawat,
Ingrid
Verbauwhede
Panel Members: Gerard Berry, Ramesh Chandra, Daniel Gajski, Kris Konigsfeld,
Portiek Schaumont,
Ingrid
Verbauwhede
.71
Session
7
Design for Subwavelength Manufacturability: Impact on EDA
Chair: Robert
С
Pack
Organizers: Andrew B. Kahng,
Lars Liebmann
7.1
Reticle Enhancement Technology: Implications and Challenges for Physical Design
W. Grobman, M. Thompson, R. Wang, C. Yuan, R.
Tian,
E. Demircan
.73
7.2
Enabling Alternating Phase Shifted Mask Designs for a Full Logic Gate Level: Design Rules
and Design Rule Checking
Lars Liebmann,
Jennifer Lund, Fook-Luen
Heng,
Ioana Graur
.79
73
Layout Design Methodologies for Sub-Wavelength Manufacturing
Michael L. Rieger, Jeffrey P. Mayhew, Sridhar Panchapakesan
.85
xxu
7.4 Adoption
of OPC and the Impact on Design and Layout
F. M.
Schellenberg,
Olivier Toublan,
Luigi
Capodieci, Bob
Socha
.89
7.5
Practical Application of Full-Feature Alternating Phase-Shifting Technology for a Phase-Aware Standard-
Cell Design Flow
Michael
Sanie,
Michel
Côté,
Philippe Hurat, Vinod Malhotra
.93
Session
8
New Ideas in Logic Synthesis
Chair: Yusuke Matsunaga
Organizers: Timothy
Kam, Masahiro
Fujita
8.1
Layout-Driven Hot-Carrier Degradation Minimization Using Logic Restructuring Techniques
Chih-Wei (Jim) Chang,
Kai
Wang,
Małgorzata Marek-Sadowska
.97
8.2
An Algorithm for Bi-Decomposition of Logic Functions
Alan Mishchenko, Bernd Steinbach,
Marek Perkowski
.103
8.3
Factoring and Recognition of Read-Once Functions using Cographs and Normality
Martin C. Golumbic,
Aviad
Mintz, UdiRotics
.109
8.4
Logic Minimization using Exclusive OR Gates
Valentina
Ciriani
.115
Session
9
Analog Design and Modeling
Chair:
Alper Demir
Organizers: Joel Phillips, Noel
Menezes
9.1
Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems
JafarSavoj, BehzadRazavi
.121
9.2
A Novel Method for Stochastic Nonlinearity Analysis of a CMOS Pipeline ADC
David
Goren, Eliyahu
Shamsaev, Israel A. Wagner
.127
93
Behavioral Partitioning in the Synthesis of Mixed Analog-Digital Systems
Sree Ganesan,
Ranga
Venturi.
133
9.4
Efficient DDD-based Symbolic Analysis of Large Linear Analog Circuits
Wim Verhaegen,
Georges Gielen
.139
Session
10
Scan-Based Testing
Chair: T. M.
Mak
Organizers: Anand Raghunathan, Tim Cheng
ЮЛ
Random Limited-Scan to Improve Random Pattern Testing of Scan Circuits
Irith Pomeranz.
.
10.2
Test Volume and Application Time Reduction Through Scan Chain Concealment
Ismet Bayraktaroglu, Alex Orailoglu
.151
103
An Approach to Test Compaction for Scan Circuits that Enhances At-Speed Testing
Irith Pomeranz, Sudhakar M. Ready
.156
10.4
Generating Efficient Tests for Continuous Scan
Sying-Jyan Wang, Sheng-Nan
Chiou
.162
10.5
Combining Low-Power Scan Testing and Test Data Compression for System-on-a-Chip
Anshuman Chandra, Krishnendu Chakrabarty
.166
xxiii
Session 11
Panel:
Your Core
-
My Problem? Integration and Verification of IP
Chair:
Gabe
Moretti
Organizers: Nanette Collins,
Dave Keif, Gabe
Moretti
Panel Members: Tom Anderson, Janick Bergeron, Ashish Dixit, Peter Flake, Tim Hopes, Ramesh
Narayanaswamy
.
Session
12
Configurable Computing: Reconfiguring the Industry
Chair:
Diederik Verkest
Organizers:
Diederik Verkest,
Kurt Keutzer
12.1
A
Quick Safari
through the Reconfiguration Jungle
Patrick Schaumont,
Ingrid
Verbauwhede, Kurt Keutzer, Majid Sarrajzadeh
.172
12.2
Re-Configurable Computing in Wireless
Bill Salefski,
Levent
Caglar
.178
123
Hardware/Software Instruction Set Configurability for System-on-Chip Processors
Albert Wang,
Earl Killian,
Dror Maydan, Chris Rowen
.184
Session
13
Interconnect Design Optimization
Chair: Martin D. F. Wong
Organizers: Jason Cong, Louis Scheffer, Patrick Groeneveld
13.1
A Practical Methodology for Early Buffer and Wire Resource Allocation
Charles J. Alpert, Jiang
Hu, Sachin
S.
Sapatnekar, Paul
G. Villarrubia
.189
13.2
Creating and Exploiting Flexibility in
Steiner
Trees
Elaheh Bozorgzadeh,
Ryan Kastner,
Majid Sarrajzadeh
.795
133
Simultaneous Shield Insertion and Net Ordering under Explicit RLC Noise Constraint
Kevin
M Lepak,
Invan Luwandi,
Lei He
.199
13.4
On Optimum Switch Box Designs for 2-D FPGAs
HongbingFan, JipingLiu, Yu-Liang Wu, Chak-Chung Cheung.
.203
Session
14
Power Estimation Techniques
Chair: Massoud Pedram
Organizers: Donatella Sciuto, Kazutoshi Wakabayashi
14.1
Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks
Sanjukta Bhanja,
N.
Ranganathan
.209
14.2
A Static
Estimatton
Technique of Power Sensitivity in Logic Circuits
Taewhan Kim, Ki-Seok Chung,
C. L.
Liu
.215
143
JouIeTrack
-
A Web Based Tool for Software Energy Profiling
AmitSinha, AnanthaP.
Chandrakasan.220
Session
15
Functional Validation Based on Boolean Reasoning (BDD, SAT)
Chair. Limor Fix
Organizers: Masahiro Fujita, Timothy
Kam
15.1
Effective Use of Boolean Satisfiability Procedures in the Formal Verification of Superscalar and VLIW
Microprocessors
Miroslav N.
Velev, Randal
E.
Bryant
.226
xxiv
15.2
Circuit-based Boolean
Reasoning
Andreas Kuehlmann, Malay
К.
Ganai, Viresh Paruthi
.232
15.3
Checking Equivalence for Partial Implementations
Christoph Scholl, Bernd
Becker
. 238
Session
16
Verification: Life Beyond Algorithms
Chair and Organizer: Carl Pixley
16.1
Validating the Intel® Pentium®
4
Microprocessor
Bob
Bentley
.244
16.2
Nuts and Bolts of Core and SoC Verification
Ken
Albin
.249
16.3
Teaching Future Verification Engineers: The Forgotten Side of Logic Design
Fusun Ozguner, Duane Marhefka, Joanne DeGroat, Bruce Wile, Jennifer Stofer, LyleHanrahan
.253
Session
17
Dissecting an Embedded System: Lessons from Bluetooth
Chair: Jan Rabaey
Organizers: Jan Rabaey, Anantha
Chandrakasan
17.1
SoC Integration of Reusable Baseband Bluetooth IP
Barry Clark,
Torbjörn Grahm
.256
17.2
One-chip Bluetooth ASIC Challenges
PaulT.M. vanZeijl
.262
Session
18
Algorithmic and Compiler Transformations for High-Level Synthesis
Chair: Hiroto Yasuura
Organizers: Kazutoshi Wakabayashi, Rajesh K. Gupta
18.1
Transformations for the Synthesis and Optimization of Asynchronous Distributed Control
Michael Theobald, Steven M. Nowick
.263
18.2
Speculation Techniques for High Level Synthesis of Control Intensive Designs
Sumit Gupta, Nick Savoiu, Sunwoo Kim, NikilDutt, Rajesh K. Gupta,
Alex Nicolau.269
18.3
Parallelizing DSP Nested Loops on
Reconfigurable
Architectures using Data Context Switching
Kiran Bondalapati
."5
18.4
Using Symbolic Algebra in Algorithmic Level DSP Synthesis
Armita Peymandoust, Giovanni
De Micheli.
277
Session
19
Gate Delay Calculation
Chair: Satya Pullela
Organizers: Jaijeet Roychowdhury, Joel Phillips
19.1
Computing Logic-Stage Delays Using Circuit Simulation and Symbolic Elmore Analysis
Clayton B. McDonald, Randal E. Bryant
.
19.2
A New Gate Delay Model for Simultaneous Switching and Its Applications
Liang-Chi Chen, SandeepK. Gupta, MelvinA.
Breuer. . .289
193
Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits
Geng
Bai,
Sudhakar
Bobba,
Ibrahim N.Hqjj.
.
295
xxv
Session 20
Memory, Bus
and Current Testing
Chair:
Magdy
S. Abadir
Organizers: Irith Pomeranz, Tim Cheng
20.1
Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories
Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu
.301
20.2
Improving Bus Test Via IDDT and Boundary Scan
Shih-yu
Yang, Christos
A. Papachristou, Massood Tabib-Azar
.307
20.3
Fault Characterizations and Design-for-Testability Technique for Detecting IDDQ Faults in
CMOS/BiCMOS Circuits
Kaamran Raahemifar, MajidAhmadi
.313
20.4
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores
Li Chen, Xiaoliang
Bai, SujitDey.317
Session
21
Panel: (When) Will FPGAs Kill ASIC's?
Chair and Organizer: Rob A.
Rutenbar
(When) Will FPGAs Kill ASICs?
Panel Members: Max Baron, Thomas Daniel, Rajeev Jayaraman,
Zvi
Or-Bach,
Jonathan Rose,
Carl Sechen.321
Session
22
Inductance
101
and Beyond
Chair: Phillip
Restie
Organizers: Joel Phillips, Noel
Menezes
22.1
Inductance
101:
Modeling and Extraction
Michael W. Beattie, Lawrence T. Pileggi
.323
22.2
Inductance
101:
Analysis and Design Issues
Kaushik Gala, David Blaauw, Junfeng Wang, Vladimir Zolotov,
Min
Zhao
.329
223
Modeling Magnetic Coupling for On-Chip Interconnect
Michael W. Beattie, Lawrence T. Pileggi
.335
22.4
Min/max On-Chip
Inductance Models and Delay Metrics
Yi-ChangLu, Mustafa Celik,
Так
Young, Lawrence T. Pileggi.
.341
Session
23
Memory Optimization Techniques for DSP Processors
Chair: Daniel Connors
Organizers: Dirk
Grunwald,
Marco
Di Natale
23.1
Utilizing Memory Bandwidth in DSP Embedded Processors
Catherine H. Gebotys
.347
232
Address Code Generation for Digital Signal Processors
Sathishkumar Udayanarayanan, Chaitali Chakrabarti
.353
233
Reducing Memory Requirements of Nested Loops for Embedded Systems
J. Ramanujam, JinpyoHong, Mahmut Kandemir, A. Narayan
.359
23.4
Detection of Partially Simultaneously Alive Signals in Storage Requirement Estimation for Data
Intensive Applications
Per
Gunnar
Kjeldsberg,
Francky
Catthoor,
Einar
J.
Aas.365
xxvi
Session 24
Technology
Dependant
Logic
Synthesis
Chair: Peichen Pan
Organizers: Jason
Cong,
Małgorzata Marek-Sadowska
24.1
A
New
Structural Pattern Matching Algorithm for Technology Mapping
Min
Zhao,
Sachin
S.
Sapatnekar
.371
24.2
Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect
SrirangK. Karandikar,
Sachin
S.
Sapatnekar.
.377
24.3
Latency and Latch Count Minimization in Wave Steered Circuits
Amit
Singh, Arindam Mukherjee,
Małgorzata
Marek-Sadowska
.383
24.4
Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping
Jason Cong,
Michail
Romesis
.389
Session
25
Collaborative and Distributed Design Frameworks
Chair: Satish Venkatesan
Organizers: Noel
Menezes,
Vivek Tiwari
25.1
Application of Constraint-Based Heuristics in Collaborative Design
Juan A. Carballo, Stephen W. Director
.395
25.2
A Universal Client for Distributed Networked Design and Computing
Franc Brglez, Hemang
Lavano
.401
25.3
Hypermedia-Aided Design
Darko Kirovski,
Milenko
Drinic, Miodrag Potkonjak
.407
25.4
A Framework for Object Oriented Hardware Specification, Verification, and Synthesis
T.Kuhn,
T.
Oppold,
M.
Winterholer,
W.
Rosenstiel,
Mark Edwards, YaronKashai
.413
Session
26
Panel: When Will the Analog Design How Catch Up with Digital Methodology?
Chair: Georges Gielen
Organizers: Mike Sottak, Mike Murray, Linda Kaye
Panel Members: Mar Hershenson, Ken
Kundért,
Philippe Magarshack, Akria Matsuzawa, Ronald A. Rohrer,
Ping Yang
.
419
Session
27
Closing the Gap Between ASIC and Custom: Design Examples
Chair: Bryan Ackland
Organizer: Kurt Keutzer
27.1
Achieving
550
Mhz in
an ASIC Methodology
D. G. Chinnery, B.
Nikolić, Kurt
Keutzer
.420
27.2
A Semi-Custom Design Flow in High-Performance Microprocessor Design
Gregory A. Northrop, Pong-Fei
Lu
.426
273
Reducing the Frequency Gap Between ASIC and Custom Designs: A Custom Perspective
StephenE. Rich, Matthew J.Parker, Jim Schwartz.
.432
Session
28
Energy and Hexibility Driven Scheduling
Chair: Marco
Di Natale
Organizers: Donatella Sciuto, Luciano Lavagno
28.1
Low-Energy Intra-Task Voltage Scheduling Using Static Timing Analysis
Dongkun Shin, Jihong Kim, Seongsoo Lee
.438
xxvii
28.2
Battery-Aware Static Scheduling for Distributed Real-Time Embedded Systems
JiongLuo, Niraj K. Jha
.444
28.3
An Approach to Incremental Design of Distributed Embedded Systems
Paul Pop,
Petru
Eles,
Traían
Pop,
Zebo
Peng
.450
Session
29
Representation and Optimization for Digital Arithmetic Circuits
Chair: Miodrag Potkonjak
Organizers: Kazutoshi Wakabayashi, Rajesh K. Gupta
29.1
Signal Representation Guided Synthesis Using Carry-Save Adders For Synchronous Data-path Circuits
Zhan Yu, Meng-Lin Yu, Alan
N.
Willson, Jr.
.456
29.2
Improved Merging of Datapath Operators using Information Content and Required Precision Analysis
Anmol Mathur, Sanjeev Saluja
.462
29.3
Digital Filter Synthesis Based on Minimal Signed Digit Representation
In-Cheol Park, Hyeong-Ju Kang
.468
Session
30
Techniques for IP Protection
Chair: Ian R. Mackintosh
Organizers: Kenji Yoshida, Majid Sarrafeadeh
30.1
Publicly Detectable Techniques for the Protection of Virtual Components
Gang ()u
.474
30.2
Watermarking of SAT using Combinatorial Isolation Lemmas
Rupak Majumdar, Jennifer L. Wong
.480
303
Watermarking Graph Partitioning Solutions
Greg Wolfe, Jennifer L. Wong, Miodrag Potkonjak
.486
30.4
Hardware Metering
Farinaz Koushanfar, GangQu
.490
Session
31
Visualization and Animation for VLSI Design
Chair: Chandu Visweswariah
Organizers: Chandu Visweswariah, Majid Sarrafeadeh
31.1
Technical Visualizations in VLSI Design
Phillip J.
Restie
.494
31.2
Using Texture Mapping with Mipmapping to Render a VLSI Layout
Jeff Solomon, Mark Horowitz
.500
31
J
Web-based Algorithm Animation
Marc Nqjork
.506
Session
32
Application-Specific Customization for Systems-on-a-Chip
Chair:
Kees Vissers
Organizers: Kurt Keutzer, Dirk
Grunwald
32.1
Speeding Up Control-Dominated Applications through Microarchitectural Customizations
in Embedded Processors
Peter
Petrov,
Alex Orailoglu
. 572
xxviii
32.2
Automatic
Generation
of Application-Specific Architectures for Heterogeneous Multiprocessor
System-on-Chip
Damien Lyonnard, Sungjoo Yoo,
Amer
Baghdadi, Ahmed A. Jerraya
.518
32.3
Dynamic Voltage Scaling and Power Management for Portable Systems
Tajana Simunic,
Luca
Benini,
Andrea Acquaviva, Peter Glynn, Giovanni
De Micheli.
524
Session
33
Satisfiability Solvers and Techniques
Chair:
Karem
A. Sakallah
Organizers: Andrew B. Kahng, Kurt Keutzer, Limor Fix
33.1
Chaff: Engineering an Efficient SAT Solver
Matthew W. Moskewicz, ConorF. Madigan, YingZhao, Lintao Zhang, SharadMalik
.530
33.2
Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image Computation
Aarti Gupta, Anubhav Gupta, Zijiang Yang, PranavAshar
.536
33.3
SATIRE: A New Incremental Satisfiability Engine
Jesse Whittemore, Joonyoung
Kim, Karem
Sakallah
.542
33.4
A Framework for Low Complexity Static Learning
Emil
Gizdarski, Hideo
Fuj
iwara
.546
Session
34
Power and Interconnect Analysis
Chair: L. Miguel
Silveira
Organizers: Joel Phillips, Mustafa Celik
34.1
Fast Power/Ground Network Optimization Based on Equivalent Circuit Modeling
X.-D. Sheldon Tan, C.-J. Richard Shi
.550
34.2
An Interconnect Energy Model Considering Coupling Effects
Taku
Uchino, Jason Cong
.555
34.3
Efficient Large-Scale Power Grid Analysis Based on Preconditioned Krylov-Subspace Iterative Methods
Tsung-Hao Chen, Charlie Chung-Ping Chen
.559
34.4
Using Conduction Modes Basis Functions for Efficient Electromagnetic Analysis of On-Chip and
Off-Chip Interconnect
Luca
Daniel, Alberto Sangiovanni-Vincentelli, Jacob White
.563
34.5
Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs
AmirH. Ajami, Kaustav Banerjee, Massoud Pedram,
Lukas
P.P.P. van
Ginneken.567
Session
35
Domain Specific Design Methodologies
Chair: Yosinori Watanabe
Organizers: Anand Raghunathan, Shin-ichi
Minato
35.1
VHDL-Based Design and Design Methodology for Reusable High Performance Direct Digital Frequency
Synthesizers
Ireneusz
Janiszewski,
Bernhard
Hoppe,
Hermann Meuth
.3/5
35.2
Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-Bit Symmetric
Block Ciphers
Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim
.
3/v
353
MetaCores: Design and Optimization Techniques
Seapahn Meglerdichian, Farinaz Koushanfar, Advait Mogre, Dusan Petranovw, Miodrag Potkonjak
.585
xxix
Session 36
Panel:
Debate:
Who has Nanometer
Design
Under Control?
Chair: Andrew B. Kahng
Organizer:
Bing
Sheu
Panel Members: Nancy Nettleton, John Cohn, Shekhar Borkar, Louis Scheffer, Ed Cheng, Sang Wang
.591
Session
37
Analysis and Implementation for Embedded Systems
Chair: Grant Martin
Organizers: Dirk
Grunwald, Kurt
Keutzer, Luciano Lavagno
37.1
A Hardware/Software Co-design Flow and IP Library Based of Simulink ™
L. M. Reyneri, F. Cucinotta,
A. Serra,
L.
Lavagno
.593
37.2
System-Level Power/Performance Analysis for Embedded Systems Design
Amit Nándi,
Radu Marculescu
.599
37.3
High-level Software Energy Macro-modeling
T. K. Tan, A. Raghunathan, G. Lakshminarayana,
N.
K. Jha
.605
Session
38
Industrial Case Studies in Verification
Chair: Carl Pixley
Organizers: Anand Raghunathan, Carl Pixley
38.1
Model Checking of S3C2400X Industrial Embedded
SOC
Product
Hoon
Choi, Byeongwhee Yun, Yuntae Lee, Hyunglae
Roh
.611
38.2
Semi-Formal Test Generation with
Geneviève
Julia Dushina, Mike Benjamin, Daniel
Geist.617
383
A Transaction-Based Unified Simulation/Emulation Architecture for Functional Verification
Murali
Kudlugi,
Soha Hassoun,
Charles Selvidge, Duaine Pryor
.623
Session
39
Integrated High-Level Synthesis Based Solutions
Chair: Kazutoshi Wakabayashi
Organizers: Kazutoshi Wakabayashi, Rajesh K. Gupta
39.1
Integrated High-Level Synthesis and Power-Net Routing for Digital Design under Switching Noise
Constraints
AlexDoboli,
Ranga Vemuri
.629
39.2
Integrating Scheduling and Physical Design into a Coherent Compilation Cycle for
Reconfigurable
Computing Architectures
Kia Bazargan,
Seda
Ogrenci, Majid Sarrafeadeh
.635
39
J
Statistical Design Space Exploration for Application-Specific Unit Synthesis
Davide Brunì, Alessandro Bugliolo, Luca Benini
.641
Session
40
Timing Verification and Simulation
Chair Ashok Vittal
Organizer:
Narendra
Shenoy
40.1
Static Scheduling of Multiple Asynchronous Domains For Functional Verification
Murali
Kudlugi, Charles Selvidge, Russell Tessier
.647
40.2
Functional Correlation Analysis in Crosstalk Induced
Criticai
Paths Identification
Tong
Xiao,
Małgorzata Marek-Sadowska
.653
xxx
40.3
An Advanced Timing Characterization Method Using Mode Dependency
Hakan
Yalcin, Robert Palermo, Mohammad Mortazavi, Cyrus Bamji,
Karem
Sakallah,
John Hayes
.657
40.4
Fast Statistical Timing Analysis By Probabilistic Event Propagation
Jing-JiaLiou, Kwang-Ting Cheng, Sandip Kundu, Angela
Krstić
.661
Session
41
On-Chip Communication Architectures
Chair: Anand Raghunathan
Organizers: Anand Raghunathan, Sharad Malik
41.1
Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design
M. Sgroi, M. Sheets,
A. Mihal, K.
Keutzer,
S.
Malik, J. Rabaey, A. Sangiovanni-Vincentelli
.667
41.2 MicroNetwork-Based Integration
for SOCs
Drew Wingard
.673
41.3
On-Chip Communication Architecture for OC-768 Network Processors
Faraydon
Karím,
Anh Nguyen, SujitDey, RameshRao
.678
41.4
Route Packets, Not Wires: On-Chip Interconnection Networks
William J. Dally, Brian Towles
.684
Session
42
Compiler and Architecture Interactions
Chair: Stephen Neuendorffer
Organizers: Donatella
Scruto,
Marco
Di Natale
42.1
Dynamic Management of Scratch-Pad Memory Space
M. Kandemir, J. Ramanujam, M. J.
Irwin, N.
Vijaykrishnan, I. Kadayif, A. Parikh
.690
42.2
Clustered VLIW Architectures with Predicated Switching
Margarida
F. Jacome, Gustavode
Veciana, Satish
Pillai
.696
423
High-Quality Operation Binding for Clustered VLIW Datapaths
Viktor S. Lapinskii,
Margarida
F. Jacome, Gustavo
A. de
Veciana
.702
42.4
Fast Bit-True Simulation
Holger
Keding, Martin Coors,
Olaf Lüthje, Heinrich Meyr.708
Session
43
Timing with Crosstalk
Chair:
Sachin
S.
Sapatnekar
Organizers: Jaijeet Roychowdhury, Mustafa Celik
43.1
Timing Analysis with Crosstalk as
Fixpoints
on Complete Lattice
Hai
Zhou,
Narendra
Shenoy, William Nicholls
.714
43.2
Driver Modeling and Alignment for Worst-Case Delay Noise
Suparnas
Sirichotiyakul, David Blaauw, Chanhee Oh, Rafi Levy, Vladimir Zolotov, Jingyan Zuo
.720
433
False Coupling Interactions in Static Timing Analysis
Ravishankar Arunachalam, Ronald D. Blanton, Lawrence T.
Fileggi
.726
43.4
Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique
Ki-WookKim, Seong-OokJung, PrashantSaxena,
C. L.
Liu, Sung-MoKang
.732
Session
44
Low Power Design: Systems to Interconnect
Chair: Vivek Tiwari
Organizers:
Ingrid Verbauwhede,
Tadahiro Kuroda
44.1
Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optunfeation
W. Wang, A. Raghunathan, G. Labhrnmarayana,
N.
K. Jha
.738
XXXI
44.2
A2BC:
Adaptive Address Bus Coding for Low Power Deep Sub-Micron Designs
Jörg Henkel,
Haris Lekatsas
.744
44.3
Coupling-Driven Bus
Design
for Low-Power Application-Specific Systems
Youngsoo Shin, Takayasu Sakurai
.750
44.4
Modeling and Minimization of Interconnect Energy Dissipation in Nanometer Technologies
Clark
N.
Taylor, Sujit
Dey, Yi
Zhao
.754
44.5
A True Single-Phase 8-bit Adiabatic Multiplier
SuhwanKim, Conrad
H
.
Ziesler, Marios C. Papaefihymiou
.758
Session
45
Floorplanning Representations and Placement Algorithms
Chair: Ralph H. J. M. Otten
Organizers: Louis Scheffer, Patrick Groeneveld
45.1
TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans
Jai-MingLin, Yao-Wen Chang
.764
45.2
Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List
Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici
Cai,
Chung-Kuan Cheng,
Jun Gu.
770
45.3
Improved Cut Sequences for Partitioning Based Placement
Mehmet
Can Yildiz, Patrick H. Madden
.776
45.4
Timing Driven Placement using Physical Net Constraints
Bill Halpin,
C. Y.
Roger Chen, Naresh Sehgal
.780
45.5
From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip
L.
Benini,
L.
Macchiarulo,
A. Macii,
E.
Macii,
M. Poncino
.784
Session
46
Panel:
What
Drives EDA Innovation?
Chair:
Steven
Schulz
Organizer: Georgia
Marszałek
Panel
Members:
Greg Hinckley, Greg Spirakis, Karen Vahtra, John Darringer, J. George Janac, Handel H.
Jones.790
Session 47
Signal
Integrity: Avoidance and Test Techniques
Chair: Anirudh Devgan
Organizers: Chandu Visweswariah, Kenji Yoshida
47.1
Built-in Self-Test for Signal Integrity
MehrdadNourani, Amir A ttar ha
.792
47.2
Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for
Distributed RLC Interconnects
Kaustav Banerjee,
Amit
Mehrotra
.798
47
J
Modeling and Analysis of Differential Signaling for Minimizing Inductive Cross-Talk
Yehia Massoud, Jamil
Kawa,
Don MacMillen, Jacob White
.804
Session
48
Novel Approaches to Microprocessor Design and Verification
Chain Derek Beatty
Organizers: Carl Pixley, Shin-ichi
Minato
48.1
Automated Pipeline Design
Daniel Kroening, Wolfgang J.
Pend
.
xxxii
48.2
A New Verification Methodology for Complex Pipeline Behavior
Kazuyoshi Kohno, Nobu Matsumoto
.816
48.3
Pre-silicon Verification of the Alpha
21364
Microprocessor Error Handling System
Richard Lee, Benjamin Tsien
.^22
Session
49
Scheduling Techniques for Power Management
Chair: Donatella Sciuto
Organizers:
Diederik Verkest,
Luciano Lavagno
49.1
Energy Efficient Fixed-Priority Scheduling for
Real-Time
Systems on Variable Voltage Processors
Gang Quan, Xiaobo (Sharon)
Ни
.828
49.2
Dynamic Power Management in a Mobile Multimedia System with Guaranteed Quality-of-Service
Qinru Qiu, Qing Wu, Massoud Pedram
.834
49.3
Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems
JinfengLiu, PaiH.
Chou,
Nader Bagherzadeh, FadiKurdahi
.840
Session
50
Novel Devices and Yield Optimization
Chair: Chandu Visweswariah
Organizers: Chandu Visweswariah, Ralph H. J. M. Otten
50.1
Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration
Rongtian Zhang, KaushikRoy, Cheng
-Кок
Koh, DavidB. Janes
.846
50.2
Two-Dimensional Position Detection System with MEMS Accelerometer for MOUSE Applications
SeungbaeLee, Gi-JoonNam, JunseokChae, HanseupKim, AlanJ. Drake
.852
50
J
Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided
Search
Frank
Schenkel,
Michael Pronath,
Stephan
Znala,
Robert Schwencker, Helmut Graeb, KurtAntreich
.858
Author Index
.
865
xxxiii |
| any_adam_object | 1 |
| author_corporate | Design Automation Conference (Association for Computing Machinery) Las Vegas, Nev |
| author_corporate_role | aut |
| author_facet | Design Automation Conference (Association for Computing Machinery) Las Vegas, Nev |
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| classification_tum | DAT 810f |
| ctrlnum | (OCoLC)634054955 (DE-599)BVBBV013872392 |
| discipline | Informatik |
| format | Conference Proceeding Book |
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| spelling | Design Automation Conference (Association for Computing Machinery) 38 2001 Las Vegas, Nev. Verfasser (DE-588)6033467-8 aut Proceedings 2001 Las Vegas Convention Center, Las Vegas, NV, June 18 - 22, 2001 38th Design Autmation Conference, DAC DAC 2001 Proceedings of the 38th Design Automation Conference New York, NY ACM Press 2001 XXXIII, 868 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier CAD (DE-588)4069794-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 2001 Las Vegas Nev. gnd-content CAD (DE-588)4069794-0 s DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009489421&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Proceedings 2001 Las Vegas Convention Center, Las Vegas, NV, June 18 - 22, 2001 CAD (DE-588)4069794-0 gnd |
| subject_GND | (DE-588)4069794-0 (DE-588)1071861417 |
| title | Proceedings 2001 Las Vegas Convention Center, Las Vegas, NV, June 18 - 22, 2001 |
| title_alt | DAC 2001 Proceedings of the 38th Design Automation Conference |
| title_auth | Proceedings 2001 Las Vegas Convention Center, Las Vegas, NV, June 18 - 22, 2001 |
| title_exact_search | Proceedings 2001 Las Vegas Convention Center, Las Vegas, NV, June 18 - 22, 2001 |
| title_full | Proceedings 2001 Las Vegas Convention Center, Las Vegas, NV, June 18 - 22, 2001 38th Design Autmation Conference, DAC |
| title_fullStr | Proceedings 2001 Las Vegas Convention Center, Las Vegas, NV, June 18 - 22, 2001 38th Design Autmation Conference, DAC |
| title_full_unstemmed | Proceedings 2001 Las Vegas Convention Center, Las Vegas, NV, June 18 - 22, 2001 38th Design Autmation Conference, DAC |
| title_short | Proceedings 2001 |
| title_sort | proceedings 2001 las vegas convention center las vegas nv june 18 22 2001 |
| title_sub | Las Vegas Convention Center, Las Vegas, NV, June 18 - 22, 2001 |
| topic | CAD (DE-588)4069794-0 gnd |
| topic_facet | CAD Konferenzschrift 2001 Las Vegas Nev. |
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