Verfügbarkeit: Field programmable logic and applications

Field programmable logic and applications: 11th international conference, FPL 2001, Belfast, Northern Ireland, UK, August 27 - 29, 2001 ; proceedings

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Bibliographische Detailangaben
Format:	Tagungsbericht Buch
Sprache:	English
Veröffentlicht:	Berlin ; Heidelberg ; New York ; Barcelona ; Hong Kong ; London Springer 2001
Schriftenreihe:	Lecture notes in computer science 2147
Schlagworte:	Logique à réseau programmable - Congrès Réseaux logiques programmables par l'utilisateur - Congrès Field programmable gate arrays > Congresses Programmable array logic > Congresses Field programmable gate array Rekonfiguration Konferenzschrift > 2001 > Belfast
Online-Zugang:	Inhaltsverzeichnis
Beschreibung:	XV, 665 S. Ill., graph. Darst.
ISBN:	3540424997

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adam_text	TABLE OF CONTENTS INVITED KEYNOTE 1 TECHNOLOGY TRENDS AND ADAPTIVE COMPUTING . 1 M.J. FLYNN AND A.A. LIDDICOAT ARCHITECTURAL FRAMEWORKS PROTOTYPING FRAMEWORK FOR RECONFIGURABLE PROCESSORS . 6 S. SAWITZKI, S. K¨OHLER, AND R.G. SPALLEK AN EMULATOR FOR EXPLORING RAPID CONFIGURABLE COMPUTING ARCHITECTURES . 17 C. FISHER, K. RENNIE, G. XING, S.G. BERG, K. BOLDING, J. NAEGLE, D. PARSHALL, D. PORTNOV, A. SULEJMANPASIC, AND C. EBELING PLACE AND ROUTE 1 A NEW PLACEMENT METHOD FOR DIRECT MAPPING INTO LUT-BASED FPGAS . 27 J. ABKE AND E. BARKE FGREP - FAST GENERIC ROUTING DEMAND ESTIMATION FOR PLACED FPGA CIRCUITS . 37 P. KANNAN, S. BALACHANDRAN, AND D. BHATIA ARCHITECTURE MACROCELL ARCHITECTURES FOR PRODUCT TERM EMBEDDED MEMORY ARRAYS . 48 E. LIN AND S.J.E. WILTON GIGAHERTZ RECONFIGURABLE COMPUTING USING SIGE HBT BICMOS FPGAS . 59 B.S. GODA, R.P. KRAFT, S.R. CARLOUGH, T.W. KRAWCZYK JR., AND J.F. MCDONALD MEMORY SYNTHESIS FOR FPGA-BASED RECONFIGURABLE COMPUTERS . 70 A. KASAT, I. OUAISS, AND R. VEMURI DSP 1 IMPLEMENTING A HIDDEN MARKOV MODEL SPEECH RECOGNITION SYSTEM IN PROGRAMMABLE LOGIC . 81 S.J. MELNIKOFF, S.F. QUIGLEY, AND M.J. RUSSELL IMPLEMENTATION OF (NORMALISED) RLS LATTICE ON VIRTEX . 91 F. ALBU, J. KADLEC, C. SOFTLEY, R. MATOUSEK, A. HERMANEK, N. COLEMAN, AND A. FAGAN X TABLE OF CONTENTS ACCELERATING MATRIX PRODUCT ON RECONFIGURABLE HARDWARE FOR SIGNAL PROCESSING . 101 A. AMIRA, A. BOURIDANE, AND P. MILLIGAN SYNTHESIS STATIC PROFILE-DRIVEN COMPILATION FOR FPGAS . 112 S. CADAMBI AND S.C. GOLDSTEIN SYNTHESIZING RTL HARDWARE FROM JAVA BYTE CODES . 123 M.J. WIRTHLIN, B.L. HUTCHINGS, AND C. WORTH PUMA ++: FROM BEHAVIORAL SPECIFICATION TO MULTI-FPGA-PROTOTYPE . 133 K. HARBICH AND E. BARKE ENCRYPTION SECURE CONFIGURATION OF FIELD PROGRAMMABLE GATE ARRAYS . 142 T. KEAN SINGLE-CHIP FPGA IMPLEMENTATION OF THE ADVANCED ENCRYPTION STANDARD ALGORITHM . 152 M. MCLOONE AND J.V. MCCANNY JBITS TM IMPLEMENTATIONS OF THE ADVANCED ENCRYPTION STANDARD (RIJNDAEL) . 162 S. MCMILLAN AND C. PATTERSON RUNTIME RECONFIGURATION 1 TASK-PARALLEL PROGRAMMING OF RECONFIGURABLE SYSTEMS . 172 M. WEINHARDT AND W. LUK CHIP-BASED RECONFIGURABLE TASK MANAGEMENT . 182 G. BREBNER AND O. DIESSEL CONFIGURATION CACHING AND SWAPPING . 192 S. SUDHIR, S. NATH, AND S.C. GOLDSTEIN GRAPHICS AND VISION MULTIPLE STEREO MATCHING USING AN EXTENDED ARCHITECTURE . 203 M. ARIAS-ESTRADA AND J.M. XICOTENCATL IMPLEMENTATION OF A NURBS TO B´EZIER CONVERSOR WITH CONSTANT LATENCY . 213 P.N. MALL´ON, M. B´OO, AND J.D. BRUGUERA RECONFIGURABLE FRAME-GRABBER FOR REAL-TIME AUTOMATED VISUAL INSPECTION (RT-AVI) SYSTEMS . 223 S. A.CUENC A,F.IB AR R A,ANDR.AL VAR EZ TABLE OF CONTENTS XI INVITED KEYNOTE 2 PROCESSING MODELS FOR THE NEXT GENERATION NETWORK [ABSTRACT] . 232 J. LAWRENCE PLACE AND ROUTE 2 TIGHTLY INTEGRATED PLACEMENT AND ROUTING FOR FPGAS . 233 P. KANNAN AND D. BHATIA GAMBIT: A TOOL FOR THE SIMULTANEOUS PLACEMENT AND DETAILED ROUTING OF GATE-ARRAYS . 243 J. KARRO AND J. COHOON NETWORKING RECONFIGURABLE ROUTER MODULES USING NETWORK PROTOCOL WRAPPERS . 254 F. BRAUN, J. LOCKWOOD, AND M. WALDVOGEL DEVELOPMENT OF A DESIGN FRAMEWORK FOR PLATFORM-INDEPENDENT NETWORKED RECONFIGURATION OF SOFTWARE AND HARDWARE . 264 Y. HA, B. MEI, P. SCHAUMONT, S. VERNALDE, R. LAUWEREINS, AND H. DE MAN PROCESSOR INTERACTION THE MOLEN µ -CODED PROCESSOR . 275 S. VASSILIADIS, S. WONG, AND S. COT¸OFANA RUN-TIME OPTIMIZED RECONFIGURATION USING INSTRUCTION FORECASTING . 286 M. ILIOPOULOS AND T. ANTONAKOPOULOS CRISP: A TEMPLATE FOR RECONFIGURABLE INSTRUCTION SET PROCESSORS . 296 P. OP DE BEECK, F. BARAT, M. JAYAPALA, AND R. LAUWEREINS APPLICATIONS EVALUATION OF AN FPGA IMPLEMENTATION OF THE DISCRETE ELEMENT METHOD . 306 B. CARRION SCHAFER, S.F. QUIGLEY, AND A.H.C. CHAN RUN-TIME PERFORMANCE OPTIMIZATION OF AN FPGA-BASED DEDUCTION ENGINE FOR SAT SOLVERS . 315 A. DANDALIS, V.K. PRASANNA, AND B. THIRUVENGADAM A RECONFIGURABLE EMBEDDED INPUT DEVICE FOR KINETICALLY CHALLENGED PERSONS . 326 A. DOLLAS, K. PAPADEMETRIOU, N. ASLANIDES, AND T. KEAN XII TABLE OF CONTENTS METHODOLOGY 1 BUBBLE PARTITIONING FOR LUT-BASED SEQUENTIAL CIRCUITS . 336 F. WOLZ AND R. KOLLA RAPID CONSTRUCTION OF PARTIAL CONFIGURATION DATASTREAMS FROM HIGH-LEVEL CONSTRUCTS USING JBITS . 346 S. SINGH AND P. JAMES-ROXBY PLACING,ROUTING,AND EDITING VIRTUAL FPGAS . 357 L. LAGADEC, D. LAVENIER, E. FABIANI, AND B. POTTIER DSP 2 VIRTEX IMPLEMENTATION OF PIPELINED ADAPTIVE LMS PREDICTOR IN ELECTRONIC SUPPORT MEASURES RECEIVER . 367 L.-K. TING, R. WOODS, AND C. COWAN A MUSIC SYNTHESIZER ON FPGA . 377 T. SAITO, T. MARUYAMA, T. HOSHINO, AND S. HIRANO MOTIVATION FROM A FULL-RATE SPECIFIC DESIGN TO A DSP CORE APPROACH FOR GSM VOCODERS . 388 S. SHEIDAEI, H. NOORI, A. AKBARI, AND H. PEDRAM LOOPS AND SYSTOLIC LOOP TILING FOR RECONFIGURABLE ACCELERATORS . 398 S. DERRIEN AND S. RAJOPADHYE THE SYSTOLIC RING: A DYNAMICALLY RECONFIGURABLE ARCHITECTURE FOR EMBEDDED SYSTEMS . 409 G. SASSATELLI, L. TORRES, J. GALY, G. CAMBON, AND C. DIOU A N -BIT RECONFIGURABLE SCALAR QUANTISER . 420 O. CADENAS AND G. MEGSON IMAGE PROCESSING REAL TIME MORPHOLOGICAL IMAGE CONTRAST ENHANCEMENT IN VIRTEX FPGA . 430 J. KASPEREK DEMONSTRATING REAL-TIME JPEG IMAGE COMPRESSION-DECOMPRESSION USING STANDARD COMPONENT IP CORES ON A PROGRAMMABLE LOGIC BASED PLATFORM FOR DSP AND IMAGE PROCESSING . 441 A. SIMPSON, J. HUNTER, M. WYLIE, Y. HU, AND D. MANN DESIGN AND IMPLEMENTATION OF AN ACCELERATED GABOR FILTER BANK USING PARALLEL HARDWARE . 451 N. VOSS AND B. MERTSCHING TABLE OF CONTENTS XIII INVITED KEYNOTE 3 THE EVOLUTION OF PROGRAMMABLE LOGIC: PAST,PRESENT,AND FUTURE PREDICTIONS [ABSTRACT] . 461 B. CARTER RUNTIME RECONFIGURATION 2 DYNAMICALLY RECONFIGURABLE CORES . 462 J. MACBETH AND P. LYSAGHT RECONFIGURABLE BREAKPOINTS FOR CO-DEBUG . 473 T. PRICE AND C. PATTERSON FAULTS USING DESIGN-LEVEL SCAN TO IMPROVE FPGA DESIGN OBSERVABILITY AND CONTROLLABILITY FOR FUNCTIONAL VERIFICATION . 483 T. WHEELER, P. GRAHAM, B. NELSON, AND B. HUTCHINGS FPGA-BASED FAULT INJECTION TECHNIQUES FOR FAST EVALUATION OF FAULT TOLERANCE IN VLSI CIRCUITS . 493 P. CIVERA, L. MACCHIARULO, M. REBAUDENGO, M. SONZA REORDA, AND M. VIOLANTE METHODOLOGY 2 A GENERIC LIBRARY FOR ADAPTIVE COMPUTING ENVIRONMENTS . 503 T. NEUMANN AND A. KOCH GENERATIVE DEVELOPMENT SYSTEM FOR FPGA PROCESSORS WITH ACTIVE COMPONENTS . 513 S. R¨UHL, P. DILLINGER, S. HEZEL, AND R. M¨ANNER COMPILATION INCREASING THE SCHEDULING SCOPE FOR MULTI-MEMORY- FPGA-BASED CUSTOM COMPUTING MACHINES . 523 J.M.P. CARDOSO AND H.C. NETO SYSTEM LEVEL TOOLS FOR DSP IN FPGAS . 534 J. HWANG, B. MILNE, N. SHIRAZI, AND J.D. STROOMER ARITHMETIC PARAMETERIZED FUNCTION EVALUATION FOR FPGAS . 544 O.MENC ER ,N.BOUL L I S ,W.LUK,ANDH.ST YL ES ECIENT CONSTANT COECIENT MULTIPLICATION USING ADVANCED FPGA ARCHITECTURES . 555 M.J. WIRTHLIN AND B. MCMURTREY XIV TABLE OF CONTENTS A DIGIT-SERIAL STRUCTURE FOR RECONFIGURABLE MULTIPLIERS . 565 C. VISAVAKUL, P.Y.K. CHEUNG, AND W. LUK FPGA RESOURCE REDUCTION THROUGH TRUNCATED MULTIPLICATION . 574 K.E. WIRES, M.J. SCHULTE, AND D. MCCARLEY SHORT PAPERS 1 ECIENT MAPPING OF PRE-SYNTHESIZED IP-CORES ONTO DYNAMICALLY RECONFIGURABLE ARRAY ARCHITECTURES . 584 J. BECKER, N. LIEBAU, T. PIONTECK, AND M. GLESNER AN FPGA-BASED SYNTACTIC PARSER FOR REAL-LIFE ALMOST UNRESTRICTED CONTEXT-FREE GRAMMARS . 590 C. CIRESSAN, E. SANCHEZ, M. RAJMAN, AND J.-C. CHAPPELIER HARDWARE-SOFTWARE PARTITIONING: A RECONFIGURABLE AND EVOLUTIONARY COMPUTING APPROACH . 595 J. HARKIN, T.M. MCGINNITY, AND L.P. MAGUIRE AN APPROACH TO REAL-TIME VISUALIZATION OF PIV METHOD WITH FPGA . 601 T. MARUYAMA, Y. YAMAGUCHI, AND A. KAWASE FPGA-BASED DISCRETE WAVELET TRANSFORMS SYSTEM . 607 M. NIBOUCHE, A. BOURIDANE, F. MURTAGH, AND O. NIBOUCHE X-MATCHPRO: A PROASIC-BASED 200 MBYTES/S FULL-DUPLEX LOSSLESS DATA COMPRESSOR . 613 J.L. N´UNEZ, C. FEREGRINO, S. JONES, AND S. BATEMAN ARITHMETIC OPERATION ORIENTED RECONFIGURABLE CHIP: RHW . 618 T. YAMAUCHI, S. NAKAYA, T. INUO, AND N. KAJIHARA SHORT PAPERS 2 INITIAL ANALYSIS OF THE PROTEUS ARCHITECTURE . 623 M. DALES BUILDING ASYNCHRONOUS CIRCUITS WITH JBITS . 628 E. KELLER CASE STUDY OF INTEGRATION OF RECONFIGURABLE LOGIC AS A COPROCESSOR INTO A SCI-CLUSTER UNDER RT-LINUX . 633 T. LEHMANN AND A. SCHRECKENBERG A RECONFIGURABLE APPROACH TO PACKET FILTERING . 638 R. SINNAPPAN AND S. HAZELHURST FPGA-BASED MODELLING UNIT FOR HIGH SPEED LOSSLESS ARITHMETIC CODING . 643 R. STEFO, J.L. N´UNEZ, C. FEREGRINO, S. MAHAPATRA, AND S. JONES TABLE OF CONTENTS XV A DATA RE-USE BASED COMPILER OPTIMIZATION FOR FPGAS . 648 R. SUBRAMANIAN AND S. PANDE DIJKSTRA'S SHORTEST PATH ROUTING ALGORITHM IN RECONFIGURABLE HARDWARE . 653 M. TOMMISKA AND J. SKYTT¨A A SYSTEM ON CHIP FOR POWER LINE COMMUNICATIONS ACCORDING TO EUROPEAN HOME SYSTEMS SPECIFICATIONS . 658 I. URRIZA, J.I. GARC´*A-NICOL´AS, A. SANZ, AND A. VALDOVINOS AUTHOR INDEX . 663
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spelling	Field programmable logic and applications 11th international conference, FPL 2001, Belfast, Northern Ireland, UK, August 27 - 29, 2001 ; proceedings Gordon Brebner ; Roger Woods (ed.) field-programmable Berlin ; Heidelberg ; New York ; Barcelona ; Hong Kong ; London Springer 2001 XV, 665 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Lecture notes in computer science 2147 Logique à réseau programmable - Congrès Réseaux logiques programmables par l'utilisateur - Congrès Field programmable gate arrays Congresses Programmable array logic Congresses Field programmable gate array (DE-588)4347749-5 gnd rswk-swf Rekonfiguration (DE-588)4306238-6 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 2001 Belfast gnd-content Field programmable gate array (DE-588)4347749-5 s DE-604 Rekonfiguration (DE-588)4306238-6 s Brebner, Gordon Sonstige oth FPL 11 2001 Belfast Sonstige (DE-588)10024673-4 oth Lecture notes in computer science 2147 (DE-604)BV000000607 2147 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009484540&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis
spellingShingle	Field programmable logic and applications 11th international conference, FPL 2001, Belfast, Northern Ireland, UK, August 27 - 29, 2001 ; proceedings Lecture notes in computer science Logique à réseau programmable - Congrès Réseaux logiques programmables par l'utilisateur - Congrès Field programmable gate arrays Congresses Programmable array logic Congresses Field programmable gate array (DE-588)4347749-5 gnd Rekonfiguration (DE-588)4306238-6 gnd
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title	Field programmable logic and applications 11th international conference, FPL 2001, Belfast, Northern Ireland, UK, August 27 - 29, 2001 ; proceedings
title_alt	field-programmable
title_auth	Field programmable logic and applications 11th international conference, FPL 2001, Belfast, Northern Ireland, UK, August 27 - 29, 2001 ; proceedings
title_exact_search	Field programmable logic and applications 11th international conference, FPL 2001, Belfast, Northern Ireland, UK, August 27 - 29, 2001 ; proceedings
title_full	Field programmable logic and applications 11th international conference, FPL 2001, Belfast, Northern Ireland, UK, August 27 - 29, 2001 ; proceedings Gordon Brebner ; Roger Woods (ed.)
title_fullStr	Field programmable logic and applications 11th international conference, FPL 2001, Belfast, Northern Ireland, UK, August 27 - 29, 2001 ; proceedings Gordon Brebner ; Roger Woods (ed.)
title_full_unstemmed	Field programmable logic and applications 11th international conference, FPL 2001, Belfast, Northern Ireland, UK, August 27 - 29, 2001 ; proceedings Gordon Brebner ; Roger Woods (ed.)
title_short	Field programmable logic and applications
title_sort	field programmable logic and applications 11th international conference fpl 2001 belfast northern ireland uk august 27 29 2001 proceedings
title_sub	11th international conference, FPL 2001, Belfast, Northern Ireland, UK, August 27 - 29, 2001 ; proceedings
topic	Logique à réseau programmable - Congrès Réseaux logiques programmables par l'utilisateur - Congrès Field programmable gate arrays Congresses Programmable array logic Congresses Field programmable gate array (DE-588)4347749-5 gnd Rekonfiguration (DE-588)4306238-6 gnd
topic_facet	Logique à réseau programmable - Congrès Réseaux logiques programmables par l'utilisateur - Congrès Field programmable gate arrays Congresses Programmable array logic Congresses Field programmable gate array Rekonfiguration Konferenzschrift 2001 Belfast
url	http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009484540&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
volume_link	(DE-604)BV000000607
work_keys_str_mv	AT brebnergordon fieldprogrammablelogicandapplications11thinternationalconferencefpl2001belfastnorthernirelandukaugust27292001proceedings AT fplbelfast fieldprogrammablelogicandapplications11thinternationalconferencefpl2001belfastnorthernirelandukaugust27292001proceedings AT brebnergordon fieldprogrammable AT fplbelfast fieldprogrammable

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