Test pattern generation and verification for logic circuits: an implication graph based approach
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Abschlussarbeit Buch |
| Sprache: | English |
| Veröffentlicht: |
München
Hieronymus
2001
|
| Ausgabe: | Als Typoskript gedr. |
| Schriftenreihe: | Informationstechnik
|
| Schlagworte: | |
| Beschreibung: | III, 190, XXVI S. Ill., graph. Darst. |
| ISBN: | 3897911922 |
Internformat
MARC
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| 100 | 1 | |a Tafertshofer, Paul |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Test pattern generation and verification for logic circuits |b an implication graph based approach |c Paul Tafertshofer |
| 250 | |a Als Typoskript gedr. | ||
| 264 | 1 | |a München |b Hieronymus |c 2001 | |
| 300 | |a III, 190, XXVI S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 0 | |a Informationstechnik | |
| 502 | |a Zugl.: München, Techn. Univ., Diss., 2001 | ||
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Datensatz im Suchindex
| _version_ | 1804128669972561920 |
|---|---|
| any_adam_object | |
| author | Tafertshofer, Paul |
| author_facet | Tafertshofer, Paul |
| author_role | aut |
| author_sort | Tafertshofer, Paul |
| author_variant | p t pt |
| building | Verbundindex |
| bvnumber | BV013837637 |
| classification_tum | ELT 359d ELT 273d |
| ctrlnum | (OCoLC)76274408 (DE-599)BVBBV013837637 |
| discipline | Elektrotechnik |
| edition | Als Typoskript gedr. |
| format | Thesis Book |
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| genre | (DE-588)4113937-9 Hochschulschrift gnd-content |
| genre_facet | Hochschulschrift |
| id | DE-604.BV013837637 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T18:52:56Z |
| institution | BVB |
| isbn | 3897911922 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-009464654 |
| oclc_num | 76274408 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM DE-12 DE-703 DE-634 |
| owner_facet | DE-91 DE-BY-TUM DE-12 DE-703 DE-634 |
| physical | III, 190, XXVI S. Ill., graph. Darst. |
| publishDate | 2001 |
| publishDateSearch | 2001 |
| publishDateSort | 2001 |
| publisher | Hieronymus |
| record_format | marc |
| series2 | Informationstechnik |
| spelling | Tafertshofer, Paul Verfasser aut Test pattern generation and verification for logic circuits an implication graph based approach Paul Tafertshofer Als Typoskript gedr. München Hieronymus 2001 III, 190, XXVI S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Informationstechnik Zugl.: München, Techn. Univ., Diss., 2001 Digitale integrierte Schaltung (DE-588)4113313-4 gnd rswk-swf Selbsttest (DE-588)4054433-3 gnd rswk-swf Fehlererkennung (DE-588)4133764-5 gnd rswk-swf Algorithmus (DE-588)4001183-5 gnd rswk-swf Testmustergenerierung (DE-588)4234817-1 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Digitale integrierte Schaltung (DE-588)4113313-4 s Testmustergenerierung (DE-588)4234817-1 s Selbsttest (DE-588)4054433-3 s Fehlererkennung (DE-588)4133764-5 s DE-604 Algorithmus (DE-588)4001183-5 s |
| spellingShingle | Tafertshofer, Paul Test pattern generation and verification for logic circuits an implication graph based approach Digitale integrierte Schaltung (DE-588)4113313-4 gnd Selbsttest (DE-588)4054433-3 gnd Fehlererkennung (DE-588)4133764-5 gnd Algorithmus (DE-588)4001183-5 gnd Testmustergenerierung (DE-588)4234817-1 gnd |
| subject_GND | (DE-588)4113313-4 (DE-588)4054433-3 (DE-588)4133764-5 (DE-588)4001183-5 (DE-588)4234817-1 (DE-588)4113937-9 |
| title | Test pattern generation and verification for logic circuits an implication graph based approach |
| title_auth | Test pattern generation and verification for logic circuits an implication graph based approach |
| title_exact_search | Test pattern generation and verification for logic circuits an implication graph based approach |
| title_full | Test pattern generation and verification for logic circuits an implication graph based approach Paul Tafertshofer |
| title_fullStr | Test pattern generation and verification for logic circuits an implication graph based approach Paul Tafertshofer |
| title_full_unstemmed | Test pattern generation and verification for logic circuits an implication graph based approach Paul Tafertshofer |
| title_short | Test pattern generation and verification for logic circuits |
| title_sort | test pattern generation and verification for logic circuits an implication graph based approach |
| title_sub | an implication graph based approach |
| topic | Digitale integrierte Schaltung (DE-588)4113313-4 gnd Selbsttest (DE-588)4054433-3 gnd Fehlererkennung (DE-588)4133764-5 gnd Algorithmus (DE-588)4001183-5 gnd Testmustergenerierung (DE-588)4234817-1 gnd |
| topic_facet | Digitale integrierte Schaltung Selbsttest Fehlererkennung Algorithmus Testmustergenerierung Hochschulschrift |
| work_keys_str_mv | AT tafertshoferpaul testpatterngenerationandverificationforlogiccircuitsanimplicationgraphbasedapproach |