ICCAD-2000: a conference for the EE CAD professional ; November 5 - 9, 2000 Doubletree Hotel, San Jose, CA
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| Format: | Conference Proceeding Book |
| Language: | English |
| Published: |
Piscataway, NJ
IEEE [u.a.]
2000
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| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Physical Description: | XXV, 575 S. graph. Darst. |
| ISBN: | 0780364457 0780364465 0780364473 |
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MARC
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| 111 | 2 | |a International Conference on Computer Aided Design (Institute of Electrical and Electronics Engineers) |d 2000 |c San José, Calif. |j Verfasser |0 (DE-588)10024261-3 |4 aut | |
| 245 | 1 | 0 | |a ICCAD-2000 |b a conference for the EE CAD professional ; November 5 - 9, 2000 Doubletree Hotel, San Jose, CA |c IEEE /ACM International Conference on Computer Aided Design |
| 246 | 1 | 3 | |a IEEE ACM digest of technical papers |
| 246 | 1 | 3 | |a Proceeding of the 2000 International Conference on Computer-Aided Design |
| 264 | 1 | |a Piscataway, NJ |b IEEE [u.a.] |c 2000 | |
| 300 | |a XXV, 575 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 4 | |a Datenverarbeitung | |
| 650 | 4 | |a Computer-aided design |v Congresses | |
| 650 | 4 | |a Electronic circuit design |x Data processing |v Congresses | |
| 650 | 4 | |a Electronic circuits |x Testing |v Congresses | |
| 650 | 0 | 7 | |a CAD |0 (DE-588)4069794-0 |2 gnd |9 rswk-swf |
| 655 | 7 | |0 (DE-588)1071861417 |a Konferenzschrift |y 2000 |z San Jose Calif. |2 gnd-content | |
| 689 | 0 | 0 | |a CAD |0 (DE-588)4069794-0 |D s |
| 689 | 0 | |5 DE-604 | |
| 856 | 4 | 2 | |m Digitalisierung TU Muenchen |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009314916&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-009314916 | |
Record in the Search Index
| _version_ | 1820868237661831168 |
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| adam_text |
Table
of Contents
Foreword
.
iii
Conference Committee
.xiv
Technical Program Committee
.xv
Reviewers
.xvii
LEEE/CAS William J. McCalla ICCAD Best Paper Award
.xx
Keynote
.xxi
Tutorial
1:
Modern Physical Design:
.xxii
Algorithm Technology and Methodology
Tutorial
2:
Interconnect-Centric Design and Analysis for
.xxiii
Electrical Integrity in Systems-on-a-Chip
Tutorial
3:
Symbolic Model Checking:.
.xxiv
Principles and Advanced Techniques
Tutorial
4:
Gain-Based Logic Synthesis
.xxv
Session 1A: Floorplanning and Partitioning
Moderators: Charles J. Alpert, IBM Corporation, Austin,
TX
Carl Sechen,
University of Washington, Seattle, WA
1A.1 Physical Planning with Retiming
.2
Jason Cong, SungKyu
Lim
1A.2 Corner Block List: An Effective and Efficient Topological Representation
. . 8
of Non-Slicing Floorplan
Xianlong Hong, Gang Huang, Yici
Cai,
Jiangchun Gu, Sheqin Dong,
Chung-Kuan Cheng,
Jun Gu
1A3 Modeling Non-Slicing Floorplans with Binary Trees
.13
Florin
Balosa
1A.4 On Mismatches Between Incremental Optimizers and Instance
.17
Perturbations in Physical Design Tools
Andrew B. Kahng,
Stefanus Mantik
IV
SessionlB:
High Level Simulation
Moderators: James H. Kukula, Synopsys, Inc., Beaverton, OR
Vigyan
Singhai, Tempus
Fugit,
Inc., Fremont, CA
1B.1 Event Driven Simulation Without Loops or Conditionals
.23
Peter M.
Maurer
1B.2 Observability Analysis of Embedded Software for Coverage-Directed
.27
Validation
José Costa,
Srinivas Devadas,
José Monteiro
1B.3 A Methodology for Verifying Memory Access Protocols in Behavioral
.33
Synthesis
Gemot
Koch, Taewhan Kim, Reiner Genevriere
Session
1С:
Methods for DSP Synthesis and Debugging
Moderators: Sridevan Parameswaran, University of Queensland, Brisbane, Australia
Kazutoshi Wakabayashi, NEC Corporation, Kawasaki, Japan
ICI
Symbolic Debugging Scheme for Optimized Hardware and Software
.40
Farinaz Koushanfar, Darko
Kirovs/ä, Miodrag
Potkonjak
1C.2 Automated Data Dependency Size Estimation with a Partially Fixed
.44
Execution Ordering
Per
Gunnar
Kjeldsberg,
Francky
Catthoor,
Einar
J.
Aas
1CJ FIR Filter Synthesis Algorithms for Minimizing the Delay and the
.51
Number of Adders
Hyeong-Ju Kang, Hansoo Kim, In-CheolPark
Session ID: Issues in Timing Estimation
Moderators:
Florentin Dortu,
Intel Corporation, Hillsboro, OR
Anirudh Devgan, IBM Corporation, Austin,
TX
1D.1 Effects of Global Interconnect Optimizations on Performance Estimation
. . . 56
of Deep
Submicron
Design
Yu
Cao,
Chenming
Ни,
Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu,
Dirk Stroobandt, Dennis Sylvester
1D.2 Impact of Systematic Spatial Intra-Chip Gate Length friability on
.62
Performance of High-Speed Digital Circuits
Michael Orshansky, Linda
Milor, Pinhong
Chen, Kurt Keutzer,
Chenming
Ни
1D3 Miller Factor for Gate-Level Coupling Delay Calculation
.68
Pinhong Chen, Desmond A. Kirkpatrick, Kurt Keutzer
Session 2A: Embedded Tutorial
Moderator: Ellen M. Sentovich, Cadence Berkeley Labs., Berkeley, CA
2А.1
Challenges
and Opportunities in Broadband and Wireless
.76
Communication Designs
Jan M. Rabaey, Miodrag Potkonjak, Farinaz Koushanfar,
Suet-Fei Li, Tun Tuan
Session 2B: Embedded Tutorial
Moderator: Georges Gielen,
Katholieke
University,
Leuven,
Belgium
2B.1 Challenges in Physical Chip Design
.84
Ralph HJ.M. Otten, Paul Stravers
Session
ЗА:
Topics in Routing
Moderators: John Lillis, University of Illinois, Chicago,
IL
Majid Sarrafzadeh, Northwestern University, Evanston,
IL
ЗАЛ
General Models for Optimum Arbitrary-Dimension FPGA Switch
.93
Box Designs
Hongbing Fan, JipingLiu, Yu-Liang Wu
3A.2 A Timing-constrained Algorithm for Simultaneous Global Routing of
.99
Multiple Nets
Jiang
Hu, Sachin
S.
Sapatnekar
ЗАЗ
Provably
Good
Global
Buffering Using an Available Buffer Block Plan
. 104
FeodorF.
Dragan,
Andrew
В.
Kahng, Ion Mandoiu, Sudhakar Muddu,
Alexander Zelikovsky
3A.4 Predictable Routing
.110
Ryan Kastner,
Elaheh Bozorgzadeh, Majid Sarrafzadeh
Session 3B: Partial Verification Techniques
Moderators: Andreas Kuehlmann, Cadence Berkeley Labs., Berkeley, CA
Yunshan Zhu, Synopsys, Inc., Mountain View, CA
3B.1 Counterexample-Guided Choice of Projections in Approximate Symbolic.
. . 115
Model Checking
Shankar G. Govindaraju, David L. Dill
3B.2 Smart Simulation Using Collaborative Formal and Simulation Engines
. . . 120
Pei-Hsin Ho, Thomas Shiple, Kevin Harer, James Kukula, Robert
Damiano,
Valeria Bertacco, Jerry Taylor, Jiang Long
3B
3
Simulation Coverage Enhancement Using Test Stimulus Transformation.
. . 127
С
Nonislp
Session 3C: Scheduling and Compilation for Embedded Systems
Moderators: Xiaobo (Sharon)
Ни,
University of Notre Dame, Notre Dame, IN
LucianoLavagno,
Universita'
di Udine, Udine,
Italy
VI
3d
Hardware
Compilation
for High-Performance Embedded Systems
.
t
VinodKathail
3C.2 Dynamic Response Time Optimization for SDF Graphs
.135
Dirk Ziegenbein, Jan
Uerpmann, Rolf Ernst
Session
3D:
Inductance and Full-Wave Analysis
Moderators:
Matton
Kamon, Microcosm Technologies, Inc., Cambridge, MA
Mustafa Celik, Monterey Design Systems, Inc., Sunnyvale, CA
3D.1 Full-chip, Three-dimensional, Shapes-based RLC Extraction
.142
K.L. Shepard, D. Sitaram, Yu Zheng
3D.2 How to Efficiently Capture On-Chip Inductance Effects: Introducing
.150
a New Circuit Element
К
Anirudh Devgan, Hao Ji, Wayne Dai
3D.3 Generalized FDTD-ADI: An Unconditionally Stable Full-Wave Maxwell's
. . 156
Equations Solver for VLSI Interconnect Modeling
Charlie C.-P. Chen, Tae-WooLee, Narayanan Murugesan, Susan
С
Hagness
Session 4A: Placement I
Moderators: Patrick Groeneveld, Magma Design Automation, Inc., Cupertino, CA
Hidetoshi Onodera, Kyoto University, Kyoto, Japan
4A.1 Mongrel: Hybrid Techniques for Standard Cell Placement
.165
Sung-Woo
Hur,
John Lillis
4A.2 Multilevel Optimization for Large-Scale Circuit Placement
.171
Tony
E
Chan, Jason Cong, Tianming Kong, Joseph R. Shinnerl
4A-J A Force-Directed Macro-Cell Placer
.177
Fan
Mo, Abdallah
Tabbara, Robert K. Brayton
Session 4B: High-Level Design Tools for Analog Circuits
Moderators: Henry Chang, Cadence Design Systems, Inc., San Jose, CA
Rob A.
Rutenbar,
Carnegie Mellon University, Pittsburgh, PA
4B.1 Verification of
Delta-Sigma
Converters Using Adaptive Regression
.182
Modeling
Jeongjin
Roh, Suresh
Seshadri, Jacob A. Abraham
4B.2 DAISY: A Simulation-Based High-Level Synthesis Tool forAI
.188
Modulators
K.
Francken,
P. Vancorenland, Georges Gielen
4BJ
ACTIF: A
High-Level Power Estimation Tool for Analog
.193
Continuous-Time Filters
Erik Lauwers, Georges Gielen
VII
Session 4C:
Delay Budgeting and Distribution
Moderators: Peter
A. Beerei,
University of Southern California, Los Angeles, CA
Rajeev Murgai, Fujitsu Labs, of America, Inc., Sunnyvale, CA
4C.1 Potential Slack: An Effective Metric of Combinational Circuit
.198
Performance
Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh
4C.2 Delay Budgeting for A Timing-Closure-Driven Design Method
.202
Chien-Chu Kuo, Allen C.-H. Wu
4C3 Stochastic Wire-Length and Delay Distributions of 3-Dimensional
.208
Circuits
Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes
Session 4D: Interconnect Analysis
Moderators: Mustafa
Celile,
Monterey Design Systems, Inc., Sunnyvale, CA
Florentin Dartu,
Intel Corporation,
Hillsboro,
OR
4D.1 Hierarchical Interconnect Circuit Models
.215
Michael
Beatňe,
Satrajit Gupta, Lawrence Pileggi
4D.2 Hurwitz Stable Reduced Order Modeling for RLC Interconnect Trees
.222
XiaodongYang, Chung-Kuan Cheng, WalterH. Ku, RobertJ. Carragher
4D3 An "Effective" Capacitance Based Delay Metric for RC Interconnect
.229
Chandramouli V.Kashyap, Charles J. Alpert, Anirudh Devgan
Session 5A: Embedded Tutorial
Moderator: Georges Gielen,
Katholieke
University,
Leuven,
Belgium
5A.1 Incremental CAD
.236
Olivier Coudert, Jason Cong, Sharad Malik, Majid Sarrafzadeh
Session 5B: Embedded Tutorial
Moderator: Andreas Kuehlmann, Cadence Berkeley Labs., Berkeley, CA
5B.1 Decomposing Refinement Proofs using Assume-Guarantee Reasoning
. 245
Thomas A. Henzinger, Shaz Qadeer, Snram
К
Raj
ämani
Session 6A: Placement II
Moderators: Jason Cong, University of California, Los Angeles, CA
Carl Sechen,
University of Washington, Seattle, WA
6A.1 Effective Partition-Driven Placement with Simultaneous Level Processing
. . 254
and Global Net Views
Ke Zhong, Shantanu Dutt
Vill
6A.2 DRAGON2000:
Standard-Cell Placement Tool for Large Industry Circuits
. . 260
Maogang Wang, Xiaojian Yang, Majid Sarrafzadeh
6A.3 Data Path Placement with Regularity
.264
Terry Tao Ye, Giovanni
De Micheli
Session 6B: Analog and RF Simulation
Moderators:
Koen
Lampaert, Conexant Systems, Inc., Newport Beach, CA
Ramesh Harjani, University of Minnesota, Minneapolis, MN
6B.1 Efficient Finite-Difference Method for Quasi-Periodic Steady-State
.272
and Small Signal Analyses
Baolin Yang, Dan Feng
6B.2 Noise Analysis of Phase-Locked Loops
.277
Amit Mehrotra
6B.3 Computing Phase Noise Eigenfunctions Directly from Steady-State
.283
Jacobian Matrices
Alper
Demir, David Long, Jaijeet Roychowdhury
Session 6C: Markovian Analysis and Asynchronous Circuits
Moderators: Steven M. Nowick, Columbia University, New York, NY
Massoud Pedram, University of Southern California, Los Angeles, CA
6C.1 Modeling and Analysis of Communication Circuit Performance using
. 290
Markov Chains and Efficient Graph Representations
Alper
Demir, Peter
Feldmann
6C.2 Pipeline Optimization for Asynchronous Circuits: Complexity Analysis.
. . . 296
and an Efficient Optimal Algorithm
Sangyun Kim, Peter
A. Beerei
6G3 Achieving Fast and Exact Hazard-Free Logic Minimization of Extended
. . . 303
Burst-Mode gC Finite State Machines
Hans
Jacobson,
Chris Myers, Ganesh Gopalahishnan
Session 6D: Low Power Interconnect Modeling and Optimization
Moderators: Miodrag Potkonjak, University of California, Los Angeles, CA
Kazutoshi Wakabayashi, NEC Corporation, Kawasaki, Japan
6D.1 Bus Optimization for Low-Power Data Path Synthesis Based on Network.
. . 312
Flow Method
Sungpack Hong, TaewhanKim
6D.2 Coupling-Driven Signal Encoding Scheme for Low-Power Interface
.318
Design
Ki-Wook Kim, Kwang-Hyun Baek, Naresh Shanbhag, C.L. Liu, Sung-Mo Kang
6D3 Bus Energy Minimization by Transition Pattern Coding (TPC) in Deep.
. 322
Sub-Micron Technologies
Paul P. Sotiriadis, Anantha
Chandrakasan
їх
Session 7A: Panel
Moderator:
A. Richard
Newton,
University of
California, Berkeley, CA
7A.1
Why Doesn't EDA Get Enough Respect?.
329
Andreas Bechtolsheim, CISCO Systems, Mountain View, CA, Joe
Costello, think3
Inc.,
Santa Clara,
CA, Aart
de
Gues, Synopsys, Inc., Mountain View, CA, Patrick
Scaglia,
Hewlett-Packard Labs., Palo Alto, CA, Jennifer, Myriad Investments, Chestnut Hill, MA
Session 8A: Static Timing Analysis
Moderators:
Sachin
S.
Sapatnekar, University of Minnesota, Minneapolis, MN
Timothy M. Burks, Magma Design Automation, Inc., Cupertino, CA
8A.1 Switching Window Computation for Static Timing Analysis in Presence
. . . 331
of Crosstalk Noise
Pinhong Chen, Desmond A. Kirkpatrick, KurtKeutzer
8A.2 Slope Propagation in Static Timing Analysis
.338
David Blaauw, Vladimir Zolotov, Savithri
Sundareswaran, Chanhee
Oh,
Rajendran Panda
8A.3 Transistor-Level Timing Analysis Using Embedded Simulation
.344
Pawan Kulshreshtha, Robert Palermo, Mohammad Mortazavi, Cyrus Bamji,
.
Hakin Yalcin
Session 8B: Embedded Systems Power Management and Validation
Moderators: Felice
Bakuin,
Cadence Berkeley Labs., Berkeley, CA
Frank Vahid, University of California, Riverside, CA
8B.1 Latency Effects of System Level Power Management Algorithms
.350
Dinesh Ramanathan, Sandy Irani, Rajesh Gupta
8B.2 Power-Conscious Joint Scheduling of Periodic Task Graphs and
.357
Aperiodic Tasks in Distributed
Real-Time
Embedded Systems
Jiong Luo, Niraj K. Jha
8B.3 Power Optimization of Real-Time Embedded Systems on Variable
.365
Speed Processors
Youngsoo Shin, Kiyoung Choi, Takayasu Sakurai
8B.4 A Data Flow Fault Coverage Metric for Validation of Behavioral
.369
HDL Descriptions
Qiushuang Zhang, Ian G. Harris
Session 8C: Advances in Layout and Synthesis
Moderators:
Hamid
Savoj, Magma Design Automation, Inc., Cupertino, CA
Makoto Ikeda, University of Tokyo, Tokyo, Japan
8C.1 Simultaneous Gate Sizing and Fanout Optimization
.374
Wei Chen, Cheng-Ta Hsieh, Massoud Pedram
8C.2 Layout-driven Area-constrained Timing Optimization by Net Buffering
. . . 379
Rajeev Murgai
8C.3
Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation
.387
Ching-Hwa Cheng, Shih-Chieh Chang, Shin
De
Li, Wen-Ben
Jone,
Jinn-Shyan Wang
Session 8D: Embedded Tutorial
Moderator: Rolf Ernst, Technical University Braunschweig, Braunschweig, Germany
8D.1 Test of Future System-on-Chips
.392
Yervant Zorian, SujitDey, Michael
J
. Rodgers
Session 9A: Noise and Performance Issues in Routing
Moderators:
Tong
Gao,
Monterey Design Systems, Sunnyvale, CA
Margaret Marek-Sadowska, University of California, Santa Barbara, CA
9A.1 UST/DME: A Clock Tree Router For General Skew Constraints
.400
Chung-Wen Albert Tsao, Cheng-KokKoh
9A.2 A Twisted-Bundle Layout Structure for Minimizing Inductive
.406
Coupling Noise
Guoan Zhong, Cheng
-Кок
Koh, Kaushik Roy
9A.3 Cross-talk Immune VLSI Design using a Network of PLAs Embedded in a
. . 412
Regular Layout Fabric
Sunil P. Khatri, Robert K. Brayton, Alberto Sangiovanni-Vincentelli
Session 9B: Communication Architectures Design and Analysis
Moderators:
Diederik Verkest, IMEC,
Leuven,
Belgium
Preeti Ranjan Panda, Synopsys, Inc., Mountain View, CA
9B.1 Latency-Guided On-Chip Bus Network Design.
.420
Milenko
Drinic, Darko Kirovski, Seapahn Mequerdichian, Miodrag Potkonjak
9B.2 Efficient Exploration of the SoC Communication Architecture
.424
Design Space
Kanishka Lahiri, Anand Raghunathan, Sujit
Dey
9B.3 MIST: An Algorithm for Memory Miss Traffic Management
.431
Peter
Grün, Nikü Dutt, Alex Nicolau
Session 9C: Performance
Driven
Logic
Synthesis
Moderators: Shih-Chieh
Chang,
National
Chung-Cheng University,
Taiwan
ROC
Masahiro Fujita,
University of
Tokyo, Tokyo, Japan
9C.1
Regularity Driven
Logic
Synthesis.
439
Thomas Kutzschebauch, Leon
Stok
9C.2
Timing Driven Gate Duplication: Complexity Issues and Algorithms
.447
Ankur Srivastava, Ryan Kastner, Majid
Sarrafzadeh
xi
9C.3
An Exact
Gate Assignment Algorithm for Tree
Circuits
Under Rise
.451
and Fall Delays
Arlindo L.
Oliveira, Rajeev
Murgai
Session 9D: New Approaches to At-Speed BIST and Diagnosis
Moderators: Yervant Zorian, LogicVision, Inc., San Jose, CA
Sujit
Dey,
University of California at San Diego, La
Joüa,
С А
9D.1 Improving the Proportion of At-Speed Tests in Scan BIST
.459
Y. Huang, I. Pomeranz, S.M. Ready, J.
Rajski
9D.2 Fast Test Application Technique Without Fast Scan Clocks
.464
Seonki Kim, Bapiraju Vmnakota
9Đ3
Error Catch and Analysis for Semiconductor Memories Using March
lests
. 468
Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng,
Cheng-Wen Wu
9D.4 Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures.
. . . 472
Ian G. Harris, Russell Tessier
Session 10A: Power Analysis and Optimization
Moderators: Dennis Sylvester, University of Michigan, Ann Arbor, MI
Anirudh Devgan, IBM Corporation, Austin,
TX
10A.1 Fast Analysis and Optimization of Power/Ground Networks
.477
Haihua
Su,
Kaushik H. Gala,
Sachin
S.
Sapatnekar
10A.2 Simulation and Optimization of the Power Distribution Network in
.481
VLSI Circuits
G. Bai, S.
Bobba,
IN. Hajj
10A3 Frequency Domain Analysis of Switching Noise on Power Supply Network
. . 487
Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
10A.4 Path Selection and Pattern Generation for Dynamic liming Analysis
.493
Considering Power Supply Noise Effects
Jing-Jia
Liou,
Angela
Krstić,
Yi-Min Jiang, Kwang-Ting Cheng
Session 10B: VLIW Exploration and Design Synthesis
Moderators: Santanu Dutta, Phillips, Sunnyvale, CA
Ali
Dasdan,
Synopsys, Inc., Mountain View, CA
10B.1 Power Exploration for Embedded VLIW Architectures
.498
Mariagiovanna
Sami,
Donatella Sciuto,
Cristina
Silvano, Vittorio
Zacearía
10B.2
Exploring
Performance
Tradeoffs for Clustered VLIW ASIPs
.504
Margarida
F.
Jacome, Gustavo
de
Veciana, Victor Lapinskii
10B-3 Synthesis of Operation-Centric Hardware Descriptions.
.511
James C. Hoe, Arvind
xu
Session IOC:
Flexibility in
Logic
Synthesis
Moderators: Yuji Kukimoto,
Monterey
Design Systems,
Inc., Sunnyvale,
СА
Tiziano
VUL·, Parades,
Roma,
Italy
ЮСІ
Don't Cares and Multi-Valued Logic Network Minimization
.520
Yunjian Jiang, Robert K. Bray ton
10C.2 Generalized Symmetries in Boolean functions
.526
Victor
N.
Kravets,
Karem
A. Sakallah
10C.3 Wire Reconnections Based on Implication Flow Graph
.533
Shih-Chieh Chang, Zhong-Zhen Wu, He-Zhe Yu
Session 10D: Digital and Analog Test Generation
Moderators: Bapiraju Vinnakota, Univ, of Minnesota, Minneapolis, MN
Seiji Kajihara, Kyushu Institute of Technology, Iizuka, Japan
10D.1 Deterministic Test Pattern Generation Techniques for Sequential Circuits
. . 538
Ilker Hamzaoglu, JanakH.
Patel
10D.2 Simulation Based Test Generation for Scan Designs
.544
Irith Pomeranz, SudhakarM. Reddy
10D.3 Test Generation for Acyclic Sequential Circuits with Hold Registers
.550
Tomoo Inoue, Debesh Kumar Das, Chiiho
Sano, Takahiro
Mihara,
Hideo Fujiwara
10D.4 A Parametric Test Method for Analog Components in Integrated
.557
Mixed-Signal Circuits
M. Pronath, VGloeckel, H. Graeb
10D.5 Partial Simulation-Driven ATPG for Detection and Diagnosis of
.562
Faults in Analog Circuits
Sudip Chakrabarti, Abhijit Chatterjee
Session
11
A: Embedded Tutorial
Moderator:
Francky
Catthoor, IMEC,
Leuven,
Belgium
НАЛ
System and Architecture-Level Power Reduction for
.569
Microprocessor-Based Communication and Multi-Media Applications
Lode Nachtergaele, Vivek Tiwari, Nikil Dutt
Session 11B: Embedded Tutorial
Moderator: Lawrence T. Pileggi, Carnegie Mellon University, Pittsburgh, PA
11B.1 Design-Manufacturing Interface for
0.13
Micron and Below
.575
Andrzej
J. Strojwas
t
-
Manuscript unavailable for publication
Xlii |
| any_adam_object | 1 |
| author_corporate | International Conference on Computer Aided Design (Institute of Electrical and Electronics Engineers) San José, Calif |
| author_corporate_role | aut |
| author_facet | International Conference on Computer Aided Design (Institute of Electrical and Electronics Engineers) San José, Calif |
| author_sort | International Conference on Computer Aided Design (Institute of Electrical and Electronics Engineers) San José, Calif |
| building | Verbundindex |
| bvnumber | BV013634090 |
| callnumber-first | T - Technology |
| callnumber-label | TK7874 |
| callnumber-raw | TK7874 |
| callnumber-search | TK7874 |
| callnumber-sort | TK 47874 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | SS 2000 |
| classification_tum | DAT 810f |
| ctrlnum | (OCoLC)45699678 (DE-599)BVBBV013634090 |
| discipline | Informatik |
| format | Conference Proceeding Book |
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| genre | (DE-588)1071861417 Konferenzschrift 2000 San Jose Calif. gnd-content |
| genre_facet | Konferenzschrift 2000 San Jose Calif. |
| id | DE-604.BV013634090 |
| illustrated | Illustrated |
| indexdate | 2025-01-10T13:21:11Z |
| institution | BVB |
| institution_GND | (DE-588)10024261-3 |
| isbn | 0780364457 0780364465 0780364473 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-009314916 |
| oclc_num | 45699678 |
| open_access_boolean | |
| owner | DE-739 DE-91G DE-BY-TUM DE-20 DE-706 |
| owner_facet | DE-739 DE-91G DE-BY-TUM DE-20 DE-706 |
| physical | XXV, 575 S. graph. Darst. |
| publishDate | 2000 |
| publishDateSearch | 2000 |
| publishDateSort | 2000 |
| publisher | IEEE [u.a.] |
| record_format | marc |
| spelling | International Conference on Computer Aided Design (Institute of Electrical and Electronics Engineers) 2000 San José, Calif. Verfasser (DE-588)10024261-3 aut ICCAD-2000 a conference for the EE CAD professional ; November 5 - 9, 2000 Doubletree Hotel, San Jose, CA IEEE /ACM International Conference on Computer Aided Design IEEE ACM digest of technical papers Proceeding of the 2000 International Conference on Computer-Aided Design Piscataway, NJ IEEE [u.a.] 2000 XXV, 575 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Datenverarbeitung Computer-aided design Congresses Electronic circuit design Data processing Congresses Electronic circuits Testing Congresses CAD (DE-588)4069794-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 2000 San Jose Calif. gnd-content CAD (DE-588)4069794-0 s DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009314916&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | ICCAD-2000 a conference for the EE CAD professional ; November 5 - 9, 2000 Doubletree Hotel, San Jose, CA Datenverarbeitung Computer-aided design Congresses Electronic circuit design Data processing Congresses Electronic circuits Testing Congresses CAD (DE-588)4069794-0 gnd |
| subject_GND | (DE-588)4069794-0 (DE-588)1071861417 |
| title | ICCAD-2000 a conference for the EE CAD professional ; November 5 - 9, 2000 Doubletree Hotel, San Jose, CA |
| title_alt | IEEE ACM digest of technical papers Proceeding of the 2000 International Conference on Computer-Aided Design |
| title_auth | ICCAD-2000 a conference for the EE CAD professional ; November 5 - 9, 2000 Doubletree Hotel, San Jose, CA |
| title_exact_search | ICCAD-2000 a conference for the EE CAD professional ; November 5 - 9, 2000 Doubletree Hotel, San Jose, CA |
| title_full | ICCAD-2000 a conference for the EE CAD professional ; November 5 - 9, 2000 Doubletree Hotel, San Jose, CA IEEE /ACM International Conference on Computer Aided Design |
| title_fullStr | ICCAD-2000 a conference for the EE CAD professional ; November 5 - 9, 2000 Doubletree Hotel, San Jose, CA IEEE /ACM International Conference on Computer Aided Design |
| title_full_unstemmed | ICCAD-2000 a conference for the EE CAD professional ; November 5 - 9, 2000 Doubletree Hotel, San Jose, CA IEEE /ACM International Conference on Computer Aided Design |
| title_short | ICCAD-2000 |
| title_sort | iccad 2000 a conference for the ee cad professional november 5 9 2000 doubletree hotel san jose ca |
| title_sub | a conference for the EE CAD professional ; November 5 - 9, 2000 Doubletree Hotel, San Jose, CA |
| topic | Datenverarbeitung Computer-aided design Congresses Electronic circuit design Data processing Congresses Electronic circuits Testing Congresses CAD (DE-588)4069794-0 gnd |
| topic_facet | Datenverarbeitung Computer-aided design Congresses Electronic circuit design Data processing Congresses Electronic circuits Testing Congresses CAD Konferenzschrift 2000 San Jose Calif. |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009314916&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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