Field programmable logic and applications: the roadmap to reconfigurable computing ; 10th international conference, FPL 2000, Villach, Austria, August 27 - 31, 2000 ; proceedings
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| Format: | Conference Proceeding Book |
|---|---|
| Language: | English |
| Published: |
Berlin ; Heidelberg ; New York ; Barcelona ; Hong Kong ; London
Springer
2000
|
| Series: | Lecture notes in computer science
1896 |
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Physical Description: | XV, 856 S. Ill., graph. Darst. |
| ISBN: | 3540678999 |
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| 245 | 1 | 0 | |a Field programmable logic and applications |b the roadmap to reconfigurable computing ; 10th international conference, FPL 2000, Villach, Austria, August 27 - 31, 2000 ; proceedings |c Reiner W. Hartenstein ; Herbert Grünbacher (ed.) |
| 264 | 1 | |a Berlin ; Heidelberg ; New York ; Barcelona ; Hong Kong ; London |b Springer |c 2000 | |
| 300 | |a XV, 856 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Lecture notes in computer science |v 1896 | |
| 650 | 0 | 7 | |a Field programmable gate array |0 (DE-588)4347749-5 |2 gnd |9 rswk-swf |
| 655 | 7 | |0 (DE-588)1071861417 |a Konferenzschrift |y 2000 |z Villach |2 gnd-content | |
| 689 | 0 | 0 | |a Field programmable gate array |0 (DE-588)4347749-5 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Hartenstein, Reiner W. |d 1934-2022 |e Sonstige |0 (DE-588)109112660 |4 oth | |
| 711 | 2 | |a FPL |n 10 |d 2000 |c Villach |j Sonstige |0 (DE-588)10006698-7 |4 oth | |
| 830 | 0 | |a Lecture notes in computer science |v 1896 |w (DE-604)BV000000607 |9 1896 | |
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| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-009074412 | |
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| _version_ | 1820874893605994496 |
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TABLE
OF
CONTENTS
INVITED
KEYNOTE
THE
RISING
WAVE
OF
FIELD
PROGRAMMABILITY
.
1
MAKIMOTO,
T.
TIGHTLY
INTEGRATED
DESIGN
SPACE
EXPLORATION
WITH
SPATIAL
AND
TEMPORAL
PARTITIONING
IN
SPARCS
.
7
GOVINDARAJAN,
S.;
VEMURI,
R.
NETWORK
PROCESSORS
A
DYNAMICALLY
RECONFIGURABLE
FPGA-BASED
CONTENT
ADDRESSABLE
MEMORY
FOR
INTERNET
PROTOCOL
CHARACTERIZATION
.
19
DITMAR,
J.;
TORKELSSON,
K;
JANTSCH,
A.
A
COMPILER
DIRECTED
APPROACH
TO
HIDING
CONFIGURATION
LATENCY
IN
CHAMELEON
PROCESSORS
.
29
TANG,
X.;
AALSMA,
M.;
JOU,
R.
RECONFIGURABLE
NETWORK
PROCESSORS
BASED
ON
FIELD
PROGRAMMABLE
SYSTEM
LEVEL
INTEGRATED
CIRCUITS
.
39
ILIOPOULOS,
M.;
ANTONAKOPOULOS,
T.
INTERNET
CONNECTED
FPL
.
48
FALLSIDE,
H.;
SMITH,
M.J.S.
PROTOTYPING
FIELD
PROGRAMMABLE
COMMUNICATION
EMULATION
AND
OPTIMIZATION
FOR
EMBEDDED
SYSTEM
DESIGN
.
58
RENNER,
F.-M.;
BECKER,
J.;
GLESNER,
M.
FPGA-BASED
EMULATION:
INDUSTRIAL
AND
CUSTOM
PROTOTYPING
SOLUTIONS
.
68
KRUPNOVA,
H.;
SAUCIER,
G.
FPGA-BASED
PROTOTYPING
FOR
PRODUCT
DEFINITION
.
78
KRESS,
R.;
PYTTEL,
A.;
SEDLMEIER,
A.
IMPLEMENTATION
OF
VIRTUAL
CIRCUITS
BY
MEANS
OF
THE
FIPSOC
DEVICES
.
87
CANTO,
E.;
MORENO,
J.M.;
CABESTANY,
J.;
LACADENA,
I.;
INSENSER,
J.M.
DYNAMICALLY
RECONFIGURABLE
I
STATIC
AND
DYNAMIC
RECONFIGURABLE
DESIGNS
FOR
A
2D
SHAPE-ADAPTIVE
DCT
.
96
GAUSE,
J.;
CHEUNG,
P.Y.K.;
LUK,
W.
A
SELF-RECONFIGURABLE
GATE
ARRAY
ARCHITECTURE
.
106
SIDHU,
R.;
WADHWA,
S.;
MEI,
A.;
PRASANNA,
V.K.
MULTITASKING
ON
FPGA
COPROCESSORS
.
121
SIMMLER,
H.;
LEVINSON,
L;
MANNER,
R.
XII
TABLE
OF
CONTENTS
DESIGN
VISUALISATION
FOR
DYNAMICALLY
RECONFIGURABLE
SYSTEMS
.
131
VASILKO,
M.
VERIFICATION
OF
DYNAMICALLY
RECONFIGURABLE
LOGIC
.
141
ROBINSON,
D.
;
LYSAGHT,
P.
MISCELLANEOUS
I
DESIGN
OF
A
FAULT
TOLERANT
FPGA
.
151
BARTZICK,
T.;
HENZE,
M.;
KICKLER,
J.;
WOSKA,
K.
REAL-TIME
FACE
DETECTION
ON
A
CONFIGURABLE
HARDWARE
SYSTEM
.
157
MCCREADY,
R.
MULTIFUNCTIONAL
PROGRAMMABLE
SINGLE-BOARD
CAN
MONITORING
MODULE
.
163
PFEIFER,
P.
SELF-TESTING
OF
LINEAR
SEGMENTS
IN
USER-PROGRAMMED
FPGAS
.
169
TOMASZEWICZ,
P.
IMPLEMENTING
A
FIELDBUS
INTERFACE
USING
AN
FPGA
.
175
LIAS,
G.;
VALDES,
M.D.;
DOMINGUEZ,
M.A.;
MOURE,
M.J.
TECHNOLOGY
MAPPING
AND
ROUTING
&
PLACEMENT
AREA-OPTIMIZED
TECHNOLOGY
MAPPING
FOR
HYBRID
FPGAS
.
181
KRISHNAMOORTHY,
S.;
SWAMINATHAN,
S.;
TESSIER,
R.
COMGEN:
DIRECT
MAPPING
OF
ARBITRARY
COMPONENTS
INTO
LUT-BASED
FPGAS
.
191
ABKE,
J.;
BARKE,
E.
EFFICIENT
EMBEDDING
OF
PARTITIONED
CIRCUITS
ONTO
MULTI-FPGA
BOARDS
.
201
CHANDRA
JAIN,
S.;
KUMAR,
A.;
KUMAR,
S.
A
PLACEMENT
ALGORITHM
FOR
FPGA
DESIGNS
WITH
MULTIPLE
I/O
STANDARDS
.
211
ANDERSON,
J.;
SAUNDERS,
J.;
NAG,
S.;
MADABHUSHI,
C.;
JAYARAMAN,
R.
A
MAPPING
METHODOLOGY
FOR
CODE
TREES
ONTO
LUT-BASED
FPGAS
.
221
KROPP,
H.;
REUTER,
C.
BIOLOGICALLY
INSPIRED
METHODS
POSSIBILITIES
AND
LIMITATIONS
OF
APPLYING
EVOLVABLE
HARDWARE
TO
REAL-WORLD
APPLICATIONS
.
230
TORRESEN,
J.
A
CO-PROCESSOR
SYSTEM
WITH
A
VIRTEX
FPGA
FOR
EVOLUTIONARY
COMPUTATION
.
240
YAMAGUCHI,
Y.;
MIYASHITA,
A.;
MARUYAMA,
T.;
HOSHINO,
T.
SYSTEM
DESIGN
WITH
GENETIC
ALGORITHMS
.
250
BAUER,
C.;
ZIPF,
P.;
WOJTKOWIAK,
H.
IMPLEMENTING
KAK
NEURAL
NETWORKS
ON
A
RECONFIGURABLE
COMPUTING
PLATFORM
.
260
ZHU,
J.;
MILNE,
G.
COMPACT
SPIKING
NEURAL
NETWORK
IMPLEMENTATION
IN
FPGA
.
270
MAYA,
S.;
REYNOSO,
R.;
TORRES,
C.;
ARIAS-ESTRADA,
M.
TABLE
OF
CONTENTS
XIII
INVITED
KEYNOTE
SILICON
PLATFORMS
FOR
THE
NEXT
GENERATION
WIRELESS
SYSTEMS
-
WHAT
ROLE
DOES
RECONFIGURABLE
HARDWARE
PLAY?
.
277
RABAEY,
J.M.
INVITED
PAPERS
FROM
RECONFIGURABILITY
TO
EVOLUTION
IN
CONSTRUCTION
SYSTEMS:
SPANNING
THE
ELECTRONIC,
MICROFLUIDIC
AND
BIOMOLECULAR
DOMAINS
.
286
MCCASKILL,
J.S.;
WAGLER,
P.
A
SPECIFIC
TEST
METHODOLOGY
FOR
SYMMETRIC
SRAM-BASED
FPGAS
.
300
RENOVELL,
M.
MOBILE
COMMUNICATION
DREAM:
A
DYNAMICALLY
RECONFIGURABLE
ARCHITECTURE
FOR
FUTURE
MOBILE
COMMUNICATION
APPLICATIONS
.
312
BECKER,
J.;
PIONTECK,
T.;
GLESNER,
M.
FAST
CARRIER
AND
PHASE
SYNCHRONIZATION
UNITS
FOR
DIGITAL
RECEIVERS
BASED
ON
RE-CONFIGURABLE
LOGIC
.
322
BLAICKNER,
A.;
NAGY,
O.;
GRIINBACHER,
H.
SOFTWARE
RADIO
RECONFIGURABLE
HARDWARE
SYSTEM
(SHARE)
.
332
REVES,
X.;
GELONCH,
A.;
CASADEVALL,
F.;
GARCIA,
J.L.
ANALYSIS
OF
RNS-FPL
SYNERGY
FOR
HIGH
THROUGHPUT
DSP
APPLICATIONS:
DISCRETE
WAVELET
TRANSFORM
.
342
RAMIREZ,
J.;
GARCIA,
A.;
FERNANDEZ,
P.G.;
PARILLA,
L;
LLORIS,
A.
DYNAMICALLY
RECONFIGURABLE
II
PARTIAL
RUN-TIME
RECONFIGURATION
USING
JRTR
.
352
MCMILLAN,
S.;
GUCCIONE,
S.A.
A
COMBINED
APPROACH
TO
HIGH-LEVEL
SYNTHESIS
FOR
DYNAMICALLY
RECONFIGURABLE
SYSTEMS
.
361
ZHANG,
X.-J.;
NG,
K.-W.;
LUK,
W.
A
HYBRID
PROTOTYPING
PLATFORM
FOR
DYNAMICALLY
RECONFIGURABLE
DESIGNS
.
371
RISSA,
T.;
NIITTYLAHTI,
J.
TASK
REARRANGEMENT
ON
PARTIALLY
RECONFIGURABLE
FPGAS
WITH
RESTRICTED
BUFFER
.
379
ELGINDY,
H.;
MIDDENDORF,
M.;
SCHMECK,
H.;
SCHMIDT,
B.
DESIGN
SPACE
EXPLORATION
GENERATION
OF
DESIGN
SUGGESTIONS
FOR
COARSE-GRAIN
RECONFIGURABLE
ARCHITECTURES
.
389
HARTENSTEIN,
R.;
HERZ,
M.;
HOFFMANN,
TH.;
NAGELDINGER,
U.
MAPPING
OF
DSP
ALGORITHMS
ON
FIELD
PROGRAMMABLE
FUNCTION
ARRAYS
.
400
HEYSTERS,
P.M.;
SMIT,
J.;
SMIT,
G.J.M.;
HAVINGA,
P.J.M.
ON
AVAILABILITY
OF
BIT-NARROW
OPERATIONS
IN
GENERAL-PURPOSE
APPLICATIONS
.
412
STEFANOVII,
D.;
MARTONOSI,
M.
XIV
TABLE
OF
CONTENTS
A
COMPARISON
OF
FPGA
IMPLEMENTATIONS
OF
BIT-LEVEL
AND
WORD-LEVEL
MATRIX
MULTIPLIERS
.
422
GROVER,
R.S.;
SHANG,
W.;
LI,
Q.
A
NEW
FLOORPLANNING
METHOD
FOR
FPGA
ARCHITECTURAL
RESEARCH
.
432
WOLZ,
F;
KOLLA,
R.
MISCELLANEOUS
II
EFFICIENT
SELF-RECONFIGURABLE
IMPLEMENTATIONS
USING
ON-CHIP
MEMORY
.
443
WADHWA,
S.;
DANDALIS,
A.
DESIGN
AND
IMPLEMENTATION
OF
AN
XC6216
FPGA
MODEL
IN
VERILOG
.
449
GLASMACHER,
A.;
WOSKA,
K.
REUSABLE
DSP
FUNCTIONS
IN
FPGA'S
.
456
ANDREJAS,
J.;
TROST,
A.
A
PARALLEL
PIPELINED
SAT
SOLVER
FOR
FPGAS
.
462
REDEKOPP,
M.;
DANDALIS,
A.
A
MULTI-NODE
DYNAMIC
RECONFIGURABLE
COMPUTING
SYSTEM
WITH
DISTRIBUTED
RECONFIGURATION
CONTROLLER
.
469
TOUHAFI,
A.
APPLICATIONS
I
A
RECONFIGURABLE
STOCHASTIC
MODEL
SIMULATOR
FOR
ANALYSIS
OF
PARALLEL
SYSTEMS
.
475
YAMAMOTO,
O.;
SHIBATA,
Y.;
KUROSAWA,
H.;
AMANO,
H.
A
CORDIC
ARCTANGENT
FPGA
IMPLEMENTATION
FOR
A
HIGH-SPEED
3D-CAMERA
SYSTEM
.
485
BELLIS,
S.J.;
MAMANE,
W.P.
RECONFIGURABLE
COMPUTING
FOR
SPEECH
RECOGNITION:
PRELIMINARY
FINDINGS
.
495
MELNIKOFF,
S.J.;
JAMES-ROXBY,
P.B.;
QUIGLEY,
S.F.;
RUSSELL,
M.J.
SECURITY
UPGRADE
OF
EXISTING
ISDN
DEVICES
BY
USING
RECONFIGURABLE
LOGIC
.
505
PLOOG,
H.;
SCHMALISCH,
M.;
TIMMERMANN,
D.
THE
FASTEST
MULTIPLIER
ON
FPGAS
WITH
REDUNDANT
BINARY
REPRESENTATION
.
515
MIOMO,
T.;
YASUOKA,
K.;
KANAZAWA,
M.
OPTIMIZATION
HIGH-LEVEL
AREA
AND
PERFORMANCE
ESTIMATION
OF
HARDWARE
BUILDING
BLOCKS
ON
FPGAS
.
525
ENZLER,
R.;
JEGER,
T.;
COTTET,
D.;
TRBSTER,
G.
BALANCING
LOGIC
UTILIZATION
AND
AREA
EFFICIENCY
IN
FPGAS
.
535
TESSIER,
R.;
GIZA,
H.
PERFORMANCE
PENALTY
FOR
FAULT
TOLERANCE
IN
ROVING
STARS
.
545
EMMERT,
J.M.;
STROUD,
C.E.;
CHEATHAM,
J.;
TAYLOR,
A.M.;
KATARIA,
P.;
ABRAMOVICI,
M.
TABLE
OF
CONTENTS
XV
OPTIMUM
FUNCTIONAL
DECOMPOSITION
FOR
LUT-BASED
FPGA
SYNTHESIS
.
555
QIAO,
J.;
IKEDA,
M.;
ASADA,
K.
OPTIMIZATION
OF
RUN-TIME
RECONFIGURABLE
EMBEDDED
SYSTEMS
.
565
EISENRING,
M.;
PLATZNER,
M.
INVITED
KEYNOTE
IT
'
S
FPL,
JIM
-
BUT
NOT
AS
WE
KNOW
IT!
OPPORTUNITIES
FOR
THE
NEW
COMMERCIAL
ARCHITECTURES
.
575
KEAN,
T.
INVITED
PAPER
RECONFIGURABLE
SYSTEMS:
NEW
ACTIVITIES
IN
ASIA
.
585
AMANO,
H.;
SHIBATA,
Y.;
UNO,
M.
STREAM:
OBJECT-ORIENTED
PROGRAMMING
OF
STREAM
ARCHITECTURES
USING
PAM-BLOX
.
595
MENCER,
O.;
HUBERT,
H.;
MORF,
M.;
FLYNN,
M.J.
ARCHITECTURES
STREAM
COMPUTATIONS
ORGANIZED
FOR
RECONFIGURABLE
EXECUTION
(SCORE)
.
605
CASPI,
E.;
CHU,
M.;
HUANG,
R.;
YEH,
J.;
WAWRZYNEK,
J.;
DEHON,
A.
MEMORY
ACCESS
SCHEMES
FOR
CONFIGURABLE
PROCESSORS
.
615
LANGE,
H.;
KOCH,
A.
GENERATING
ADDRESSES
FOR
MULTI-DIMENSIONAL
ARRAY
ACCESS
IN
FPGA
ON-CHIP
MEMORY
.
626
DARING,
A.C.;
LUSTIG,
G.
COMBINING
SERIALISATION
AND
RECONFIGURATION
FOR
FPGA
DESIGNS
.
636
DERBYSHIRE,
A.;
LUK,
W.
METHODOLOGY
AND
TECHNOLOGY
MULTIPLE-WORDLENGTH
RESOURCE
BINDING
.
646
CONSTANTINIDES,
G.A.;
CHEUNG,
P.Y.K.;
LUK,
W.
AUTOMATIC
TEMPORAL
FLOORPLANNING
WITH
GUARANTEED
SOLUTION
FEASIBILITY
.
656
VASILKO,
M.;
BENYON-TINKER,
G.
A
THRESHOLD
LOGIC-BASED
RECONFIGURABLE
LOGIC
ELEMENT
WITH
A
NEW
PROGRAMMING
TECHNOLOGY
.
665
AOYAMA,
K;
SAWADA,
H.;
NAGOYA,
A.;
NAKAJIMA,
K.
EXPLOITING
RECONFIGURABILITY
FOR
EFFECTIVE
DETECTION
OF
DELAY
FAULTS
IN
LUT-BASED
FPGAS
.
675
KRASNIEWSKI,
A.
COMPILATION
AND
RELATED
ISSUES
DATAFLOW
PARTITIONING
AND
SCHEDULING
ALGORITHMS
FOR
WASMII,
A
VIRTUAL
HARDWARE
.
685
TAKAYAMA,
A.;
SHIBATA,
Y.;
IWAI,
K;
AMANO,
H.
XVI
TABLE
OF
CONTENTS
COMPILING
APPLICATIONS
FOR
CONCISE:
AN
EXAMPLE
OF
AUTOMATIC
HW/SW
PARTITIONING
AND
SYNTHESIS
.
695
KASTRUP,
B.;
TRUM,
J.;
MOREIRA,
0.;
HOOGERBRUGGE,
J.;
VAN
MEERBERGEN,
J.
BEHAVIOURAL
LANGUAGE
COMPILATION
WITH
VIRTUAL
HARDWARE
MANAGEMENT
.
707
DIESSEL,
O.;
MILNE,
G.
SYNTHESIS
AND
IMPLEMENTATION
OF
RAM-BASED
FINITE
STATE
MACHINES
IN
FPGAS
.
718
SKLYAROV,
V.
APPLICATIONS
II
EVALUATION
OF
ACCELERATOR
DESIGNS
FOR
SUBGRAPH
ISOMORPHISM
PROBLEM
.
729
ICHIKAWA,
S.;
SAITO,
H.;
UDORN,
L;
KONISHI,
K.
THE
IMPLEMENTATION
OF
SYNCHRONOUS
DATAFLOW
GRAPHS
USING
RECONFIGURABLE
HARDWARE
.
739
EDWARDS,
M.;
GREEN,
P.
MULTIPLEXER
BASED
RECONFIGURATION
FOR
VIRTEX
MULTIPLIERS
.
749
COURTNEY,
T.;
TURNER,
R.;
WOODS,
R.
EFFICIENT
BUILDING
OF
WORD
RECOGNIZER
IN
FPGAS
FOR
TERM-DOCUMENT
MATRICES
CONSTRUCTION
.
759
BOBDA,
C.;
LEHTNANN,
T.
SHORT
PAPERS
RECONFIGURABLE
COMPUTING
BETWEEN
CLASSIFICATIONS
AND
METRICS
-
THE
APPROACH
OF
SPACE/TIME-SCHEDULING
.
769
SIEMERS,
C.
FPGA
IMPLEMENTATION
OF
A
PROTOTYPE
WDM
ON-LINE
SCHEDULER
.
773
CHENG,
W.W.;
WILTON,
S.J.E.;
HAMIDZADEH,
B.
AN
FPGA
BASED
SCHEDULING
COPROCESSOR
FOR
DYNAMIC
PRIORITY
SCHEDULING
IN
HARD-TIME
SYSTEMS
.
777
HILDEBRANDT,
J.;
TIMMERMANN,
D.
FORMAL
VERIFICATION
OF
A
RECONFIGURABLE
MICROPROCESSOR
.
781
SAWITZKI,
S.;
SCHBNHERR,
J.;
SPALLEK,
R.G.;
STRAUBE,
B.
THE
ROLE
OF
THE
EMBEDDED
MEMORIES
IN
THE
IMPLEMENTATION
OF
ARTIFICIAL
NEURAL
NETWORKS
.
785
GADEA,
R.;
HERRERO,
V.;
SEBASTIA,
A.;
MOCHOLI,
A.
PROGRAMMABLE
SYSTEM
LEVEL
INTEGRATION
BRINGS
SYSTEM-ON-CHIP
DESIGN
TO
THE
DESKTOP
.
789
LAFAYETTE,
G.L
ON
APPLYING
SOFTWARE
DEVELOPMENT
BEST
PRACTICE
TO
FPGAS
IN
SAFETY-CRITICAL
SYSTEMS
.
793
HILTON,
A.;
HALL,
J.
PRE-ROUTE
ASSISTANT:
A
ROUTING
TOOL
FOR
RUN-TIME
RECONFIGURATION
.
797
BLODGET,
B.
HIGH
SPEED
COMPUTATION
OF
LATTICE
GAS
AUTOMATA
WITH
FPGA
.
801
KOBORI,
T.;
MARUYAMA,
T.;
HOSHINO,
T.
TABLE
OF
CONTENTS
XVII
AN
IMPLEMENTATION
OF
LONGEST
PREFIX
MATCHING
FOR
IP
ROUTER
ON
PLASTIC
CELL
ARCHITECTURE
.
805
SHIOZAWA,
T.;
IMLIG,
N.;
NAGAMI,
K.;
OGURI,
K.;
NAGOYA,
A.;
NAKADA,
H.
FPGA
IMPLEMENTATION
OF
AN
EXTENDED
BINARY
GCD
ALGORITHM
FOR
SYSTOLIC
REDUCTION
OF
RATIONAL
NUMBERS
.
810
A/UTDSARU,
B.;
JEBELEAN,
T.
TOWARD
UNIFORM
APPROACH
TO
DESIGN
OF
EVOLVABLE
HARDWARE
BASED
SYSTEMS
.
814
SEKANINA,
L.;
SLLAME,
A.M.
EDUCATIONAL
PROGRAMMABLE
HARDWARE
PROTOTYPING
AND
VERIFICATION
SYSTEM
.
818
TROST,
A.;
ZEMVA,
A.;
ZAJC,
B.
A
STREAM
PROCESSOR
ARCHITECTURE
BASED
ON
THE
CONFIGURABLE
CEPRA-S
.
822
HOFFMANN,
R.;
ULMANN,
B.;
VOLKMANN,
K.-P.;
WALDSCHMIDT,
S.
AN
INNOVATIVE
APPROACH
TO
COUPLE
EDA
TOOLS
WITH
RECONFIGURABLE
HARDWARE
.
826
HATNIK,
U.;
HAUFE,
J.;
SCHWARZ,
P.
FPL
CURRICULUM
AT
TALLINN
TECHNICAL
UNIVERSITY
.
830
TAMMEMAE,
K.;
EVARTSON,
T.
THE
MODULAR
ARCHITECTURE
OF
SYNTHUP,
FPGA
BASED
PCI
BOARD
FOR
REAL-TIME
SOUND
SYNTHESIS
AND
DIGITAL
SIGNAL
PROCESSING
.
834
RACZINSKI,
J.-M.;
SLADEK,
S.
A
RAPID
PROTOTYPING
ENVIRONMENT
FOR
MICROPROCESSOR
BASED
SYSTEM-ON-CHIPS
AND
ITS
APPLICATION
TO
THE
DEVELOPMENT
OF
A
NETWORK
PROCESSOR
.
838
BRINKMANN,
A.;
LANGEN,
D.;
RUCKERT,
U.
CONFIGURATION
PREFETCHING
FOR
NON-DETERMINISTIC
EVENT
DRIVEN
MULTI-CONTEXT
SCHEDULERS
.
842
NOGUERA,
J.;
BADIA,
R.M.
WIRELESS
BASE
STATION
DESIGN
USING
A
RECONFIGURABLE
COMMUNICATIONS
PROCESSOR
.
846
PHILLIPS,
C.
PLACEMENT
OF
LINEAR
ARRAYS
.
849
FABIANI,
E.;
LAVENIER,
D.
AUTHOR
INDEX
.
853 |
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| author_GND | (DE-588)109112660 |
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| discipline | Elektrotechnik |
| format | Conference Proceeding Book |
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| genre_facet | Konferenzschrift 2000 Villach |
| id | DE-604.BV013308822 |
| illustrated | Illustrated |
| indexdate | 2025-01-10T15:06:59Z |
| institution | BVB |
| institution_GND | (DE-588)10006698-7 |
| isbn | 3540678999 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-009074412 |
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| physical | XV, 856 S. Ill., graph. Darst. |
| publishDate | 2000 |
| publishDateSearch | 2000 |
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| publisher | Springer |
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| series | Lecture notes in computer science |
| series2 | Lecture notes in computer science |
| spelling | Field programmable logic and applications the roadmap to reconfigurable computing ; 10th international conference, FPL 2000, Villach, Austria, August 27 - 31, 2000 ; proceedings Reiner W. Hartenstein ; Herbert Grünbacher (ed.) Berlin ; Heidelberg ; New York ; Barcelona ; Hong Kong ; London Springer 2000 XV, 856 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Lecture notes in computer science 1896 Field programmable gate array (DE-588)4347749-5 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 2000 Villach gnd-content Field programmable gate array (DE-588)4347749-5 s DE-604 Hartenstein, Reiner W. 1934-2022 Sonstige (DE-588)109112660 oth FPL 10 2000 Villach Sonstige (DE-588)10006698-7 oth Lecture notes in computer science 1896 (DE-604)BV000000607 1896 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009074412&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Field programmable logic and applications the roadmap to reconfigurable computing ; 10th international conference, FPL 2000, Villach, Austria, August 27 - 31, 2000 ; proceedings Lecture notes in computer science Field programmable gate array (DE-588)4347749-5 gnd |
| subject_GND | (DE-588)4347749-5 (DE-588)1071861417 |
| title | Field programmable logic and applications the roadmap to reconfigurable computing ; 10th international conference, FPL 2000, Villach, Austria, August 27 - 31, 2000 ; proceedings |
| title_auth | Field programmable logic and applications the roadmap to reconfigurable computing ; 10th international conference, FPL 2000, Villach, Austria, August 27 - 31, 2000 ; proceedings |
| title_exact_search | Field programmable logic and applications the roadmap to reconfigurable computing ; 10th international conference, FPL 2000, Villach, Austria, August 27 - 31, 2000 ; proceedings |
| title_full | Field programmable logic and applications the roadmap to reconfigurable computing ; 10th international conference, FPL 2000, Villach, Austria, August 27 - 31, 2000 ; proceedings Reiner W. Hartenstein ; Herbert Grünbacher (ed.) |
| title_fullStr | Field programmable logic and applications the roadmap to reconfigurable computing ; 10th international conference, FPL 2000, Villach, Austria, August 27 - 31, 2000 ; proceedings Reiner W. Hartenstein ; Herbert Grünbacher (ed.) |
| title_full_unstemmed | Field programmable logic and applications the roadmap to reconfigurable computing ; 10th international conference, FPL 2000, Villach, Austria, August 27 - 31, 2000 ; proceedings Reiner W. Hartenstein ; Herbert Grünbacher (ed.) |
| title_short | Field programmable logic and applications |
| title_sort | field programmable logic and applications the roadmap to reconfigurable computing 10th international conference fpl 2000 villach austria august 27 31 2000 proceedings |
| title_sub | the roadmap to reconfigurable computing ; 10th international conference, FPL 2000, Villach, Austria, August 27 - 31, 2000 ; proceedings |
| topic | Field programmable gate array (DE-588)4347749-5 gnd |
| topic_facet | Field programmable gate array Konferenzschrift 2000 Villach |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009074412&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV000000607 |
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