Synthesis of fast controllers subject to power consumption, testability and fault tolerance:
Saved in:
| Main Author: | |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Düsseldorf
VDI-Verl.
1999
|
| Edition: | Als Ms. gedr. |
| Series: | Verein Deutscher Ingenieure: [Fortschritt-Berichte VDI / 20]
303 Berichte der GI/GMM/ITG-Kooperationsgemeinschaft Rechnergestützter Schaltungs- und Systementwurf |
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Physical Description: | IX,124 S. graph. Darst. |
| ISBN: | 3183303205 |
Staff View
MARC
| LEADER | 00000nam a2200000 cb4500 | ||
|---|---|---|---|
| 001 | BV012942354 | ||
| 003 | DE-604 | ||
| 005 | 20001106 | ||
| 007 | t | ||
| 008 | 000114s1999 d||| |||| 00||| eng d | ||
| 016 | 7 | |a 958120471 |2 DE-101 | |
| 020 | |a 3183303205 |9 3-18-330320-5 | ||
| 035 | |a (OCoLC)247178774 | ||
| 035 | |a (DE-599)BVBBV012942354 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-91G |a DE-210 |a DE-706 |a DE-83 | ||
| 084 | |a ST 190 |0 (DE-625)143607: |2 rvk | ||
| 084 | |a ELT 468d |2 stub | ||
| 100 | 1 | |a Hertwig, Andre |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Synthesis of fast controllers subject to power consumption, testability and fault tolerance |c Andre Hertwig |
| 250 | |a Als Ms. gedr. | ||
| 264 | 1 | |a Düsseldorf |b VDI-Verl. |c 1999 | |
| 300 | |a IX,124 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Verein Deutscher Ingenieure: [Fortschritt-Berichte VDI / 20] |v 303 | |
| 490 | 0 | |a Berichte der GI/GMM/ITG-Kooperationsgemeinschaft Rechnergestützter Schaltungs- und Systementwurf | |
| 650 | 4 | |a Entwurfsautomation - Reglerentwurf - Systemsynthese - Testbarkeit - Fehlertoleranz | |
| 650 | 0 | 7 | |a Reglerentwurf |0 (DE-588)4177447-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Testbarkeit |0 (DE-588)4271826-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Fehlertoleranz |0 (DE-588)4123192-2 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Systemsynthese |0 (DE-588)4198909-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Entwurfsautomation |0 (DE-588)4312536-0 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Entwurfsautomation |0 (DE-588)4312536-0 |D s |
| 689 | 0 | 1 | |a Reglerentwurf |0 (DE-588)4177447-4 |D s |
| 689 | 0 | 2 | |a Systemsynthese |0 (DE-588)4198909-0 |D s |
| 689 | 0 | 3 | |a Testbarkeit |0 (DE-588)4271826-0 |D s |
| 689 | 0 | 4 | |a Fehlertoleranz |0 (DE-588)4123192-2 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a Entwurfsautomation |0 (DE-588)4312536-0 |D s |
| 689 | 1 | 1 | |a Testbarkeit |0 (DE-588)4271826-0 |D s |
| 689 | 1 | 2 | |a Fehlertoleranz |0 (DE-588)4123192-2 |D s |
| 689 | 1 | |5 DE-604 | |
| 810 | 2 | |a 20] |t Verein Deutscher Ingenieure: [Fortschritt-Berichte VDI |v 303 |w (DE-604)BV021786833 |9 303 | |
| 856 | 4 | 2 | |m DNB Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008811897&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
Record in the Search Index
| _version_ | 1805068376387616768 |
|---|---|
| adam_text |
V
CONTENTS
PREFACE
ID
ABBREVIATIONS,
SYMBOLS
AND
IDENTIFIERS
VII
ABSTRACT
IX
1
INTRODUCTION
1
1.1
BACKGROUND
.
;
.
1
1.2
AIMS
OF
THE
RESEARCH
PROJECT
.
2
1.3
OVERVIEW
OF
THE
CONTENT
.
2
2
BACKGROUND
5
2.1
OVERALL
DESIGN
FLOW
.
5
2.2
FINITE
STATE
MACHINE
SYNTHESIS
.
7
2.3
FINITE
STATE
MACHINE
DECOMPOSITION
.
10
3
OVERALL
APPROACH
13
3.1
CONTROLLER
ARCHITECTURE
.
13
3.2
SYNTHESIS
ALGORITHM
.
18
3.2.1
CUTTING
SELF-LOOPS
.
22
3.2.2
PARTIAL
GRAPH
COLORING
.
23
3.2.3
EQUIVALENT
GRAPH
TRANSFORMATION
AND
GRAPH
COLORING
.
28
3.3
EXPERIMENTAL
RESULTS
.
33
4
PERFORMANCE
CONSIDERATIONS
37
4.1
STATE
OF
THE
ART
.
37
4.2 BYPASS-PIPELINE
WITH
ROBUST
TIMING
.
39
4.3
EXPERIMENTAL
RESULTS
.
40
5
LOW
POWER
DESIGN
45
5.1
STATE
OF
THE
ART
.
45
5.2
BYPASS-PIPELINE
WITH
GATED
CLOCKS
.
48
5.3
EXPERIMENTAL
RESULTS
.
50
VI
6
OFF-LINE
TEST
53
6.1
STATE
OF
THE
ART
.
53
6.2
BYPASS-PIPELINE
WITH
TEST-PER-CLOCK
ARCHITECTURE
.
56
6.3
BYPASS-PIPELINE
WITH
TEST-PER-SCAN
ARCHITECTURE
.
61
6.4
EXPERIMENTAL
RESULTS
.
63
7
LOW
POWER
BUILT-IN
SELF-TEST
67
7.1
STATE
OF
THE
ART
.
68
7.2
LOW
POWER
TEST-PER-CLOCK
ARCHITECTURE
.
68
7.3
LOW
POWER
TEST-PER-SCAN
ARCHITECTURE
.
71
7.4
PATTERN
SELECTION
FOR
LOW
POWER
RANDOM
BIST
.
75
8
ON-LINE
TEST
81
8.1
STATE
OF
THE
ART
.
82
8.2
ON-LINE
TEST
WITH
OFF-LINE
BIST
CIRCUITRY
.
85
8.3
TEST
CIRCUITRY
SHARING
AMONG
PIPELINE
STAGES
.
88
8.4
EXPERIMENTAL
RESULTS
.
90
9
FAULT
TOLERANT
DESIGN
93
9.1
STATE
OF
THE
ART
.
93
9.2
FAULT
TOLERANT
BYPASS-PIPELINE
.
96
10
BYPASS-PIPELINE
FOR
REACTIVE
SYSTEMS
99
10.1
THE
OVERALL
APPROACH
.
99
10.2
LOW
POWER
DESIGN
.
102
10.3
OFF-LINE
TEST
.
-.
.
103
10.4
ON-LINE
TEST
.
104
10.5
FAULT
TOLERANT
DESIGN
.
105
11
CONCLUSION
109
12
BIBLIOGRAPHY
113
INDEX
121 |
| any_adam_object | 1 |
| author | Hertwig, Andre |
| author_facet | Hertwig, Andre |
| author_role | aut |
| author_sort | Hertwig, Andre |
| author_variant | a h ah |
| building | Verbundindex |
| bvnumber | BV012942354 |
| classification_rvk | ST 190 |
| classification_tum | ELT 468d |
| ctrlnum | (OCoLC)247178774 (DE-599)BVBBV012942354 |
| discipline | Informatik Elektrotechnik |
| edition | Als Ms. gedr. |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>00000nam a2200000 cb4500</leader><controlfield tag="001">BV012942354</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20001106</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">000114s1999 d||| |||| 00||| eng d</controlfield><datafield tag="016" ind1="7" ind2=" "><subfield code="a">958120471</subfield><subfield code="2">DE-101</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">3183303205</subfield><subfield code="9">3-18-330320-5</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)247178774</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV012942354</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91G</subfield><subfield code="a">DE-210</subfield><subfield code="a">DE-706</subfield><subfield code="a">DE-83</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 190</subfield><subfield code="0">(DE-625)143607:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ELT 468d</subfield><subfield code="2">stub</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Hertwig, Andre</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Synthesis of fast controllers subject to power consumption, testability and fault tolerance</subfield><subfield code="c">Andre Hertwig</subfield></datafield><datafield tag="250" ind1=" " ind2=" "><subfield code="a">Als Ms. gedr.</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Düsseldorf</subfield><subfield code="b">VDI-Verl.</subfield><subfield code="c">1999</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">IX,124 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">Verein Deutscher Ingenieure: [Fortschritt-Berichte VDI / 20]</subfield><subfield code="v">303</subfield></datafield><datafield tag="490" ind1="0" ind2=" "><subfield code="a">Berichte der GI/GMM/ITG-Kooperationsgemeinschaft Rechnergestützter Schaltungs- und Systementwurf</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Entwurfsautomation - Reglerentwurf - Systemsynthese - Testbarkeit - Fehlertoleranz</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Reglerentwurf</subfield><subfield code="0">(DE-588)4177447-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Testbarkeit</subfield><subfield code="0">(DE-588)4271826-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Fehlertoleranz</subfield><subfield code="0">(DE-588)4123192-2</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Systemsynthese</subfield><subfield code="0">(DE-588)4198909-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Entwurfsautomation</subfield><subfield code="0">(DE-588)4312536-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Entwurfsautomation</subfield><subfield code="0">(DE-588)4312536-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Reglerentwurf</subfield><subfield code="0">(DE-588)4177447-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="2"><subfield code="a">Systemsynthese</subfield><subfield code="0">(DE-588)4198909-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="3"><subfield code="a">Testbarkeit</subfield><subfield code="0">(DE-588)4271826-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="4"><subfield code="a">Fehlertoleranz</subfield><subfield code="0">(DE-588)4123192-2</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">Entwurfsautomation</subfield><subfield code="0">(DE-588)4312536-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2="1"><subfield code="a">Testbarkeit</subfield><subfield code="0">(DE-588)4271826-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2="2"><subfield code="a">Fehlertoleranz</subfield><subfield code="0">(DE-588)4123192-2</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="810" ind1="2" ind2=" "><subfield code="a">20]</subfield><subfield code="t">Verein Deutscher Ingenieure: [Fortschritt-Berichte VDI</subfield><subfield code="v">303</subfield><subfield code="w">(DE-604)BV021786833</subfield><subfield code="9">303</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">DNB Datenaustausch</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008811897&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield></record></collection> |
| id | DE-604.BV012942354 |
| illustrated | Illustrated |
| indexdate | 2024-07-20T03:49:08Z |
| institution | BVB |
| isbn | 3183303205 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-008811897 |
| oclc_num | 247178774 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM DE-210 DE-706 DE-83 |
| owner_facet | DE-91G DE-BY-TUM DE-210 DE-706 DE-83 |
| physical | IX,124 S. graph. Darst. |
| publishDate | 1999 |
| publishDateSearch | 1999 |
| publishDateSort | 1999 |
| publisher | VDI-Verl. |
| record_format | marc |
| series2 | Verein Deutscher Ingenieure: [Fortschritt-Berichte VDI / 20] Berichte der GI/GMM/ITG-Kooperationsgemeinschaft Rechnergestützter Schaltungs- und Systementwurf |
| spelling | Hertwig, Andre Verfasser aut Synthesis of fast controllers subject to power consumption, testability and fault tolerance Andre Hertwig Als Ms. gedr. Düsseldorf VDI-Verl. 1999 IX,124 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Verein Deutscher Ingenieure: [Fortschritt-Berichte VDI / 20] 303 Berichte der GI/GMM/ITG-Kooperationsgemeinschaft Rechnergestützter Schaltungs- und Systementwurf Entwurfsautomation - Reglerentwurf - Systemsynthese - Testbarkeit - Fehlertoleranz Reglerentwurf (DE-588)4177447-4 gnd rswk-swf Testbarkeit (DE-588)4271826-0 gnd rswk-swf Fehlertoleranz (DE-588)4123192-2 gnd rswk-swf Systemsynthese (DE-588)4198909-0 gnd rswk-swf Entwurfsautomation (DE-588)4312536-0 gnd rswk-swf Entwurfsautomation (DE-588)4312536-0 s Reglerentwurf (DE-588)4177447-4 s Systemsynthese (DE-588)4198909-0 s Testbarkeit (DE-588)4271826-0 s Fehlertoleranz (DE-588)4123192-2 s DE-604 20] Verein Deutscher Ingenieure: [Fortschritt-Berichte VDI 303 (DE-604)BV021786833 303 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008811897&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Hertwig, Andre Synthesis of fast controllers subject to power consumption, testability and fault tolerance Entwurfsautomation - Reglerentwurf - Systemsynthese - Testbarkeit - Fehlertoleranz Reglerentwurf (DE-588)4177447-4 gnd Testbarkeit (DE-588)4271826-0 gnd Fehlertoleranz (DE-588)4123192-2 gnd Systemsynthese (DE-588)4198909-0 gnd Entwurfsautomation (DE-588)4312536-0 gnd |
| subject_GND | (DE-588)4177447-4 (DE-588)4271826-0 (DE-588)4123192-2 (DE-588)4198909-0 (DE-588)4312536-0 |
| title | Synthesis of fast controllers subject to power consumption, testability and fault tolerance |
| title_auth | Synthesis of fast controllers subject to power consumption, testability and fault tolerance |
| title_exact_search | Synthesis of fast controllers subject to power consumption, testability and fault tolerance |
| title_full | Synthesis of fast controllers subject to power consumption, testability and fault tolerance Andre Hertwig |
| title_fullStr | Synthesis of fast controllers subject to power consumption, testability and fault tolerance Andre Hertwig |
| title_full_unstemmed | Synthesis of fast controllers subject to power consumption, testability and fault tolerance Andre Hertwig |
| title_short | Synthesis of fast controllers subject to power consumption, testability and fault tolerance |
| title_sort | synthesis of fast controllers subject to power consumption testability and fault tolerance |
| topic | Entwurfsautomation - Reglerentwurf - Systemsynthese - Testbarkeit - Fehlertoleranz Reglerentwurf (DE-588)4177447-4 gnd Testbarkeit (DE-588)4271826-0 gnd Fehlertoleranz (DE-588)4123192-2 gnd Systemsynthese (DE-588)4198909-0 gnd Entwurfsautomation (DE-588)4312536-0 gnd |
| topic_facet | Entwurfsautomation - Reglerentwurf - Systemsynthese - Testbarkeit - Fehlertoleranz Reglerentwurf Testbarkeit Fehlertoleranz Systemsynthese Entwurfsautomation |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008811897&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV021786833 |
| work_keys_str_mv | AT hertwigandre synthesisoffastcontrollerssubjecttopowerconsumptiontestabilityandfaulttolerance |