Formal equivalence checking and design debugging:
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Boston [u.a.]
Kluwer
1998
|
| Schriftenreihe: | Frontiers in electronic testing
12 |
| Schlagworte: | |
| Beschreibung: | XVIII, 229 S.: graph. Darst. |
| ISBN: | 079238184X |
Internformat
MARC
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|---|---|---|---|
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| 003 | DE-604 | ||
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| 008 | 981015s1998 |||| 00||| eng d | ||
| 020 | |a 079238184X |9 0-7923-8184-X | ||
| 035 | |a (OCoLC)39024860 | ||
| 035 | |a (DE-599)BVBBV012203513 | ||
| 040 | |a DE-604 |b ger |e rakwb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-91 | ||
| 050 | 0 | |a TK7874 | |
| 082 | 0 | |a 621.3815 |2 21 | |
| 100 | 1 | |a Huang, Shi-Yu |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Formal equivalence checking and design debugging |c by Shi-Yu Huang and Kwang-Ting Cheng |
| 264 | 1 | |a Boston [u.a.] |b Kluwer |c 1998 | |
| 300 | |a XVIII, 229 S.: graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Frontiers in electronic testing |v 12 | |
| 650 | 4 | |a Circuits intégrés - Vérification | |
| 650 | 4 | |a Circuits intégrés à la demande - Conception et construction | |
| 650 | 4 | |a Circuits électroniques - Calcul - Informatique | |
| 650 | 4 | |a Datenverarbeitung | |
| 650 | 4 | |a Application specific integrated circuits |x Design and construction | |
| 650 | 4 | |a Electronic circuit design |x Data processing | |
| 650 | 4 | |a Integrated circuits |x Verification | |
| 700 | 1 | |a Cheng, Kwang-Ting |e Verfasser |4 aut | |
| 830 | 0 | |a Frontiers in electronic testing |v 12 |w (DE-604)BV010836129 |9 12 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-008269700 | ||
Datensatz im Suchindex
| _version_ | 1804126821027938304 |
|---|---|
| any_adam_object | |
| author | Huang, Shi-Yu Cheng, Kwang-Ting |
| author_facet | Huang, Shi-Yu Cheng, Kwang-Ting |
| author_role | aut aut |
| author_sort | Huang, Shi-Yu |
| author_variant | s y h syh k t c ktc |
| building | Verbundindex |
| bvnumber | BV012203513 |
| callnumber-first | T - Technology |
| callnumber-label | TK7874 |
| callnumber-raw | TK7874 |
| callnumber-search | TK7874 |
| callnumber-sort | TK 47874 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| ctrlnum | (OCoLC)39024860 (DE-599)BVBBV012203513 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV012203513 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T18:23:32Z |
| institution | BVB |
| isbn | 079238184X |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-008269700 |
| oclc_num | 39024860 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM |
| owner_facet | DE-91 DE-BY-TUM |
| physical | XVIII, 229 S.: graph. Darst. |
| publishDate | 1998 |
| publishDateSearch | 1998 |
| publishDateSort | 1998 |
| publisher | Kluwer |
| record_format | marc |
| series | Frontiers in electronic testing |
| series2 | Frontiers in electronic testing |
| spelling | Huang, Shi-Yu Verfasser aut Formal equivalence checking and design debugging by Shi-Yu Huang and Kwang-Ting Cheng Boston [u.a.] Kluwer 1998 XVIII, 229 S.: graph. Darst. txt rdacontent n rdamedia nc rdacarrier Frontiers in electronic testing 12 Circuits intégrés - Vérification Circuits intégrés à la demande - Conception et construction Circuits électroniques - Calcul - Informatique Datenverarbeitung Application specific integrated circuits Design and construction Electronic circuit design Data processing Integrated circuits Verification Cheng, Kwang-Ting Verfasser aut Frontiers in electronic testing 12 (DE-604)BV010836129 12 |
| spellingShingle | Huang, Shi-Yu Cheng, Kwang-Ting Formal equivalence checking and design debugging Frontiers in electronic testing Circuits intégrés - Vérification Circuits intégrés à la demande - Conception et construction Circuits électroniques - Calcul - Informatique Datenverarbeitung Application specific integrated circuits Design and construction Electronic circuit design Data processing Integrated circuits Verification |
| title | Formal equivalence checking and design debugging |
| title_auth | Formal equivalence checking and design debugging |
| title_exact_search | Formal equivalence checking and design debugging |
| title_full | Formal equivalence checking and design debugging by Shi-Yu Huang and Kwang-Ting Cheng |
| title_fullStr | Formal equivalence checking and design debugging by Shi-Yu Huang and Kwang-Ting Cheng |
| title_full_unstemmed | Formal equivalence checking and design debugging by Shi-Yu Huang and Kwang-Ting Cheng |
| title_short | Formal equivalence checking and design debugging |
| title_sort | formal equivalence checking and design debugging |
| topic | Circuits intégrés - Vérification Circuits intégrés à la demande - Conception et construction Circuits électroniques - Calcul - Informatique Datenverarbeitung Application specific integrated circuits Design and construction Electronic circuit design Data processing Integrated circuits Verification |
| topic_facet | Circuits intégrés - Vérification Circuits intégrés à la demande - Conception et construction Circuits électroniques - Calcul - Informatique Datenverarbeitung Application specific integrated circuits Design and construction Electronic circuit design Data processing Integrated circuits Verification |
| volume_link | (DE-604)BV010836129 |
| work_keys_str_mv | AT huangshiyu formalequivalencecheckinganddesigndebugging AT chengkwangting formalequivalencecheckinganddesigndebugging |