25 years of the International Symposia on Computer Architecture: selected papers
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| Format: | Book |
|---|---|
| Language: | English |
| Published: |
New York
ACM Press
1998
|
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Physical Description: | XIII, 545 S. graph. Darst. |
| ISBN: | 1581130589 |
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| 245 | 1 | 0 | |a 25 years of the International Symposia on Computer Architecture |b selected papers |c ed. by Gurindar Sohi |
| 246 | 1 | 3 | |a Twenty-five years of the International Symposia on Computer Architecture |
| 264 | 1 | |a New York |b ACM Press |c 1998 | |
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Record in the Search Index
| _version_ | 1804126820793057280 |
|---|---|
| adam_text | Table
of Retrospectives
1
Banyan NetworL· for Partitioning Multiprocessor Systems
............................................1
Jack
Lipovskí
2
A Preliminary Architecture for a Basic Data Flow Processor
..........................................2
Jack B. Dennis
3
Improving the Throughput of a Pipeline by Insertion of Delays
......................................5
Janak H.
Patel
4
What We Have Learned from the
PDP-11........................................................................6
Gorden
Bell and W.D.
Strecker
5
An Instruction Timing Model of CPU Performance
......................................................11
Leonard J. Shustek and Bernard L. Peuto
6
High-Level Language Computer Architecture
................................................................13
David R. Ditzel and David A. Patterson
7
Architecture of a Massively Parallel Processor
...............................................................15
Ken Batcher
8
A Processor for a High-Performance Personal Computer
...............................................17
Ken Pier
9
Lockup-Free Instruction Fetch/Prefetch Cache Organization
........................................20
David Kroft
10
A Study of Branch Prediction Strategies
.......................................................................22
James E. Smith
U
RISC I: A Reduced Instruction Set Computer
................................................................24
David A. Patterson and Carlo
H. Séquin
12
Decoupled Access/Execute Architectures
.......................................................................27
James E. Smith
13
The NYU Ultracomputer
...............................................................................................29
Allan Gottlieb
14
Using Cache Memory to Reduce Processor-Memory Traffic
..........................................32
James R. Goodman
15
Very Long Instruction Word Architectures and the ELI-512
.......................................34
Joseph A. Fisher
16
Characterization of Processor Performance in the VAX-11/780
...................................37
Joel Emer and Douglas W. Clark
17
A Low-Overhead Coherence Solution for Multiprocessors with
Private Cache Memories
................................................................................................39
Janak H.
Patel
18
Implementing Precise Interrupts in Pipelined Processors
..............................................42
James E. Smith
19
HPSm, a High Performance Restricted Data Flow Architecture
Having Minimal Functionality
......................................................................................43
Wen-mei W. Hwu and Yale
N.
Patt
20
The Warp Machines
.......................................................................................................45
Thomas Gross and Monica Lam
21
Memory Access Buffering in Multiprocessors
...............................................................48
Michel Dubois
and
Christoph Scheurich
22
Instruction Issue Logic for High-P
er
formance,
ìnterruptable
Pipelined Processors
.......................................................................................................51
GurindarS.
Sohi
VI
23
The J-Machine
.................................................................................................................54
William
J.
Dally, Andrew Chang, Andrew
Chien,
Stuart
Fiske,
Waldemar Horwat,
John Keen,
Richard Lethin, Michael
Noakes,
Peter Nuth, Ellen Spertus, Deborah
Wallach,
D.
Scott Wills
24
On the Inclusion Properties for Multi-Level Cache Hierarchies
...................................59
Jean-Loup
Baer and Wen-Hann Wang
25
Evaluation of Directory Schemes for Cache Coherence
..................................................61
John Hennessy
26
Weak Ordering
—
A New Definition
............................................................................63
Sarita
V. Adve and Mark D. Hill
27
Memory Consistency and Event Ordering in Scalable
Shared-Memory Multiprocessors
...................................................................................67
Kourosh Gharachorloo
28
Improving Direct-Mapped Cache Performance by the Addition of a
Small Fully-Associative Cache and Prefetch Buffers
.....................................................71
Norman P. Jouppi
29
Monsoon: An Explicit Token-Store Architecture
..........................................................74
Gregory M. Papadopoulos and David E. Culler
30
IMPACT: An Architectural Framework for Multiple-Instruction Issue
......................77
Wen-mei W. Hwu
31
The DASH Prototype: Implementation and Performance
..............................................80
Daniel E. Lenoski and James P. Laudon
32
Active Messages: A Mechanism for Integrating Computation
and Communication
.......................................................................................................83
Thorsten von
Eicken, David E. Culler, Klaus Erik Schauser
and Seth
Copen
Goldstein
VII
33
The Turn Model for Adaptive Routing
..........................................................................85
Lionel
Ni
34
Alternative Implementations of Two-Level Adaptive
Training Branch Prediction
...........................................................................................87
Yale
N.
Patt
and Tse-Yu Yeh
35
The Cedar System
............................................................................................................89
A. Veidenbaum, P.
С
Yew, D. J.
Киек, С
D. Polychronopoulos,
D. H. Padua, E.S. Davidson and K.
Gallivan
36
Virtual Memory Mapped Network Interface for the SHRIMP Multicomputer
............92
Matthias A. Blumrich,
Kai
Li, Richard D. Alpert,
Cezary
Dubnickí,
Edward
W.
Feltén
and Jonathan
Sandberg
37
The Stanford FLASH Multiprocessor
.............................................................................95
Jeffrey S. Kuskin
38
Tempest and Typhoon: User-Level Shared Memory
......................................................98
Steven K.
Reinhardt,
James R. Larus, and David A. Wood
39
The MIT Alewife Machine: Architecture and Performance
.........................................103
Anant Agarwal
40
Multiscalar Processors
..................................................................................................222
GurindarS.
Sohi
41
Simultaneous Multithreading: Maximizing On-Chip Parallelism
.............................225
Dean M. Tullsen, Susan J. Eggers, and Henry M. Levy
VUl
List of Selected Papers
ISCA
1 (1973):
1
Banyan NetworL· for Partitioning Multiprocessor Systems
........................................217
Rodney Goke and G.J.
Lipovskí
ISCA
2 (1975):
2
A Preliminary Architecture for a Basic Data Flow Processor
.......................................225
Jack B. Dennis and David P. Misunas
ISCA
3 (1976):
3
Improving the Throughput of a Pipeline by Insertion of Delays
...................................232
Janak H.
Patel
and Edward S. Davidson
4
Computer Structures: What Have We Learned from the
PDP-11?.............................238
Gordon Bell and William D.
Strecker
ISCA
4 (1977):
5
An Instruction Timing Model of CPU Performance
...................................................252
Bernard L. Peuto and Leonard J. Shustek
ISCA
7 (1980):
6
Retrospective on High-Level Language Computer Architecture
.................................266
David R. Ditzel and David A. Patterson
7
Architecture of a Massively Parallel Processor
............................................................274
Kenneth E. Batcher
8
A Processor for a High-P
er
formance
Personal Computer
............................................180
Butler W. Lampson and Kenneth A. Pier
IX
ISCA
8 (1981):
9
Lockup-Free Instruction Fetch/Prefetch Cache Organization
......................................195
David Kroft
10
A Study of Branch Prediction Strategies
......................................................................202
James E. Smith
n RISC I: A Reduced Instruction Set VLSI Computer
...................................................216
David A. Patterson and Carlo H. Sequin
ISCA
9 (1982):
12
Decoupled Access/Execute Computer Architecture
.....................................................231
James E. Smith
13
The NYU
Ultracomputer —
Designing a MIMD, Shared-Memory Parallel
Machine
....................................................................................................................239
Allan Gottlieb, Ralph
Grisham,
Clyde P. Kruskal,
Kevin P. McAuliffe, Larry Rudolph and Marc Snir
ISCA
10 (1983):
14
Using Cache Memory to Reduce Processor-Memory Traffic
.......................................255
James R. Goodman
15
Very Long Instruction Word Architectures and the ELI-512
......................................263
Joseph A. Fisher
ISCA
11 (1984):
16
A Characterization of Processor Performance in the VAX-ii/jSo
..............................274
Joel S. Emer and Douglas W. Clark
ij
A Low-Overhead Coherence Solution for Multiprocessors with Private
Cache Memories
........................................................................................................284
Mark S. Pap
amárcos
and Janak H.
Patel
ISCA
12 (1985):
18
Implementation of
Precise
Interrupts in Pipelined Processors
.....................................291
James E. Smith and Andrew R. Pleszkun
ISCA
13 (1986):
19
HPSm, a High Performance Restricted Data Flow Architecture Having
Minimal Functionality
.............................................................................................300
Wen-mei Hwu and Yale
N.
Patt
2.0
Warp Architecture and Implementation
......................................................................309
Marco Annaratone, Emmanuel Arnould, Thomas Gross,
H.T.
Kung,
Monica S. Lam, Onat Menzilcioglu, Ken Sarocky
and Jon A. Webb
21
Memory Access Buffering in Multiprocessors
.............................................................320
Michel Dubois,
Christoph
Scheurich and
Fayé
Briggs
ISCA
14 (1987):
22
instruction Issue Logic for High-Performance, Interruptable
Pipelined Processors
.................................................................................................329
GURINDAR S.
SOHI
AND SrIRAM VaJAPEYAM
23
Architecture of a Message-Driven Processor
...............................................................
33y
William J. Dally,
Linda Chao,
Andrew
Chien,
Soha Hassoun,
Waldemar
Horwat, Jon Kaplan, Paul Song, Brian Totty and
Scott Wills
ISCA
15 (1988):
24
On the inclusion Properties for Multi-Level Cache Hierarchies
..................................345
Jean-Loup
Baer and Wen-Hann Wang
25
An Evaluation of Directory Schemes for Cache Coherence
..........................................353
Anant Agarwal, Richard
Simoni,
John Hennessy and
Mark Horowitz
Xl
ISCA
17 (1990):
26
Weak Ordering—A New Definition
............................................................................
363
Sarita
V. Adve and Mark D. Hill
27
Memory Consistency and Event Ordering in Scalable Shared-Memory
Multiprocessors
........................................................................................................376
KouROSH Gharachorloo, Daniel Lenoski, James Laudon,
Phillip Gibbons, Anoop Gupta and John Hennessy
28
Improving Direct-Mapped Cache Performance by the Addition of a Small
Fully-Associative Cache and Prefetch Buffers
..........................................................388
Norman P. Jouppi
29
Monsoon: An Explicit Token-Store Architecture
..........................................................398
Gregory M. Papadopoulos and David E. Culler
ISCA
18 (1991):
30
IMPACT: An Architectural Framework for Multiple-Instruction-Issue
Processors
..................................................................................................................408
Pohua P. Chang, Scott A. Mahlke, William Y. Chen,
Nancy J.
Wärter
and Wen-mei W. Hwu
ISCA
19 (1992):
31
The DASH Prototype: Implementation and Performance
............................................4.18
Daniel Lenoski, James Laudon, Truman Joe, David Nakahira,
Luis Stevens, Anoop Gupta and John Hennessy
32
Active Messages: A Mechanism for Integrated Communication
and Computation
......................................................................................................430
Thorsten von Eicken, David E.
Culler, Seth
Copen
Goldstein
and Klaus Erik Schauser
33
The Turn Model for Adaptive Routing
........................................................................441
Christopher J. Glass and Lionel
M. Ni
34
Alternative Implementations of Two-Level Adaptive Branch Prediction
....................451
Tse-Yu Yeh and Yale
N.
Patt
Xli
ISCA
20 (1993):
35
The Cedar System and an Initial Performance Study
..................................................462
D.
Киек,
E. Davidson, D. Lawrie, A. Sameh, C. -Q. Zhu,
A. Veidenbaum,
J. Koníček,
P. Yew, K.
Gallivan,
W.
Jalby,
H. WijsHOFF, R. Bramley, U. M. Yang, P. Emrath, D. Padua,
R.
Eigenmann,
J.
Hoeflinger, G. Jaxon,
Z. Li, T.
Murphy,
J. Andrews and S. Turner
ISCA
21 (1994):
36
Virtual Memory Mapped Network Interface for the SHRIMP Multicomputer
..........
4J3
Matthias A. Blumrich,
Kai
Li, Richard Alpert,
Cezary
Dubnickí,
Edward
W.
Feltén
and Jonathan
Sandberg
yj The Stanford FLASH Multiprocessor
..........................................................................485
Jeffrey
Kuskin, David Ofelt, Mark Heinrich,
John
Heinlein,
Richard
Simoni,
Kourosh Gharachorloo, John
Chapín,
David Nakahira, Joel Baxter, Mark Horowitz, Anoop Gupta,
Mendel
Rosenblum
and John Hennessy
38
Tempest and Typhoon: User-Level Shared Memory
....................................................
49y
Steven K.
Reinhardt,
James R. Larus and David A. Wood
ISCA
22 (1995):
39
The MIT Alewif
e
Machine: Architecture and Performance
.........................................509
Anant Agarwal,
Ricardo Bianchini,
David Chaiken,
Kirk L.
Johnson, David Kranz,
John Kubiatowicz,
Beng-Hong
Lim, Kenneth
Mackenzie and Donald Yeung
ąo
Multiscalar Processors
..................................................................................................521
Gurindar S.
Sohi,
Scott E. Breach and T.N. Vijaykumar
41
Simultaneous Multithreading: Maximizing On-Chip Parallelism
..............................533
Dean M. Tullsen, Susan J. Eggers and Henry M. Levy
XIII
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| genre_facet | Aufsatzsammlung Konferenzschrift |
| id | DE-604.BV012203325 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T18:23:32Z |
| institution | BVB |
| isbn | 1581130589 |
| language | English |
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| physical | XIII, 545 S. graph. Darst. |
| publishDate | 1998 |
| publishDateSearch | 1998 |
| publishDateSort | 1998 |
| publisher | ACM Press |
| record_format | marc |
| spelling | 25 years of the International Symposia on Computer Architecture selected papers ed. by Gurindar Sohi Twenty-five years of the International Symposia on Computer Architecture New York ACM Press 1998 XIII, 545 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Ordinateurs - Architecture - Congrès Computerarchitektur (DE-588)4048717-9 gnd rswk-swf (DE-588)4143413-4 Aufsatzsammlung gnd-content (DE-588)1071861417 Konferenzschrift gnd-content Computerarchitektur (DE-588)4048717-9 s DE-604 Sohi, Gurindar Sonstige oth Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008269540&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | 25 years of the International Symposia on Computer Architecture selected papers Ordinateurs - Architecture - Congrès Computerarchitektur (DE-588)4048717-9 gnd |
| subject_GND | (DE-588)4048717-9 (DE-588)4143413-4 (DE-588)1071861417 |
| title | 25 years of the International Symposia on Computer Architecture selected papers |
| title_alt | Twenty-five years of the International Symposia on Computer Architecture |
| title_auth | 25 years of the International Symposia on Computer Architecture selected papers |
| title_exact_search | 25 years of the International Symposia on Computer Architecture selected papers |
| title_full | 25 years of the International Symposia on Computer Architecture selected papers ed. by Gurindar Sohi |
| title_fullStr | 25 years of the International Symposia on Computer Architecture selected papers ed. by Gurindar Sohi |
| title_full_unstemmed | 25 years of the International Symposia on Computer Architecture selected papers ed. by Gurindar Sohi |
| title_short | 25 years of the International Symposia on Computer Architecture |
| title_sort | 25 years of the international symposia on computer architecture selected papers |
| title_sub | selected papers |
| topic | Ordinateurs - Architecture - Congrès Computerarchitektur (DE-588)4048717-9 gnd |
| topic_facet | Ordinateurs - Architecture - Congrès Computerarchitektur Aufsatzsammlung Konferenzschrift |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008269540&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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