Making VHDL a commercial reality: proceedings ; April 28 - 30, 1993, Chateau Laurier, Ottawa, Canada
Gespeichert in:
| Format: | Tagungsbericht Buch |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
Menlo Park, Calif.
Conference Mangement Services
1993
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| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | 332 S. Ill., graph. Darst. 1 Beilage |
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VHDL INTERNATIONAL USERS’ FORUM
SPRING 1993 CONFERENCE COMMITTEE
Victor Berman
Cadence Design Systems, Inc
Conference Chair
Simon Curry
Royal Society of Canada
Program Chair
Paul Menchini
Menchini EDA Consultancy
Tutorials Chair
Andy Huang
Cadence Design Systems, Inc
Finance Chair
Nanette Collins
Exemplar Logic, Inc
Publicity Chair
Joe Youmans
Hughes Aircraft Company
Exhibits Chair
Rita Glover
Documentation and Design Services
Proceedings Chair
SPRING 1993 PROGRAM COMMITEE
Steve Bailey - Vantage Analysis Systems, Inc
Victor Berman - Cadence Design Systems, Inc
Dinesh Bettadapur - Intel Corporation
J Scott Calhoun - Mississippi State University
Simon Curry - Royal Society of Canada
Rita Glover - Documentation amp; Design Services
Paul Menchini - Menchini EDA Consultancy
Gabe Moretti - Intergraph Electronics
Larry Saunders - North Oaks EDA Consulting
Parviz Yousefpour - Bell Northern Research
Conference Management provided by:
Conference Management Services
Menlo Park, CA
VIUF OFFICERS
Larry Saunders, North Oaks EDA Consulting - Chair
John Hillawi, Design Automation Solutions, Ltd - Vice-Chair
Andy Huang, Cadence Design Systems, Inc - Treasurer
Rita Glover, Documentation and Design Services - Secretary
Sponsored by:
In Cooperation with:
VHDL
IEEE Computer Society
Inv -Nr
INTERNATIONAL
I
GENERAL SESSION
WEDNESDAY, APRIL 28,1993
1:30-3:30 pm
3:30 pm
4:00-5:30 pm
4:00-8:00 pm
5:30-7:00 pm
Welcome
Victor Berman, Conference Chair
Simon Curry, Program Chair
Announcements
Michael Carroll, President amp; COO
VHDL International
VHDL 92 Update
Chair: Victor Berman
Cadence Design Systems, Inc
Clive Chari wood - Synopsys, Inc
Paul Menchini - Menchini EDA Consultancy
Moe Shahdad - Viewlogic Systems, Inc
Cary Ussery - Cadence Design Systems, Inc
Refreshment Break
Session I — VIUF/CHDL
JOINT PANEL ON STANDARDS
Chair: Victor Berman, VIUF Conference Chair
Nick English - CFI
Bill Fuchs - OVI
Tamio Hoshino - NTT
Alec Stanculescu - Fintronic, Inc
Exhibits Open
Welcome Reception in Exhibit Hall
THURSDAY, APRIL 29,1993
8:30-10:00 am Session E—SYNTHESIS
Chair: Cary Ussery
Cadence Design Systems, Inc
A Multicomponent Synthesis Environment for
VHDL Specifications
R Vemuri, N Kumar, N Ren, Ram Vemuri
University of Cincinnati
Partitioning for Multicomponent Synthesis from
VHDL Specifications
N Kumar, Ram Vemuri, R Vemuri
University of Cincinnati
Synthesis of Testable Control Hardware
P M Campbell, Z Navabi
Northeastern University
Module Generation for VHDL Synthesis
R Dekker, M Ligthart - Exemplar Logic
PAGE NO
1
19
29
37
10:00-10:30 am
Refreshment Break
10:30-12:00 pm
12:00-1:30 pm
1:30-3:00 pm
3:00 pm
3:30-5:00 pm
3:30-7:30 pm
i 8:00 pm
Session m—USERS EXPERIENCE
Chair: Parviz Yousefpour, Bell-Northern Research, Ltd
Experiences in Real-Time Hardware-Software Co-Simulation W M Loucks, B / Doray, D G Agnew Bell-Northern Research Ltd 47
Interactive Models and Testbenches in VHDL H Thaker, J Bergeron - Bell-Northern Research Ltd 59
VHDL and it s Application for Department of Defense Contracts A E Rosenberg - Zycad Corporation T Harris - Wright Pattertson AFB 67
Modeling for Fault Insertation and Parallel Fault Simulation Z Navabi, R Liyanage - University of Tehran N Cooray - Northeastern University 75
Lunch
SessionIV-MODELING METHODOLOGY Chair: Gabe Moretti, Intergraph Electronics
RAPID: A Tool for Hardware/Software Tradeoff Analysis N Rethman, P Wilsey - University of Cincinnati 91
Modeling Techniques Using VHDL/C-Language Interfacing B K Fross - Supercomputing Research Center 101
V-Charts: A Visual Formalism for VHDL D R Smith, DEW Mercer Royal Military College of Canada 115
Petri Net Based Analysis of VHDL Behavioral Models N Stollon - Texas Instruments 125
Refreshment Break
Session V—SIMULATOR PERFORMANCE Chair: Dinesh Bettadapur, Intel Corporation
Gate-level Simulation in VHDL / Sissler, B Fazakerly, N Qureshy - Ikos Systems, Inc 135
High-Level VHDL Simulator Running on Logic Simulation Machines M Shoji, F Hirose - Fujitsu Laboratories Ltd 145
Performance: The Native Code Approach V Berman Cadence Design Systems, Inc 155
A Behavioral VHDL BUS Functional Model for the Pentium (TM) Processor S Hunt, A Mehta, D Patterson, S Shah Intel Corporation 163
Exhibits Open
Birds of a Feather Sessions
I
8:30-10:00 am
10:00 am
10:30-12:00 pm
12:00-1:30 pm
1:30-3:00 pm
Session VI — PERFORMANCE AND SYSTEM MODELING
Chair: Steve Bailey, Vantage Analysis Systems, Inc
VHDL-based Methodology for Modeling 175
Performance of Parallel Systems
P Chawla, H Hirsch - MTL Systems, Inc
Modeling of a Futurebus + System Architecture 185
Using VHDL
R Schetlick - Zycad Corporation
System-Level Modeling of Equalizers Using VHDL 195
R de Fermin, D Perez, F Reguero
Alcatel SESA RDS
Self Adjusting Unidirectional Switch Models for Dynamic 201
Load Calculation and Fast Switch Level Simulation
Z Navabi, Z Razavi - University of Tehran
Refreshment Break
Session VII — PERFORMANCE AND SYSTEM MODELING
Chair: Tedd Corman, Viewlogic Systems, Inc
Configurable VHDL Models for Field Programmable 211
Gate Arrays
M R Movahhodin, Z Navabi - University of Tehran
Using Top-Down System Simulation (TDSS) to Develop 219
a Wireless LAN System
C M Costa - Zycad Corporation
Modeling Techniques with VHDL for Jitter Performance 231
Analysis
M Bourahla, K Soh, E Aboulhamid, S Curry
Bell-Northern Research, Ltd
Topdown ASIC Design Using VHDL 243
Z Khan - Intel Corporation
Lunch
Session VIII — DESIGN METHODOLOGY
Chair: J Scott Calhoun
Mississippi State University
VHDL Design Methodologies and Management 253
J S Hong, J Lutz - LSI Logic Corporation
Testview: An Innovative Approach To Automatic 259
VHDL Testbench Generation
S Smith - Mississippi State University
Specification of Interface Behavior for the Automatic 267
Generation of Bus-Interface Models
A J Daga, W P Birmingham
University of Michigan
An Object-Oriented Schema for Electronic CAD Tools 277
E Hughes, L Huang, E J Golin
University of Illinois at Urbana-Champaign
3:00 pm
3:30-5:00 pm
Refreshment Break
Session IX— CAD TOOL ENVIRONMENT
Chair: Paul Menchini, Menchini EDA Consultancy
Parallel Simulation: Self-Extraction of the Natural
Parallelism of VHDL Models
y Herve - ENSPL/LSIT
Generic Design: Its Importance, Implementation
and Limitations
K ten Hagen, H Meyr
Aachen University of Technology
Developing a VHDL Timing Package for
Calculating Delays/Timing Constraints
B Tsai - Intergraph Electronics
Automatic Generation of Timing Annotated
VHDL Models of VLSI Circuits
R Krishnamurthy, } DeGroat
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| spelling | Making VHDL a commercial reality proceedings ; April 28 - 30, 1993, Chateau Laurier, Ottawa, Canada VIUF Spring 1993 Conference. Victor Berman, Conference Chair Menlo Park, Calif. Conference Mangement Services 1993 332 S. Ill., graph. Darst. 1 Beilage txt rdacontent n rdamedia nc rdacarrier VHDL (DE-588)4254792-1 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1993 Ottawa gnd-content VHDL (DE-588)4254792-1 s DE-604 Berman, Victor Sonstige oth VHDL International Users' Forum 1993 Ottawa Sonstige (DE-588)5305991-8 oth HEBIS Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008235392&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Making VHDL a commercial reality proceedings ; April 28 - 30, 1993, Chateau Laurier, Ottawa, Canada VHDL (DE-588)4254792-1 gnd |
| subject_GND | (DE-588)4254792-1 (DE-588)1071861417 |
| title | Making VHDL a commercial reality proceedings ; April 28 - 30, 1993, Chateau Laurier, Ottawa, Canada |
| title_auth | Making VHDL a commercial reality proceedings ; April 28 - 30, 1993, Chateau Laurier, Ottawa, Canada |
| title_exact_search | Making VHDL a commercial reality proceedings ; April 28 - 30, 1993, Chateau Laurier, Ottawa, Canada |
| title_full | Making VHDL a commercial reality proceedings ; April 28 - 30, 1993, Chateau Laurier, Ottawa, Canada VIUF Spring 1993 Conference. Victor Berman, Conference Chair |
| title_fullStr | Making VHDL a commercial reality proceedings ; April 28 - 30, 1993, Chateau Laurier, Ottawa, Canada VIUF Spring 1993 Conference. Victor Berman, Conference Chair |
| title_full_unstemmed | Making VHDL a commercial reality proceedings ; April 28 - 30, 1993, Chateau Laurier, Ottawa, Canada VIUF Spring 1993 Conference. Victor Berman, Conference Chair |
| title_short | Making VHDL a commercial reality |
| title_sort | making vhdl a commercial reality proceedings april 28 30 1993 chateau laurier ottawa canada |
| title_sub | proceedings ; April 28 - 30, 1993, Chateau Laurier, Ottawa, Canada |
| topic | VHDL (DE-588)4254792-1 gnd |
| topic_facet | VHDL Konferenzschrift 1993 Ottawa |
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