Design, test and application: ASICs and systems-on-a-chip: 10th anniversary ; digest of papers ; April 7 - 9, 1992, Bally's Park Place Casino Hotel, Atlantic City, New Jersey, USA
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| Published: |
Piscataway, NJ
IEEE
1992
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| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Physical Description: | XIV, 344 S. graph. Darst. |
| ISBN: | 0780306236 0780306244 |
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| 245 | 1 | 0 | |a Design, test and application: ASICs and systems-on-a-chip |b 10th anniversary ; digest of papers ; April 7 - 9, 1992, Bally's Park Place Casino Hotel, Atlantic City, New Jersey, USA |c 1992 IEEE VLSI Test Symposium |
| 264 | 1 | |a Piscataway, NJ |b IEEE |c 1992 | |
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Record in the Search Index
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| adam_text | 1992
IEEE VLSI TEST SYMPOSIUM
Table of Contents
General Chairpersons Welcoming Message
....................................ix
Welcoming Messages
...................................................
x
Symposium Committees and Reviewers
......................................xi
Best Paper Award
..................................................... xiii
Past Committee Members
............................................... xiv
Session
1
Delay Test
Chairperson: L.
Huisman
-
IBM
Topic Coordinator: K. Iwasaki
-
Chiba
U.
1.1
Accelerated Path Delay Fault Simulation
Y. Wu, A. Ivanov
............................................... 1
1.2
Generalization of Independent Faults for Transition Faults
I. Pomeranz, S. Reddy
............................................ 7
1.3
Test Pattern Generation System for Delay Faults Using a High Speed
Simulation Processor SP
Y. Izuta, F. Hirose
.............................................. 13
1.4
On Test Generation for Path Delay Faults in ASICs
P.
Varma
.................................................... 19
1.5
Delay Fault Testing of Iterative Arithmetic Arrays
R. Roy,
N.
Nagi,
A. Chatterjee, M. d Abreu
............................. 25
Session
2
Scan/Boundary Scan
Chairperson: M.
Breuer -
USC
Topic Coordinator:
N.
Jarwala
-
AT&T
2.1
Scan Testing of Latch Arrays
M.
Hui,
B. Nadeau-Dostie
......................................... 31
2.2
A Methodology for the Insertion of a Hierarchical and
Boundary-Scan Compatible Self Test
0.
Haberl, T.
Kropf ............................................. 37
2.3
The Split Boundary Scan Register Technique for Testing Board Interconnects
N.
Haider,
N.
Kanopoulos
......................................... 43
2.4
Testability Properties of Acyclic Structures and Applications to Partial Scan Design
R. Gupta, M.
Breuer............................................. 49
2.5
A Design for Testability Scheme to Reduce Test Application Time in Full Scan
D. Pradhan, J. Saxena
........................................... 55
III
1992
IEEE VLSI TEST SYMPOSIUM
Table of Contents
Session
3
Built-in Self-Test
Chairperson: Y. Zorian
-
AT&T Bell Labs
Topic Coordinator:
С
Kime
-
University of Wisconsin
3.1
Design of Low Cost ROM Based Test Generators
G. Edirisooriya, J. Robinson
....................................... 61
3.2
On the Effectiveness of Simultaneous
Se/f
-Test Techniques
P. Johnson, F. Ferguson
.......................................... 67
3.3
Built-in
Sel f
-Test Design for Large Embedded PLAs
A. Pierzynska, S. Pilarski
......................................... 73
3.4
Coset Error Detection in BIST Design
P. Nagvajara, M. Karpovsky
....................................... 79
Session
4
Mixed Signal Test
Chairperson M.
Soma
-
University of Washington
Topic Coordinator: Y. Malaiya
-
Colorado State University
4.1 .
A Mixed Signal Tester Solution for: Standards Traceable
AC Calibration of Analog Modules
M. Abate
.................................................... 84
4.2
A Functional BIST Approach for FIR Digital Filters
С
Counil, G. Cambon
........................................... 90
4.3
Hierarchical Fault Modeling for Analog and Mixed-signal Circuits
N.
Nagi,
J.
Abraham
............................................ 96
4.4
On-Line Testing of Switched-Capacitor Filters
J.
Huertas,
D.
Vasquez,
A. Rueda
.................................. 102
Session
5
Test Generation I
Chairperson: J. Hayes
-
University of Michigan
Topic Coordinator: P. Menon
-
University of Massachusetts
5.1
Robust Switch-level Test Generation
B. Mathew, D. Saab
........................................... 107
5.2
On Test Generation for Combinational Circuits Consisting of AND and EXOR Gates
S. Toida,
N.
Rao
.............................................. 113
5.3
An Investigation of Circuit Partitioning for Parallel Test Generation
S. Bollinger, S. Midkiff
.......................................... 119
IV
1992
IEEE VLSI TEST SYMPOSIUM
Table of Contents
5.4
On Fault Deletion Problem in Concurrent Fault Simulation for Synchronous
Sequential Circuits
K. Kim, K. Saluja
.............................................. 125
Session
6
Theoretical Issues in BIST
Chairperson: S. Pilarski
-
Simon
Fraser
University
Topic Coordinator:
N.
Nagvajara
-
Drexel University
6.1
Design of Reduced Testing for VLSI Circuits Based on Linear Code Theory
T. Pimenta, M. Mokari
.......................................... 131
6.2
BIST Linear Generator Based on Complemented Outputs
L. Lew Yan Voon, C. Dufaza,
С
Landrault
............................ 1 37
6.3
Empirical Bounds on Fault Coverage Loss Due to LFSR Aliasing
W. Debany, Jr., M. Gorniak, D. Daskiewich,
A. Macera,
К.
Kwiat,
H. Dussault
... 143
6.4
Built-in Self-Diagnostic by Space-Time Compression of Test Responses
M. Karpovsky, S. Chaudhry
...................................... 149
Session
7
Error Checking I
Chairperson: D.
Bossen -
IBM
Topic Coordinator: M. Nicolaidis
-
IMAG
7.1
A New Technique for Totally Self-checking CMOS Circuit Design
for Stuck-on and Stuck-off Faults
M. Cheema, P.
Lala
............................................ 155
7.2
A Concurrent Checking Scheme for Single and Multibit Errors in Logic Circuits
B. Kolla,
P.
Lala,
K. Yarlagadda
.................................... 1 60
7.3
A Totally Self-checking Checker for a Parallel Unordered Coding Scheme
S. Burns,
N.
Jha
.............................................. 165
Session
8
Design for Yield
Chairperson: V. Agrawal
-
AT&T
Topic Coordinator: R. Rajsuman
-
Case Western Reserve University
8.1
A Defect-Tolerant Design for Mask ROMs
K. Iwasaki, T. Fujiwara, T.
Kasami
.................................. 171
8.2
Analysis of the Die Test Optimization Algorithm for Negative Binomial Yield Statistics
С
Krishna, A. Singh
........................................... 176
1992
IEEE VLSI TEST SYMPOSIUM
Table of Contents
8.3
Optimum Redundancy Design for New-generation EPROMs Based on
Yield Analysis of Previous Generation
K. Imamiya, J. Miyamoto,
N.
Ohtsuka,
N.
Tornita,
Y. lyama
................ 182
Session
9
Fault Modeling/Diagnosis
Chairperson: S. Seth
-
University of Nebraska
Topic Coordinator: F. Ferguson
-
University of California
9.1
Detection of Multiple Faults in CMOS Circuits Using a Behavioral Approach
Y. Shen, F.
Lombardi
........................................... 188
9.2
Data Driven Neural-Based Measurement Discrimination for
1С
Parametric Faults Diagnosis
A. Wu, J. Meador
............................................. 194
9.3
Partner
SRĹs
for Improved Shift Register Diagnostics
J.
Schafer, F.
Policastri,
R. McNulty
................................. 198
9.4
Simulation of Physical Faults in VLSI Circuits
I. Hajj, T. Lee
................................................ 202
Session
10
Panel Discussion: Can VLSI Testing Achieve
10
Defective Parts per Million?
Topic Coordinator: A. Singh
-
Auburn University
10.1
Can VLSI Testing Achieve
10
Defects per Million?
A. Singh
.................................................... 208
Session
11
Panel Discussion: Is Deterministic Delay Testing Necessary to Achieve
Acceptable Quality Levels?
Topic Coordinator: P.
Varma
-
Teradyne
11.1
Importance of Deterministic Path-delay Test and Measurement in
ASIC Development/Manufacture
B. Dervisoglu
................................................ 209
11.2
Robust Tests Vs. Non-Robust Tests
S. Reddy
................................................... 210
Session
1 2
Design for Testability
Chairperson: K. Wagner
-
IBM
Topic Coordinator: K. Kinoshita
-
Osaka University
12.1
The Roles of Controllability and Observability in Design for Test
K. Butler, R. Kapur, M. Mercer, D. Ross
.............................. 211
vi
1992
IEEE VLSI TEST SYMPOSIUM
Table of Contents
1 2.2
Testing and Design for Testability of BiCMOS Logic Circuits
A. Salarna,
M. Elmasry,
......................................... 217
12.3
Probe Point Insertion for At-Speed Test
E. Rudnick, V. Chickermane, J.
Patel
................................ 223
12.4
A Testable Static RAM Structure for Efficient Coverage of Pattern Sensitive Faults
S. Su,
R.
Makki
............................................... 229
Session
13
Recent Advances
Chairperson: P.
Varma
-
Teradyne
Topic Coordinator: F.
Lombardi
-
Texas A&M University
13.1
Recent Advances in BIST
S. Gupta
................................................... 235
13.2
Recent Advances in Sequential Test Generation
K. Cheng
................................................... 241
13.3
Developments in Delay Testing
J. Savir
.................................................... 247
13.4
Recent Advances in Logic Synthesis with Testability
J.
Rajski,
J Vasudevamurthy, A. El-Maleh
............................. 254
Session
14
Test Generation II
Chairperson: D. Ross
-
Texas A&M
Topic Coordinator: S. Reddy
-
University of Iowa
14.1
Techniques to Increase Sequential A TPG Performance
E. Macii, A. Meo
.............................................. 257
14.2
A Simulation-based Approach to Test Pattern Generation for
Synchronous Sequential Circuits
P. Camurati, F.
Corno,
P. Prinetto, M. Sonza
Reorda
..................... 263
14.3
Redundancy Removal and Simplification of Combinational Circuits
P.
Menőn, H.
Ahuja
............................................ 268
14.4
Multiple Redundancy Removal During Test Generation and Synthesis
D. Wu, R. Swanson
............................................ 274
VII
1992
IEEE VLSI TEST SYMPOSIUM
Table of Contents
Session
1 5
Error Checking II
Chairperson: S. Gupta
-
U. of Southern California
Topic Coordinator: S. Toida
-
Old Dominion University
15.1
Effective Concurrent Test for a Parallel-Input Multiplier Using Modulo
3
W. Debany,, Jr.,
A. Macera,
D.
Daskiewich,
M.
Gorniak,
К.
Kwiat,
H. Dussault
. . . 280
15.2
Checksum-Based
Concurrent
Error Detection in Linear Analog Systems with Second and
Higher Order Stages
A. Chatterjee
................................................ 286
1 5.3
Zero Cost Testing of Check Bits in RAMs with On-Chip ECC
P. Ramanathan, K. Saluja, M. Franklin
............................... 292
1 5.4
Self-testing and Self-checking Combinational Circuits with Weakly Independent Outputs
E. Sogomonjan, M. Goessel
...................................... 298
Session
16
IDDQ Testing
Chairperson: R. Dandapani, University of Colorado
Topic Coordinator: A. Singh
-
Auburn University
16.1
Built-in Current Self-Testing Scheme (BICSTI for CMOS Logic Circuits
Q.
Tong
.................................................... 304
16.2
On-Chip Current Sensing Circuit for CMOS VLSI
T. Shen, J. Daly, J.
Lo
.......................................... 309
16.3
Behavior of Faulty Single BJT BiCMOS Logic Gates
S. Menon, Y. Malaiya, A. Jayasumana
............................... 315
Session
17
Design Verification and Simulation
Chairperson: G. Silberman
-
IBM
Topic Coordinator: J. Monzel
-
IBM
1 7.1
A New Tool for Random Testability Evaluation Using Simulation and Formal Proof
E. Simeu, A. Puissochet, J. Rainard, A. Tagant, M. Poize
.................. 321
1 7.2
Algorithms for the Design Verification of Bipolar Array Chips
D. Zein,
0. Engel,
G. Ditlow
...................................... 327
1 7.3
HLS/M
-
A New Hierarchical
Logic
Simulator
in APL
D.
Zein, O.
Engel,
G. Ditlow
...................................... 333
17.4
Improving the Theory of Truth Table Verification of Iterative Logic Arrays
M. Nicolaidis
................................................. 339
VIII
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| spelling | Design, test and application: ASICs and systems-on-a-chip 10th anniversary ; digest of papers ; April 7 - 9, 1992, Bally's Park Place Casino Hotel, Atlantic City, New Jersey, USA 1992 IEEE VLSI Test Symposium Piscataway, NJ IEEE 1992 XIV, 344 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Kundenspezifische Schaltung (DE-588)4122250-7 gnd rswk-swf Atlantic City, NJ (DE-588)4209017-9 gnd rswk-swf (DE-588)1071861417 Konferenzschrift gnd-content Kundenspezifische Schaltung (DE-588)4122250-7 s Atlantic City, NJ (DE-588)4209017-9 g DE-604 VLSI Test Symposium 10 1992 Atlantic City, NJ Sonstige (DE-588)5102861-X oth Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008113453&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Design, test and application: ASICs and systems-on-a-chip 10th anniversary ; digest of papers ; April 7 - 9, 1992, Bally's Park Place Casino Hotel, Atlantic City, New Jersey, USA Kundenspezifische Schaltung (DE-588)4122250-7 gnd |
| subject_GND | (DE-588)4122250-7 (DE-588)4209017-9 (DE-588)1071861417 |
| title | Design, test and application: ASICs and systems-on-a-chip 10th anniversary ; digest of papers ; April 7 - 9, 1992, Bally's Park Place Casino Hotel, Atlantic City, New Jersey, USA |
| title_auth | Design, test and application: ASICs and systems-on-a-chip 10th anniversary ; digest of papers ; April 7 - 9, 1992, Bally's Park Place Casino Hotel, Atlantic City, New Jersey, USA |
| title_exact_search | Design, test and application: ASICs and systems-on-a-chip 10th anniversary ; digest of papers ; April 7 - 9, 1992, Bally's Park Place Casino Hotel, Atlantic City, New Jersey, USA |
| title_full | Design, test and application: ASICs and systems-on-a-chip 10th anniversary ; digest of papers ; April 7 - 9, 1992, Bally's Park Place Casino Hotel, Atlantic City, New Jersey, USA 1992 IEEE VLSI Test Symposium |
| title_fullStr | Design, test and application: ASICs and systems-on-a-chip 10th anniversary ; digest of papers ; April 7 - 9, 1992, Bally's Park Place Casino Hotel, Atlantic City, New Jersey, USA 1992 IEEE VLSI Test Symposium |
| title_full_unstemmed | Design, test and application: ASICs and systems-on-a-chip 10th anniversary ; digest of papers ; April 7 - 9, 1992, Bally's Park Place Casino Hotel, Atlantic City, New Jersey, USA 1992 IEEE VLSI Test Symposium |
| title_short | Design, test and application: ASICs and systems-on-a-chip |
| title_sort | design test and application asics and systems on a chip 10th anniversary digest of papers april 7 9 1992 bally s park place casino hotel atlantic city new jersey usa |
| title_sub | 10th anniversary ; digest of papers ; April 7 - 9, 1992, Bally's Park Place Casino Hotel, Atlantic City, New Jersey, USA |
| topic | Kundenspezifische Schaltung (DE-588)4122250-7 gnd |
| topic_facet | Kundenspezifische Schaltung Atlantic City, NJ Konferenzschrift |
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