Proceedings: [November 1-6, 1997 ; Sheraton Washington Hotel, Washington, D.C., USA]
Saved in:
| Corporate Author: | |
|---|---|
| Format: | Conference Proceeding Book |
| Language: | English |
| Published: |
Piscataway, NJ
IEEE Computer Soc. Press
1997
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| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Physical Description: | XIV, 1054 S. Ill. |
| ISBN: | 0780342100 |
Staff View
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Record in the Search Index
| _version_ | 1820882525988323328 |
|---|---|
| adam_text |
INTRODUCTORY SECTION
Welcoming Message
.1
Steering Committee
.2
Technical Program Committee
.4
Technical Papers Evaluation and Selection Process
.7
1996
Paper Awards
.8
1998
Call for Papers
.9
Test Technology Technical Committee
.12
Reviewers
.14
Author Index
.1053
SESSIONI:
PLENARY
ITC
General Chair: William Bruce, TTTC Chair: Yervant Zorian
Keynote Address
Future Management of the Semiconductor Manufacturing
Process
James (Jim)T. Healy
.10
Invited Address
Plug and Play or Plug and Pray: We Have a Right to Know It Will
Work (Or Why It Won't)
Colin Maunder
.11
SESSION
2:
DYNAMIC CURRENT TESTING
Session Chair: C.Thibeault, Coordinators: R. Aitken, K. Baker
2.1
Transient Power Supply Voltage (VDDT) Analysis for
Detecting
1С
Defects
E. Cole, Jr., J. Soden, P. Tangyunyong, P.
Candelaria,
R.
Beegle,
D.
Barton,
С.
Henderson,
С.
Hawkins
.23
2.2
iDD Pulse Response Testing Applied to Complex
CMOS ICs
J. Beasley, S. Pour-Mozafari, D. Huggett, A. Righter,
C.Apodaca
.32
2.3
Identification of Defective CMOS Devices Using Correlation
and Regression Analysis of Frequency Domain Transient
Signal Data
J. Plusquellic, D.
Chiamili,
S.
Levitán
.40
SESSION
3:
EMBEDDED CORE TESTING
Session Chair: B. Koenemann, Coordinator: A. Orailoglu
3.1
A Low-Overhead Design for Testability and Test Generation
Technique for Core-Based Systems
I. Ghosh,
N.
Jha,
S. Dey
.50
3.2
Modifying User-Defined Logic for Test Access to
Embedded Cores
B. Pouya, N.Touba
.60
3.3
An IEEE
1149.1
-Based Test Access Architecture for ICs with
Embedded Cores
LWhetsel
.69
Table of
Contents
ITC
Office
2000
L
Street,
N.W.
Suite
710
Washington,
D.C.
20036
USA
Tel: (202) 973-8665
in
INTERNATIONAL
TESTCONFERENCE
1997
SESSION 4:
ATE
HARDWARE
IMPROVEMENTS FOR HIGH¬
SPEED TEST
Session Chair: M. Mydill, Coordinator: D. L. Wheater
4.1
An Efficient Method for Compressing Test Data
T. Yamaguchi, M. Ishida, M. Tilgner, D. Ha
.79
4.2
Hardware Compression Speeds on Bitmap Fail Display
B. Gage, B. Brown, J. Donaldson, A.
Joffe.89
4.3
Low-Cost
A TE Pin
Electronics for Multigigabit-per-Second
At-Speed Test
D. Keezer, R.
Wenzel.94
SESSION
5:
MCM
SYSTEMS TEST
Session Chair: Y. Zorian, Coordinator: D. Keezer
5.1
A Simulation-Based JTAGA TPG Optimized for MCMs
A. Flint
. 101
5.2
Testing the 400-MHz IBM Generation^ CMOS Chip
T. Foote, D. Hoffman, W. Huott, T. Koprowski,
B. Robbins,
M. Kusko
. 106
5.3
Testing the Enterprise IBM System/390™
Multi
Processor
O.
Torreiter,
U.
Baur,
G.
Goecke,
К.
Melocco
. 115
SESSION
6:
UNPOWERED OPENS LECTURE SERIES
Session Chair and Coordinator: K. Posse
6.1
Capacitive
Leadframe Testing
T.Turner
. 124
6.2
Analog A C Harmonic Method for Detecting Solder Opens
C.Robinson
. 125
SESSION
7:
IDDQ TESTING
Session Chair: J. Acken, Coordinator: R. Aitken
7.1
Experiences with Implementation ofl^ Test for Identification
and Automotive Products
R. Arnold, M. Feuser, H.-U.
Wedekind,
T.
Bode
.127
7.2
Ц
Characterization in
Submicron
CMOS
A. Ferre, J. Figueras
.136
7.3
Intrinsic Leakage in Low-Power Deep
Submicron
CMOS ICs
A. Keshavarzi, K. Roy, C. Hawkins
.146
7.4
Current Signatures: Application
A. Gattiker, W. Maly
.156
SESSION
8:
PROGRESS ON STANDARDS AND BENCHMARKS
Session Chair: G. Robinson, Coordinator: B. Bennetts
8.1 1149.5:
Now It's a Standard, So What?
H.Hulvershorn
. 166
8.2
IEEE P1
149.4—
Almost a Standard
A.Cron
. 174
8.3
Analog and Mixed-Signal Benchmark Circuits
—
First Release
B. Kaminska, K.
Arabi,
I. Bell, J.L.
Huertas,
B. Kim, A.
Rueda,
Μ.
Soma,
P. Goteti
. 183
iv
8.4
Test Requirements for Embedded Core-Based Systems and
IEEE P1
500
Y. Zorian
. 191
SESSION
9:
MEMORY TEST
Session Chair: B. Cockbum, Coordinator: T. Furuyama
9.1
A 256Meg SDRAM BIST for Disturb Test Application
T. Powell, D.
Cline,
F. Hü.200
9.2
Cell Signal Measurement for High-Density
DRAMs
J.
Vollrath
.209
9.3
A Self-Test Circuit for Evaluating Memory Sense-Amplifier
Signal
R. Adams, E. Cooley, P.
Hansen.217
9.4
The Implementation of Pseudo-Random Memory Tests on
Commercial Memory Testers
A. van
de Goor,
M.
Un
.226
SESSION
10:
TEST
SYNTHESIS
Session Chair:
H.
Chen, Coordinators: K. Cheng, R. Roy
10.1
Testability Enhancement for
Beha vioral
Descriptions
Containing Conditional Statements
K. Ockunzzi,
С
Papachhstou
.236
10.2
Addressing Early Design-For-Test Synthesis in a Production
Environment
V. Chickermane, K. Zarrineh
.246
10.3
A Symbolic Simulation-Based ANSI/IEEE Std
1149.1
Compliance Checker and BSDL Generator
H. Singh, J. Beausang, G. Patankar
.256
10.4
H-SCAN+: A Practical Low-Overhead
RTL Design-for-
Testability Technique for Industrial Designs
T. Asaka, M. Yoshida, S. Bhattacharya,
S. Dey
.265
SESSION
11 :
UNPOWERED OPENS LECTURE SERIES
Session Chair and Coordinator: K. Posse
11.1
RF Introduction and Analog Junction Techniques for Finding
Opens
B.K. McElfresh
.275
11.3
Unpowered Opens Test with
Х
-Ray Laminography
S. Oresjo
.276
11.4
Finding Opens with Optics
D.Raymond
.277
SESSION
12:
MICROPROCESSOR TEST I
Session Chair: G. Giles, Coordinator: W. Needham
12.1
Manufacturing Pattern Development for the Alpha
21164
Microprocessor
C. Stoličný, R.
Davies, P. McKernan,
T. Truong
.278
12.2
Design of Cache Test Hardware on the HP PA8500
J.
Brauch,
J. Fleischman
.286
12.3
Pentium® Pro Processor Design for Test and Debug
A. Carbine, D. Feltham
.294
Table of
Contents
INTERNATIONAL |
TESTCONFERENCE
I
1997
!
SESSION
13:
DIAGNOSIS
&
FAILURE ANALYSIS LECTURE SERIES
Session Chair: K. Butler, Coordinator: J. Soden
13.1
The Application of Novel Failure Analysis Techniques for
Advanced Multi-Layered CMOS Devices
Y. Hong, M. We
.304
13.2
Signature Analysis for
1С
Diagnosis and Failure Analysis
C. Henderson, J. Soden
.310
13.3
Application and Analysis of IDDQDiagnostic Software
P. Nigh, D. Forlenza, F. Motika
.319
SESSION
14:
DETERMINISTIC BIST
Session Chair: A. Crouch, Coordinators: J.
Rajski,
B.
Nadeau-Dostie
14.1
Test Width Compression for Built-in Self Testing
K. Chakrabarty, J. Liu, M. Zhu, B. Murray
.328
14.2
On Using Machine Learning for Logic BIST
C. Fagot, P.
Girard,
С.
Landrault
.338
14.3
Using BIST Control for Pattern Generation
G.
Kiefer, H.-J. Wunderlich.347
SESSION
15:
COMPONENTS FOR MCMS: KNOWN-GOOD-DIE AND
SUBSTRATES
Session Chair: B. Kim, Coordinator: D. Keezer
15.1
ASIC Manufacturing Test Cost Prediction at Early Design
Stage
V. Kim, T. Chen, M. Tegethoff
.356
15.2
Screening for Known Good Die (KGD) Based on Defect
Clustering: An Experimental Study
A. Singh, P. Nigh, C. Krishna
.362
15.3
A Low-Cost Massively-Parallel Interconnect Test Method for
MCM
Substrates
K. Newman, D. Keezer
.370
SESSION
16:
MIXED-SIGNAL SEMINAR: MEASUREMENT
TECHNIQUES
Session Chair: K.
Lanier,
Coordinators: S. Kumar,
B. Kaminska
16.1
Dynamic Testing ofADCs Using Wavelet Transforms
T. Yamaguchi, M.
Soma
.379
16.2
A Simplified Polynomial-Fitting Algorithm for
DAC
and
ADC BIST
S. Sunter,
N.
Nagi
.389
16.3
Signal Generation Using Periodic Single- and Multi-Bit
Sigma-
Delta
Modulated Streams
B. Dufort, G. Roberts
.396
SESSION
17:
MICROPROCESSOR TEST II
Session Chair: W. Needham, Coordinator: G. Giles
17.1
Testability Features
ofAMD
-Кб™
Microprocessor
R. Fetherston, I. Shaik,
S. Ma
.406
vi
17.2
Next-Generation PowerPC™ Microprocessor Test Strategy
Improvements
C. Pyron, J.
Prado,
J. Golab
.414
17.3
A Case Study of the Test
De velopment
for the
2nd
Generation ColdFire® Microprocessors
M. Mateja,
A. Crouch, R. Eisele, G. Giles,
D.
Amason
.424
SESSION
18:
DIAGNOSIS AND FAILURE ANALYSIS LECTURE
SERIES PANEL
Moderator and Organizer: K. Butler
18.1
Logic Diagnosis
—
Diversion or Necessity?
W.
Fuchs.433
18.2
Logical Diagnosis Solutions Must Drive Yield Improvement
P.Ryan
.434
18.3 1С
Diagnosis: Industry Issues
J. Soden,
С
Henderson
.435
SESSION
19:
DESIGN FOR DELAY TEST
Session Chair: V. Chickermane, Coordinator: J. Beausang
19.1
Design for Primitive Delay Fault Testability
A. Krstic, K.-T. Cheng, S. Chakradhar
.436
19.2
Scan Latch Design for Delay Test
J. Savir
.446
19.3
Delay Testing with Clock Control: An Alternative to
Enhanced Scan
R. Tekumalla, P. Menon
.454
SESSION
20:
CONCURRENT CHECKING
Session Chair: Y. Zorian, Coordinator: M. Nicolaidis
20.1
An On-Line Self-Testing Switched-Current Integrator
O. Abu-Shahla, I. Bell
.463
20.2
On-Line Testable Logic Design for FPGA Implementation
A. Burress, P.
Lala
.471
20.3
A Parameterized VHDL Library for On-Line Testing
С
Stroud, M. Ding, S. Seshadri, R. Karri, I. Kim, S. Roy,
S.Wu
.479
SESSION
21:
MIXED-SIGNAL SEMINAR: MEASUREMENTS USING
P1
149.4
Session Chair: A. Cron, Coordinator: P. Pilotte
21.1
Design, Fabrications and Use of Mixed-Signal
1С
Testability
Structures
K. Parker, J. McDermid, R. Browen, K. Nuriya, K. Hirayama,
A. Matsuzawa
.489
212
Parasitic Effect Removal for Analog Measurement in P1
149.4
Environment
C. Su,
Y.-T. Chen, S.-J.
Jou
.499
213
Implementation of Mixed CurrentA/oltage Testing Using the
IEEE P1
149.4
Infrastructure
J.
da Silva,
A. Leao, J.
Matos,
J.
Alves
.509
Table of
Contents
VII
INTERNATIONAL
TESTCONFERENCE
1997
SESSION
22:
HIGH-PERFORMANCE PROBES AND SOCKETS
Session Chair: J. Woyke, Coordinator: D. L. Wheater
22.1
High-Performance Production Test Contractors for Fine-Pitch
Integrated Circuits
J.Brandes.518
22.2
A New Probe Card Technology Using Compliant
Microsprings™
N.
Sporck
.527
22.3
The Search for the Universal Probe Card Solution
R. Bates
.533
SESSION
23:
BIST AND DFT ECONOMICS
Session Chair: S. Adham, Coordinators: B. Nadeau-Dostie,
A. Ambler
23.1
BiST-Based Diagnostics of FPGA Logic Blocks
C. Stroud, E. Lee, M. Abramovici
.539
23.2
Scan-Encoded Test Pattern Generation for BIST
K.-H. Tsai, M. Marek-Sadowska, J.
Rajski
.548
23.3
To DFT or Not to DFT?
S. Wei, P. Nag, R. Blanton, A. Gattiker, W. Maly
.557
SESSION
24:
ON-LINE TESTING TECHNIQUES FOR VLSI
Session Chair and Coordinator: M. Nicolaidis
24.1
The Fail-Stop Controller AE1
1
E. Boehl, T.
Lindenkreuz,
R.
Stephan.567
24.2
Design and Realization of an Accurate Built-in Current Sensor
for On-Line Power Dissipation Measurement and IDDQ Testing
K.Arabi,
B. Kaminska
.578
24.3
On-Line
Testing
Scheme for Clock's Faults
C. Metra, M.
Favalli,
В.
Ricco
.587
SESSION
25:
DEFECT BEHAVIOR, TEST EFFICIENCY AND FAULT
MODEL EXTENSION
Session Chair: P. Nigh, Coordinator: J. Soden
25.1
Oscillation and Sequential Behavior Caused by Interconnect
Opens in Digital CMOS Circuits
H. Konuk, F. Ferguson
.597
25.2
Test Strategy Sensitivity to Defect Parameters
M. Renovell, Y. Bertrand
.607
25.3
Fault Model Extension for Diagnosing Custom Cell Fails
G. Vandling, T.
Bartenstein.617
SESSION
26:
MIXED-SIGNAL SEMINAR PANEL: ON-CHIP
1149.4,
WHAT FOR?
Moderator: K. Parker, Organizer: S. Kumar
26.1
P1
149.4—
Problem or Solution for Mixed-Signal
1С
Design?
S. Sunter
.625
VIII
SESSION 27: BOARD-LEVEL TEST
METHODS
Session
Chair: T.
Lee,
Coordinator: P. Pilotte
27.1
Optical Communication Channel Test Using BIST Approaches
M. Gagnon,
B. Kaminska
.626
27.2
System-Level Boundary-Scan in a Highly Integrated Switch
W.Hughes
.636
27.3
Analog Fault Diagnosis for Unpowered Circuit Boards
J.-L. Huang, K.-T. Cheng
.640
27.4
Board Level Automated Fault Injection for Fault Coverage and
Diagnostic Efficiency
B. Stewart
.649
SESSION
28:
SOFTWARE FOR NEW TEST STRATEGIES
Session Chair: G. Perry, Coordinator: A. Downey
28.1
Pin Margin Analysis
R.Huston
.655
28.2
Memory Test
—
Debugging Test Vectors Without
A TE
S.
Westfall.663
28.3
A DSP-Based Feedback Loop for Mixed-Signal VLSI Testing
L. Prabhu, D.
Rosenthal.670
28.4
OLDEVD
TP: A
Novel Environment for Off-Line Debugging of
VLSI Device Test Programs
Y. Ma, W. Shi
.675
SESSION
29:
DESIGN-FOR-TEST TOPICS
Session Chair: M.
Wahl,
Coordinator: J. Beausang
29.1
Incorporating Physical Design-for- Test into Routing
R. McGowen, F. Ferguson
.685
29.2
Parameterizable Testing Scheme for FIR Filters
N.
Mukherjee, J.
Rajski,
J.
Tyszer
.694
29.3
An Efficient Scheme to Diagnose Scan Chains
S. Narayanan, A. Das
.704
29.4
Scan Synthesis for One-Hot Signals
S. Mitra, L.
Avrà, E. McCluskey
.714
SESSION
30:
SEQUENTIAL ATPG
Session Chair: M. Abramovici, Coordinators: S. Davidson, M. Iyer
30.1
Putting the Squeeze on Test Sequences
E. Rudnick, J.
Patel
.723
30.2
Sequential Test Generation with A dvanced Illegal State Search
M.
Konijnenburg,
J. van
der
Linden, A. van
de Goor.
733
30.3
A Novel Functional Test Generation Method for Processors
Using Commercial ATPG
R. Tupuri, J. Abraham
.743
30.4
Testability Analysis and A TPG on Behavioral RT-Level VHDL
F.
Corno,
P. Prinetto, M. Sonza
Reorda
.753
Table of
Contents
IX
INTERNATIONAL
TESTCONFERENCE
1997
SESSION 31:
MIXED-SIGNAL
SEMINAR: BIST/DFT
Session
Chair:
J.
Huertas,
Coordinators:
S. Sunter, G.
Roberts
31.1 HABIST:
Histogram-Based Analog
Built-in Self-Test
A.
Frisch,
Τ.
Almy
.760
31.2
Experimental Results for Current-Based Analog Scan
T. Bocek,
T. Vu, M.
Soma,
J.
Moffatt
.768
31.3
On-Chip Measurement of the Jitter Transfer Function of
Charge-Pump Phase-Locked Loops
B. Veillette, G. Roberts
.776
31.4
Oscillation Built-in Self Test (OBIST) Scheme for Functional
and Structural Testing of Analog and Mixed-Signal Integrated
Circuits
K.
Arabi,
B. Kaminska
.786
SESSION
32:
TEST ENGINEERING TOPICS
Session Chair: J. Frost, Coordinator: J. Mielke
32.1
Low Current and Low Voltages—The High-End OP AMP
Testing Challenge
B.
Cornetta,
J.
Witte.796
32.2
Real-Time In-situ
Monitoring and Characterization of
Production Wafer Probing Process
M. Quach, K. Harper
.802
32.3
Analytic Models for Crosstalk Delay and Pulse Analysis Under
Non-Ideal Inputs
W. Chen, M.
Breuer,
S.
Gupta
.809
SESSION
33:
TOOLS AND TECHNIQUES FOR DEFECT TESTING
Session Chair: T. Larrabee, Coordinators: S. Davidson, M. Iyer
33.1
How Seriously Do You Take Your Possible-Detect Faults?
R.
Raina,
С.
Njinda,
R. Molyneaux
.819
33.2
ACT: A DFT Tool for Self-Timed Circuits
A. Khoche, E.
Brunvand
.829
33.3
BART: A Bridging Fault Test Generator for Sequential Circuits
J. Cusey, J.
Patel
.838
SESSION
34:
SPECIALIZED BIST GENERATORS
Session Chair: B. Murray, Coordinator: J.
Rajski
34.1
DS-LFSR: A New BIST TPG for Low Heat Dissipation
S. Wang, S. Gupta
.848
34.2
Tree-Structured Linear Cellular Automata and Their
Applications as PRPGs
J. Li, X. Sun, K. Soon
.858
34.3
An Effective BIST Scheme for Arithmetic Logic Units
D. Gizopoulos, A. Paschalis, Y. Zorian, M. Psarakis
.868
SESSION 35:
ADVANCES IN
DIGITAL LOGIC
DIAGNOSIS
Session Chain J. Saxena,
Coordinators:
К.
Butler,
J.
Soden
35.1
Diagnosis of Bridging Faults in Sequential Circuits Using
Adaptive Simulation, State Storage, and Path-Tracing
S. Venkataraman, W.
Fuchs.878
35.2
Bridging Fault Diagnosis in the Absence of Physical
Information
D.
Lavo,
T.
Larrabee,
F.
Ferguson,
В.
Chess,
J.
Saxena,
К.
Butler
.887
35.3
Fault Diagnosis in Scan-Based BIST
J.
Rajski,
J.
Tyszer
.
894
SESSION
36:
MIXED-SIGNAL SEMINAR: FAULT MODELING
Session Chair: A. Richardson, Coordinators:
B. Kaminska,
S. Sunter
36.1
Hierarchical Specification-Driven Analog Fault Modeling for
Efficient Fault Simulation and Diagnosis
R. Voorakaranam, S. Chakrabarti, J.
Hou,
A. Gomes,
S. Cherubal, A. Chatterjee, W.
Kao
.903
36.2
Fault Macromodeling for Analog/Mixed-Signal Circuits
C.-Y. Pan, K.-T. Cheng
.
913
36.3
Development of a MEMS Testing Methodology
A. Kolpekwar, R. Blanton
.923
SESSION
37:
NEW FRONTIERS IN TEST
Session Chair and Coordinator: R. Aitken
37.1
Embedded At-Speed Test Probe
M.Aigner
.932
37.2
An IDDQ Sensor Circuit for Low-Voltage ICs
Y. Miura
.938
37.3
Supervisors for Testing Non-Deterministically Specified
Systems
T. Savor, R. Seviora
.948
SESSION
38:
DESIGN VERIFICATION AND DIAGNOSIS
Session Chair: J. Pierre Masbou, Coordinator:
S. Dey
38.1
A New Validation Methodology Combining Test and Formal
Verification for PowerPC™ Microprocessor Arrays
L.-C. Wang, M. Abadir
.954
38.2
Analyzing a PowerPC™
620
Microprocessor Silicon Failure
Using Model Checking
R, Raimi, J. Lear
.964
38.3
ErrorTracer: A Fault-Simulation-Based Approach to Design
Error Diagnosis
S.-Y. Huang, K.-T. Cheng, K.-C. Chen, D. Cheng
.974
Table of
Contents
XI
INTERNATIONAL
TEST CONFERENCE
1997
SESSION 39:
DELAY
FAULT
TESTING
Session
Chair: P. Franco, Coordinators:
S.
Davidson,
M.
Iyer
39.1
Algorithms for Switch Level Delay Fault Simulation
S.
Bose,
V. Agrawal, T. Szymanski
.982
39.2
Efficient Identification of Non-Robustly Untestable Path Delay
Faults
Z. Li, R. Brayton, Y.
Min
. 992
39.3
Effective Path Selection for Delay Fault Testing of Sequential
Circuits
T. Chakraborty, V. Agrawal
.998
SESSIONS: TEST LANGUAGE STANDARDS
Session Chair: P. McHugh, Coordinator: S. Sunter
40.1
Structuring
STIL
for Incremental Test Development
G. Maston
.1004
40.2
A Unified
Interíace
for Scan Test Generation Based on
STIL
P.
Wohl,
J. Waicukauski
.1011
40.3
Artificial Intelligence Exchange and Service Tie to All Test
Environments
(ΑΙ
-ESTA
TE)
—
A New Standard for System
Diagnostics
J. Sheppard, L. Orlidge
.1020
SESSION
41 :
ADVANCES IN PROBE TECHNOLOGY
Session Chair: W. Mann, Coordinator: G. Robinson
41.1
Advances in Probe Technology: Best Sessions of the
'97
Southwest Test Workshop
W. Mann, D. Unzicker, M. Bonham, R.
Rincón
.1030
PANEL
2:
PARTIAL SCAN IS DEAD. LONG LIVE ALMOST-FULL
SCAN!
Moderator: K. Wagner, Organizer: V. Chickermane
P2.
1
Why Would an ASIC Foundry Accept Anything Less than Full
Scan?
S.Oakland
.1031
P2.
2
The Case for Partial Scan
J. Rearick
.1032
P2.
3
Why Automate Optical Inspection
?
D. Raymond, D. Haigh
.1033
PANEL
3:
ETHICS, PROFESSIONALISM, AND ACCOUNTABILITY
—
DOES IT EXIST IN TEST?
Moderator and Organizer: A. Ambler
P3 Ethics, Professionalism and Accountability in Testing
. .
W. Simpson
.1034
XII
PANEL
4:
VISION SYSTEMS
FOR BOARD TEST: MEETING THEIR
PROMISE?
Moderator:
N.
Jarwala, Organizer: P. Pilotte
P4.
1
Vision Inspection: Meeting the Promise
?
R. Pye
.1035
P4.
2
Solder Paste Inspection: Process Control for Defect
Reduction
D.Burr
.1036
PANEL
6:
SO WHAT IS AN OPTIMAL TEST MIX? A DISCUSSION OF
THE SEMATECH METHODS EXPERIMENT
Moderator and Organizer: W. Needham
P6 So What Is an Optimal Test Mix? A Discussion of the
SEMATECH Methods Experiment
P. Nigh, W. Needham, K. Butler, P. Maxwell, R. Aitken,
W. Maly
.1037
PANEL
7:
EMBEDDED CORE TEST PLUG-N-PLAY: IS IT
ACHIEVABLE?
Moderator and Organizer: Y. Zorian
P7.
1
Thoughts on Core Integration and Test
T.Anderson
.1039
P7.2 Embedded Core Test Plug-n-Play: Is It Achievable?
R.Garcia
.1040
P7.3 Test Access of TAP'ed
&
Non-TAP'ed Cores
L. Whetsel
.1041
PANEL
8:
ON-LINE TESTING, INDUSTRIAL PRACTICE AND
PERSPECTIVES
Moderator: E.J. McCluskey, Organizer: M. Nicolaidis
P8 On-Line Testing for VLSI
M. Nicolaidis
.1042
BEST PAPER:
Weak Write Test Mode: An SRAM Cell Stability Design for
Test Technique
A. Meixner, J. Banik
.1043
Table of
Contents
XIII |
| any_adam_object | 1 |
| author_corporate | International Test Conference Washington, DC |
| author_corporate_role | aut |
| author_facet | International Test Conference Washington, DC |
| author_sort | International Test Conference Washington, DC |
| building | Verbundindex |
| bvnumber | BV011714689 |
| classification_rvk | ZN 4030 |
| classification_tum | ELT 359f |
| ctrlnum | (OCoLC)633572506 (DE-599)BVBBV011714689 |
| discipline | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Conference Proceeding Book |
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| genre | (DE-588)1071861417 Konferenzschrift 1997 Washington DC gnd-content |
| genre_facet | Konferenzschrift 1997 Washington DC |
| id | DE-604.BV011714689 |
| illustrated | Illustrated |
| indexdate | 2025-01-10T17:08:17Z |
| institution | BVB |
| institution_GND | (DE-588)1901391-7 |
| isbn | 0780342100 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007899948 |
| oclc_num | 633572506 |
| open_access_boolean | |
| owner | DE-29T DE-739 DE-91G DE-BY-TUM DE-634 DE-83 |
| owner_facet | DE-29T DE-739 DE-91G DE-BY-TUM DE-634 DE-83 |
| physical | XIV, 1054 S. Ill. |
| publishDate | 1997 |
| publishDateSearch | 1997 |
| publishDateSort | 1997 |
| publisher | IEEE Computer Soc. Press |
| record_format | marc |
| spelling | International Test Conference 28 1997 Washington, DC Verfasser (DE-588)1901391-7 aut Proceedings [November 1-6, 1997 ; Sheraton Washington Hotel, Washington, D.C., USA] International Test Conference 1997 Piscataway, NJ IEEE Computer Soc. Press 1997 XIV, 1054 S. Ill. txt rdacontent n rdamedia nc rdacarrier Mikroelektronik (DE-588)4039207-7 gnd rswk-swf Bildverstehen (DE-588)4202022-0 gnd rswk-swf Testen (DE-588)4367264-4 gnd rswk-swf Elektronik (DE-588)4014346-6 gnd rswk-swf Computerunterstütztes Verfahren (DE-588)4139030-1 gnd rswk-swf Computersimulation (DE-588)4148259-1 gnd rswk-swf Mustererkennung (DE-588)4040936-3 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf Maschinelles Sehen (DE-588)4129594-8 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf Datenverarbeitungssystem (DE-588)4125229-9 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Telekommunikation (DE-588)4059360-5 gnd rswk-swf Medizin (DE-588)4038243-6 gnd rswk-swf Prüftechnik (DE-588)4047610-8 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1997 Washington DC gnd-content Integrierte Schaltung (DE-588)4027242-4 s Prüftechnik (DE-588)4047610-8 s DE-604 Datenverarbeitungssystem (DE-588)4125229-9 s Computersimulation (DE-588)4148259-1 s 1\p DE-604 Telekommunikation (DE-588)4059360-5 s 2\p DE-604 Mikroelektronik (DE-588)4039207-7 s 3\p DE-604 Elektronik (DE-588)4014346-6 s Testen (DE-588)4367264-4 s 4\p DE-604 VLSI (DE-588)4117388-0 s Entwurf (DE-588)4121208-3 s 5\p DE-604 Computerunterstütztes Verfahren (DE-588)4139030-1 s Medizin (DE-588)4038243-6 s 6\p DE-604 7\p DE-604 Bildverstehen (DE-588)4202022-0 s Maschinelles Sehen (DE-588)4129594-8 s 8\p DE-604 Mustererkennung (DE-588)4040936-3 s 9\p DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007899948&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 4\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 5\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 6\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 7\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 8\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 9\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Proceedings [November 1-6, 1997 ; Sheraton Washington Hotel, Washington, D.C., USA] Mikroelektronik (DE-588)4039207-7 gnd Bildverstehen (DE-588)4202022-0 gnd Testen (DE-588)4367264-4 gnd Elektronik (DE-588)4014346-6 gnd Computerunterstütztes Verfahren (DE-588)4139030-1 gnd Computersimulation (DE-588)4148259-1 gnd Mustererkennung (DE-588)4040936-3 gnd Entwurf (DE-588)4121208-3 gnd Maschinelles Sehen (DE-588)4129594-8 gnd VLSI (DE-588)4117388-0 gnd Datenverarbeitungssystem (DE-588)4125229-9 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Telekommunikation (DE-588)4059360-5 gnd Medizin (DE-588)4038243-6 gnd Prüftechnik (DE-588)4047610-8 gnd |
| subject_GND | (DE-588)4039207-7 (DE-588)4202022-0 (DE-588)4367264-4 (DE-588)4014346-6 (DE-588)4139030-1 (DE-588)4148259-1 (DE-588)4040936-3 (DE-588)4121208-3 (DE-588)4129594-8 (DE-588)4117388-0 (DE-588)4125229-9 (DE-588)4027242-4 (DE-588)4059360-5 (DE-588)4038243-6 (DE-588)4047610-8 (DE-588)1071861417 |
| title | Proceedings [November 1-6, 1997 ; Sheraton Washington Hotel, Washington, D.C., USA] |
| title_auth | Proceedings [November 1-6, 1997 ; Sheraton Washington Hotel, Washington, D.C., USA] |
| title_exact_search | Proceedings [November 1-6, 1997 ; Sheraton Washington Hotel, Washington, D.C., USA] |
| title_full | Proceedings [November 1-6, 1997 ; Sheraton Washington Hotel, Washington, D.C., USA] International Test Conference 1997 |
| title_fullStr | Proceedings [November 1-6, 1997 ; Sheraton Washington Hotel, Washington, D.C., USA] International Test Conference 1997 |
| title_full_unstemmed | Proceedings [November 1-6, 1997 ; Sheraton Washington Hotel, Washington, D.C., USA] International Test Conference 1997 |
| title_short | Proceedings |
| title_sort | proceedings november 1 6 1997 sheraton washington hotel washington d c usa |
| title_sub | [November 1-6, 1997 ; Sheraton Washington Hotel, Washington, D.C., USA] |
| topic | Mikroelektronik (DE-588)4039207-7 gnd Bildverstehen (DE-588)4202022-0 gnd Testen (DE-588)4367264-4 gnd Elektronik (DE-588)4014346-6 gnd Computerunterstütztes Verfahren (DE-588)4139030-1 gnd Computersimulation (DE-588)4148259-1 gnd Mustererkennung (DE-588)4040936-3 gnd Entwurf (DE-588)4121208-3 gnd Maschinelles Sehen (DE-588)4129594-8 gnd VLSI (DE-588)4117388-0 gnd Datenverarbeitungssystem (DE-588)4125229-9 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Telekommunikation (DE-588)4059360-5 gnd Medizin (DE-588)4038243-6 gnd Prüftechnik (DE-588)4047610-8 gnd |
| topic_facet | Mikroelektronik Bildverstehen Testen Elektronik Computerunterstütztes Verfahren Computersimulation Mustererkennung Entwurf Maschinelles Sehen VLSI Datenverarbeitungssystem Integrierte Schaltung Telekommunikation Medizin Prüftechnik Konferenzschrift 1997 Washington DC |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007899948&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT internationaltestconferencewashingtondc proceedingsnovember161997sheratonwashingtonhotelwashingtondcusa |