Physical design for multichip modules:
Saved in:
| Main Author: | |
|---|---|
| Format: | Book |
| Language: | German |
| Published: |
Aachen
Shaker
1997
|
| Edition: | Als Ms. gedr. |
| Series: | Berichte aus der Elektrotechnik
|
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Item Description: | Zugl.: München, Techn. Univ., Diss., 1996 |
| Physical Description: | XIV, 127 S. Ill., graph. Darst. |
| ISBN: | 3826521854 |
Staff View
MARC
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| 100 | 1 | |a Riess, Bernhard |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Physical design for multichip modules |c Bernhard Riess |
| 250 | |a Als Ms. gedr. | ||
| 264 | 1 | |a Aachen |b Shaker |c 1997 | |
| 300 | |a XIV, 127 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 0 | |a Berichte aus der Elektrotechnik | |
| 500 | |a Zugl.: München, Techn. Univ., Diss., 1996 | ||
| 650 | 4 | |a Datenverarbeitung | |
| 650 | 4 | |a Electronic packaging |x Design | |
| 650 | 4 | |a Multichip modules (Microelectronics) |x Design and construction |x Data processing | |
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| 650 | 0 | 7 | |a Chip |0 (DE-588)4197163-2 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Entwurf |0 (DE-588)4121208-3 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Partitionierung |0 (DE-588)4139496-3 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Modul |0 (DE-588)4129770-2 |2 gnd |9 rswk-swf |
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| 689 | 2 | 2 | |a Platzierung |g Mikroelektronik |0 (DE-588)4197293-4 |D s |
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Record in the Search Index
| _version_ | 1807323578433011712 |
|---|---|
| adam_text |
CONTENTS
1
INTRODUCTION
1
1.1
MULTICHIP
MODULES
.
3
1.1.1
MCM
TECHNOLOGIES
.
3
1.1.2
MCM
TARGET
ARCHITECTURES
.
4
1.1.3
ADVANTAGES
OF
MCMS
.
5
1.2
PHYSICAL
DESIGN
FOR
MULTICHIP
MODULES
.
5
1.3
STATE
OF
THE
ART
.
7
1.3.1
PARTITIONING
.
7
1.3.1.1
DETERMINISTIC
ALGORITHMS
.
9
1.3.1.2
PROBABILISTIC
ALGORITHMS
.
14
1.3.2
PIN
ASSIGNMENT
.
16
1.3.2.1
GENERAL
PIN
ASSIGNMENT
.
17
1.3.2.2
SPECIAL
PIN
ASSIGNMENT
TECHNIQUES
.
17
1.3.3
TIMING
DRIVEN
PLACEMENT
.
18
1.3.3.1
NET-BASED
APPROACHES
.
19
1.3.3.2
PATH-BASED
APPROACHES
.
20
1.4
OBJECTIVES
OF
THIS
WORK
.
21
II
CONTENTS
2
PRELIMINARIES
23
2.1
MODELING
THE
CIRCUIT
.
23
2.2
OBJECTIVE
FUNCTIONS
.
25
2.3
K-W.Y
PARTITIONING
.
27
2.4
PARTITIONING
OBJECTIVES
.
27
2.4.1
2
WAY
PARTITIONING
OBJECTIVES
.
27
2.4.2
K-WA.Y
PARTITIONING
OBJECTIVES
.
29
3
TARGET
ARCHITECTURES
AND
DESIGN
FLOW
31
3.1
TARGET
ARCHITECTURES
AND
TECHNOLOGIES
.
31
3.2
DESIGN
FLOW
.
34
4
TIMING
ANALYSIS
37
4.1
INTERCONNECT
MODEL
.
.
.
.
37
4.2
NET
MODEL
.
39
4.3
ELMORE
DELAY
.
40
4.4
EXTENSIONS
FOR
MCMS
.
41
4.5
PATH
ANALYSIS
.
43
5
TIMING
DRIVEN
PLACEMENT
45
5.1
OUTLINE
OF
THE
PROCEDURE
.
45
5.2
OBJECTIVE
FUNCTION
.
46
5.3
DYNAMIC
NET
WEIGHT
ADAPTATION
.
47
5.4
CHOICE
OF
A
TIMING
NET
WEIGHT
INCREMENT
.
48
5.5
EXPERIMENTAL
RESULTS
.
49
CONTENTS
III
6
OBJECTIVE
FUNCTIONS
FOR
ANALYTICAL
PARTITIONING
53
6.1
RATIO
CUT
PARTITIONING
BASED
ON
A
1-DIMENSIONAL
EMBEDDING
.
53
6.2
THE
QUADRATIC
OBJECTIVE
FUNCTION
AND
THE
EIGENVECTOR
APPROACH
.
55
6.3
THE
LINEARIZED
OBJECTIVE
FUNCTION
.
56
6.4
COMPARISON
OF
THE
QUADRATIC
AND
THE
LINEARIZED
OBJECTIVE
FUNCTION:
AN
EXAMPLE
.
57
6.5
OUTLINE
OF
THE
P
ARABOLI
APPROACH
.
58
6.6
EXPERIMENTAL
RESULTS
.
59
6.6.1
ARBITRARY
PARTITION
SIZES
.
60
6.6.2
A
REDUCED
RATIO
CUT
LEVEL
.
62
6.6.3
BALANCED
PARTITION
SIZES
.
64
6.7
CONCLUSIONS
.
65
7
TIMING
DRIVEN
K-WAY
PARTITIONING
67
7.1
OUTLINE
OF
THE
PROCEDURE
.
68
7.2
CALCULATING
THE
EMBEDDING
.
70
7.3
INITIAL
PARTITIONING
.
72
7.4
K-WAY
RATIO
CUT
.
75
7.4.1
THE
A"-WAY
RATIO
CUT
PROCEDURE
.
75
7.4.2
A
NEW
PROBLEM-SPECIFIC
OBJECTIVE
FUNCTION
.
77
7.5
EXPERIMENTAL
RESULTS
.
81
7.5.1
NON-TIMING
DRIVEN
MCM
PARTITIONING
.
81
7.5.1.1
COMPARISON
TO
AN
EIGENVECTOR-TABU-SEARCH
APPROACH
81
7.5.1.2
RESULTS
FOR
LARGE
CIRCUITS
AND
ADDITIONAL
TARGET
AR
CHITECTURES
.
83
7.5.2
TIMING
DRIVEN
MCM
PARTITIONING
.
85
IV
CONTENTS
7.5.3
MULTIPLE
TYPE
FPGA
PARTITIONING
.
90
7.5.4
FLOORPLANNING
.
91
7.5.5
PARTITIONING
FOR
PARALLEL
SIMULATION
OF
ANALOG
CIRCUITS
.
92
8
PAD
ASSIGNMENT
95
8.1
PAD
ASSIGNMENT
IN
MCM
DESIGN
.
95
8.2
OUR
PAD
ASSIGNMENT
APPROACH
.
96
8.3
EXPERIMENTAL
RESULTS
.
99
9
CONCLUSION
103
REFERENCES
107
A
CONVENTIONS
AND
LIST
OF
SYMBOLS
123
A.L
CONVENTIONS
.
123
A.2
SYMBOLS
.
123 |
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| author_facet | Riess, Bernhard |
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| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_tum | ELT 272d |
| ctrlnum | (OCoLC)40153403 (DE-599)BVBBV011205915 |
| discipline | Elektrotechnik |
| edition | Als Ms. gedr. |
| format | Book |
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| id | DE-604.BV011205915 |
| illustrated | Illustrated |
| indexdate | 2024-08-14T01:14:36Z |
| institution | BVB |
| isbn | 3826521854 |
| language | German |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007516452 |
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| open_access_boolean | |
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| physical | XIV, 127 S. Ill., graph. Darst. |
| publishDate | 1997 |
| publishDateSearch | 1997 |
| publishDateSort | 1997 |
| publisher | Shaker |
| record_format | marc |
| series2 | Berichte aus der Elektrotechnik |
| spelling | Riess, Bernhard Verfasser aut Physical design for multichip modules Bernhard Riess Als Ms. gedr. Aachen Shaker 1997 XIV, 127 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Berichte aus der Elektrotechnik Zugl.: München, Techn. Univ., Diss., 1996 Datenverarbeitung Electronic packaging Design Multichip modules (Microelectronics) Design and construction Data processing Platzierung Mikroelektronik (DE-588)4197293-4 gnd rswk-swf Multichiptechnik (DE-588)4267925-4 gnd rswk-swf Chip (DE-588)4197163-2 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf Partitionierung (DE-588)4139496-3 gnd rswk-swf Modul (DE-588)4129770-2 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Chip (DE-588)4197163-2 s Modul (DE-588)4129770-2 s Entwurf (DE-588)4121208-3 s DE-604 Multichiptechnik (DE-588)4267925-4 s Partitionierung (DE-588)4139496-3 s Platzierung Mikroelektronik (DE-588)4197293-4 s DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007516452&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Riess, Bernhard Physical design for multichip modules Datenverarbeitung Electronic packaging Design Multichip modules (Microelectronics) Design and construction Data processing Platzierung Mikroelektronik (DE-588)4197293-4 gnd Multichiptechnik (DE-588)4267925-4 gnd Chip (DE-588)4197163-2 gnd Entwurf (DE-588)4121208-3 gnd Partitionierung (DE-588)4139496-3 gnd Modul (DE-588)4129770-2 gnd |
| subject_GND | (DE-588)4197293-4 (DE-588)4267925-4 (DE-588)4197163-2 (DE-588)4121208-3 (DE-588)4139496-3 (DE-588)4129770-2 (DE-588)4113937-9 |
| title | Physical design for multichip modules |
| title_auth | Physical design for multichip modules |
| title_exact_search | Physical design for multichip modules |
| title_full | Physical design for multichip modules Bernhard Riess |
| title_fullStr | Physical design for multichip modules Bernhard Riess |
| title_full_unstemmed | Physical design for multichip modules Bernhard Riess |
| title_short | Physical design for multichip modules |
| title_sort | physical design for multichip modules |
| topic | Datenverarbeitung Electronic packaging Design Multichip modules (Microelectronics) Design and construction Data processing Platzierung Mikroelektronik (DE-588)4197293-4 gnd Multichiptechnik (DE-588)4267925-4 gnd Chip (DE-588)4197163-2 gnd Entwurf (DE-588)4121208-3 gnd Partitionierung (DE-588)4139496-3 gnd Modul (DE-588)4129770-2 gnd |
| topic_facet | Datenverarbeitung Electronic packaging Design Multichip modules (Microelectronics) Design and construction Data processing Platzierung Mikroelektronik Multichiptechnik Chip Entwurf Partitionierung Modul Hochschulschrift |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007516452&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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