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| Sprache: | English |
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1996
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| Schlagworte: | |
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| Beschreibung: | 362 S.: Ill. u. graph. Darst. |
| ISBN: | 0780331060 0780331079 0780331087 0780333322 |
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| 245 | 1 | 0 | |a Proceedings |c ISPSD '96, the 8th International Symposium on Power Semiconductor Devices and ICs, Hyatt Regency, Maui, Hawaii, USA, May 20 - 23, 1996. [Ed. by C. A. T. Salama ...] |
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Datensatz im Suchindex
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| adam_text | TABLE
OF
CONTENTS
ISPSD96
Page
•
Chairman s Message
................................................................................................. 2
•
Committees
................................................................................................................ 3
•
Conference Information
............................................................................................ 5
•
Conference Highlights
______________________________________________7
•
Conference Schedule/Technical Program
.......................................·....................... 8
•
Session
1
Plenary
.........................................................·......... 27
•
Session
2
Low Voltage Devices and Circuits
----------......... 51
•
Session
3
Process Technology
............................................... 69
•
Session
5
SiC Devices and Technology
___....____.....___105
•
Session
6
Dual Gate
Thyristors—
~
-----.-------------------123
•
Session
7
Lateral HV Devices
-------------------------------,.141
•
Session
8
Posters
................................................................. 155
•
Session
9
MOS
Gated
Thyristors....--------------------------255
•
Session
10
HV
Thyristors...................................................... 273
•
Session
11
Worlishop......».^«...«»^....».»«^..^.....
291
•
Session
12
IGBTs(I)
_______________________.______297
•
Session
13
Packaging
------------------...-----------------.------315
•
Session
14
IGBTs
(Π).......
-----------------..---------------------329
•
Session
15
Bipolar Devices
................................—................. 347
JOI
*
Author s Index
......
...363
ISPSD-MAY
1996
SESSION 1
Regency Room
Mon.,
20
9:00
a.m.
PLENARY
Chairs: C.A.T.
Salama, Univ.
of Toronto, Toronto, Canada
L.
Lorenz,
Siemens, Munich, Germany
FORMAL OPENING OF CONFERENCE
(9:00)
OPENING REMARKS
R.K. Williams, General Chair, ISPSD
96
INVITED PAPERS PAGE
1.1
Power IC s in Motor Control
(9:25)
B. Murári, D.
Rossi
SGS Thomson Microelectronics, Milan, Italy
...................................................................................29
BREAK
(10:10)
1.2
GaAs Rectifiers: An Enabling
(10:25)
Technology (or High Frequency
Operation of Power
MOS
Gated
Transistors
S. Anderson
Motorola, Phoenix, USA
.................................................................................................................33
1.3
Bonded SOI Technologies for
(11:10)
High Voltage Applications
T.Abe, M. Katayama
Shin-Etsu Handotai, Gunma-Ken, Japan
........................................................................................41
ISPSD-MAY
1996
9
Mon..
20
1:30 p.m.
SESSION
2
Regency Room
LOW VOLTAGE DEVICES AND CIRCUITS
Chairs: T.R. Efland, Texas Instruments, Dallas, USA
T. Yachi, NTT, Musashino-shi, Japan
2.1
A 30-V P-Channel Trench Gated
(1:30)
DMOSFET with
900
цЛсгп2
Specific
On-Resistance at 2.7V
ЯК.
Williams, W. Grabowski, M.
Damisti
H.
Yilmaz,
M.
Chang,
К.
Owy
ang
Siliconix, Santa
Clara, USA
.............................................................................................................53
2.2
An Intelligent Power MOSFET
with
(1
:55)
Reverse
Battery
Protection for Automotive
Applications
K.
Sakamoto,
N.
Fuchigami, K. Takagawa,
S.Ohtaka
Hitachi Ltd., Tokyo,
Japan
...............................................................................................................57
2.3
A 30V
Line
Driver in Submicron BiCMOS
(2:20)
Technology
M.
Aliahmad, CA.
T.
Salama
University of
Toronto, Toronto, Canada
...........................................................................................61
2.4
Hot-Electron-Induced Degradation in
(2:45)
High-Voltage
Submicron DMOS
Transistors
S.
Mamini,
С.
Contiero
SGS-Thomson,
Milano,
Italy
...........................................................................................................65
BREAK
(3:10)
ISPSD-MAY
1996
10
SESSION 3
Regency Ballroom
Mon.,
20
3:25
p.m.
PROCESS TECHNOLOGY
Chairs: G. Charitat, LAAS/CNRS, Toulouse, France
D.M.
Kinzer, International Rectifier,
El Segundo,
USA
3.1
VLSI CMOS Fabrication Modules Combine
(3:25)
with Power Device Methods to Produce
40π)Ω&
65тД
7V Logic Level P-Power FETs
T. Efland, D. Skeiton, S. Keller,
0.
Mei
Texas Instruments, Dallas, USA
......................................................................................................71
3.2
LDMOS Implementation by Large Tilt
(3:50)
Implant in
0.6цт
BCD5 Process, Rash
Memory Compatible
С
Confiero,
P. Galbiati, M.
Palmieri, L Vecchi
SGS-Thomson,
Milano,
Italy
...........................................................................................................75
3.3
Evaluation of Thick Silicon Dioxides
(4:15)
Grown on Trench
MOS
Gate Structures
K. Nakamura, T.
Minato,
T.
Takahashi,
H.
Nakamura,
M. Harada
Mitsubishi Electric, Hyogo, Japan
...................................................................................................79
3.4
Elimination of the Birds-Beak in Trench
(4:40)
MOS-Gate Power Semiconductor Devices
N.
Thapar, B.J.
Baliga
PSRC, North Carolina State Univ., Raleigh, USA
...........................................................................83
Monday
20
RECEPTION: Sunset Terrace
(6:00-7:30)
MIXER
ISPSD-MAY
1996
11
Tue.. 21
8:30 a.m.
SESSION 4
Regency Ballroom
SOI DEVICES
Chairs: A. Nakagawa, Toshiba, Kawasaki-shi, Japan
M.A. Shibib, AT&T Bell Labs, Reading, USA
4.1
High Voltage LDMOS Transistors In
(8:30)
Submicron SOI
Films
A.K. Paul, Y.K. Leung, J.D.
Plummer, S.S
Wong,
SC.
Kuehne, V.SK. Huang*,
С. Т.
Nguyen
Stanford University, Stanford, USA
•HKUST, Hong Kong
.........................................................
4.2
High-Temperature Performance of SOI
(8:55)
and Bulk-Silicon Resurt LDMOS Transistors
£
Arnold,
S
Merchant, T. Lelavic,
H. Bhimnathwala
Philips Laboratories, Briarcliff Manor, USA
.....................................................................................93
4.3
Experimental Verification of Large Current
(9:20)
Capability of Lateral lEGTs on SOI
N.
Yasuhara, H. Funaki, T. Matsudai,
A. Nakagawa
Toshiba, Kawasaki, Japan
...............................................................................................................97
4.4
High Voltage Lateral
MOS
Thyristor (9:45)
Cascode Switch on
SOI
-
Safe Operating
Area of SOMtesurf Devices
H. Funaki,
N.
Yasuhara, A Nakagawa
Toshiba, Kawasaki, Japan
.............................................................................................................101
BREAK
(10:10)
ISPSO· MAY
1996
SESSION 5
Regency Ballroom
Tue., 21
10:25
a.m.
SiC DEVICES AND TECHNOLOGY
Chairs:
M.
Damisti, Siliconix,
Santa Clara, USA
J. Korec,
Daimler
Benz,
Frankfurt, Germany
5.1
Nitrogen Implanted, High Voltage,
(10:25)
Planar,
бН
-SiC
N+P Junction Diodes
D.AIok,B.J.
Baliga
PSRC, North Carolina State Univ., Raleigh, USA
.........................................................................107
5.2
EBIC Investigation of Edge Termination
(10:50)
Techniques for SiC Power Devices
R. Raghunathan, B.J.
Baliga
PSRC, North Carolina State Univ., Raleigh, USA
.........................................................................111
5.3
Serf-Enclosed vs. LOPOS-Terminated
(11:15)
Lateral Planar p+n and n+p Junctions in
ЗС-ЅГС/Ѕ
R.
Tyagi, T.P. Chow
Rensselaer Polytechnic, Troy,
USA...............................................................................................115
5.4
A Criticai
Look at the Performance
(11:40)
Advantages and Limitations of
4H-SÍC
Power UMOSFET Structures
A.K. Agatwal, R.R. Siergiej,
S Seshadri,
M.H. White*P.G. McMulin,
A.A.
Burk,
LB.
Rowland, CD. Brandt,
RM
Hopkins
Westinghouse,
Pittsburgh, USA
*
Lehigh University, Bethlehem, USA
............................................................................................119
ISPSD- MAY
1996
13
Tue.. 21
1:30 p.m.
SESSION 6
Regency Ballroom
DUAL GATE
THYRISTORS
Chairs: W.
Fichtner, ETH,
Zurich, Switzerland
H. Ohashi, Toshiba Corp., Kawasaki, Japan
6.1
The Dual Gate
EST:
A New MOS-Gated
(1
:30)
Thyristor
Structure
S. Sawant, S. Sridhar, B.J.
Baliga
PSRC, North Carolina State Univ., Raleigh, USA
.........................................................................125
6.2 2nd
Generation Dual Gate
MOS
Thyristors (1
:5S)
N.
Iwamum, Y. Harada, T. Iwaana, Y. Hoshl,
Y.Seld
Fuji Electric, Nagano, Japan
.........................................................................................................129
6.3
The Dual Gate MOS-Controlled
Thyristor (2:20)
(DG-MCT): A new MCT Structure with
Current Saturation Capability
U.
Mehrotra,
B.J.
Baliga
PSRC, North Carolina State Univ., Raleigh, USA
.........................................................................133
6.4
A Study on Current Handling Capability of
(2:45)
Dual Gate
MOS
Thyristor (DGMOS)
M.
Otsuki,
M.
Kirisawa,
К.
Sakurai
Fuji Electric, Nagano, Japan
.........................................................................................................137
BREAK
(3:10)
ISPSD-MAY
1996
14
SESSION 7
Regency Ballroom
Tue.. 21
3:25
p.m.
LATERAL
HV
DEVICES
Chairs:
С
Contiero, SGS-Thomson, Milan, Italy
Y. Sugawara, Hitachi, Amagasaki-shi, Japan
7.1
A Fully Resurfed, BiCMOS-Compatible
(3:25)
High Voltage
MOS
Transistor
M. Uu,
CAJ.
Salama,
P. Schvan , M. King*
University of Toronto, Toronto, Canada
*
BNR/Nortel, Ottawa, Canada
.....................................................................................................143
7.2
Self-Aligned
RESURF
to LOCOS Region
(3:50)
LDMOS Characterization Shows Excellent
Rsp vs BV Performance
T. Efland, P.
Mei,
В.
Todd,
D.
Mosher
Texas Instruments, Dallas, USA
....................................................................................................147
7.3
An
0.8μπι
High Voltage
1С
using Newly
(4:15)
Designed 600V Lateral IGBT on Thick
Buried-OxideSOl
K. Watabe, H. Akiyama, T. Terashima,
S. Nobutou, M. Yamawaki, T.Hirao
Mitsubishi Electric, Hyogo, Japan
.................................................................................................151
ISPSD-MAY
1996
15
Tue.. 21
5-6:30
p.m.
SESSION 8
Maui
Suites
1,2
POSTERS
Chairs: K. IcNkawa, Shindengen Electric, Inou-shi, Japan
A. JaecWtn, ABB, Baden-Datwill, Switzerland
R.K. Williams, Siliconix, Santa
Oara,
USA
8.1
The Behavior of Very High Current Density Power MOSFETt
J.L Evans, CLA.J. Amantunga
University
d
Cambridge, Cambridge, U.K
....................................................................................157
8.2
Future Trend« in Local Lifetime Control
J. Vobecky, P.
Håzdre
Czech Technical Univ., Prague, Czech Republic
...........................................................................161
8.3
The MOS-Gated Floating Base
Thyristor:
A New
Dual Gate
Thyristor
with Improved Forward Biased
Safe Operating Area
R. Kuriagunda, B.J.
Baliga
PSRC, North Carolina State Univ., Raleigh, USA
.........................................................................165
8.4
Optimizing the Vertical IGBT Structure-the NPT
Concept as the Most Economic and Electrically Ideal Solution for a 1200V4GBT
T.Laska,
J.
Fugger,F.Hirter, W.Schob
Siemens,
Munich,
Germany..........................................................................................................
169
8.5 Optimal Design
and Fabrication of Self-Isolated
900V LDMOS
C.C.-H.HsnY.Wang
National
Tsing Hua
Univ., Hsin-Chu, Taiwan......................................................................
Withdrawn
8.6 Rapid Thennal
Modeling for Smart-Power and Integrated Multichip Power Circuit Design
P.Dupuy^.-M.
Dortu/,
P. Tounsi,
L
BorucM
LAAS/CNRS, Toulouse, France
*
Motorola, Mesa, USA
.................................................................................................................173
ISPSD-MAY
1996
16
SESSION 8
Maui
Suites
1,2
Tue.. 21
5-6:30
p.m.
POSTERS
8.7
An Intelligent Vertical Trench DMOS on SIMOX-Substrate
F. Vogt,
H.
Vogt,C.Zimmermann,F.Richter
FhG IMS, Duisburg,
Germany
.......................................................................................................177
8.8 An
Observation of Large and Long Current Pulses below the Breakdown Voltage of PIN Diode
I.Takata
Mitsubishi Electric, Amagasaki, Japan
..........................................................................................181
8.9
Multi-Megahertz PWM Converters with Improved
1
μτη
PMOS Transistors
T. Fowler, R. Kollman, T. Efland, D. Sketton
Texas Instruments, Dallas, USA
....................................................................................................185
8.10
The Effect of DMOS Cell Geometry on the Integrated Current Sensors of High-Voltage Power MOSFETs
R.H.Zhu.T.P.Chow
Rensselaer Polytechnic, Troy, USA
...............................................................................................189
8.11
High-Energy
Al
Implantation Techniques for Power Semiconductor Devices
J.H. CM, K.
Salto,
К.
Ishikawa,
S.
Kate,
T. Yokota, Y. Yamaguchl, A. Watanabe
Hitachi
Ltd., Ibaraki, Japan
............................................................................................................193
8.12
Light Triggered
8kV
Thyristors
with a Novel Integrated Breakover Diode
H.-J.
Schulze,
M
Ruff, B.
Baw
Siemens AG, Munich, Germany
....................................................................................................197
8.13
Design
and Fabrication of a New High Voltage Limiting Current Device for Series Protection Applications
J.-L Sanchez, Ph. Leturcq, P.Austin, R.
Barrían«,
M.Breil
LAAS/CNRS, Toulouse, France
.....................................................................................................201
ISPSD-MAY
1996
17
Tue.. 21
5-6:30
p.m.
SESSION 8
Maui
Suites
1,2
POSTERS
8.14
The Effect of Electron Beam Irradiation on Insulating Characteristics of Molding Compound for Power Semicon¬
ductor Modules
N.
Hong, P.
Im,
Y.-W. Lee, D.-C. Cho , J.-W. Hong
Samsung Electronics, Kyunggi-do, South Korea
*
Kwang Woon Univ.,
Seoul, South Korea
....................................................................................207
8.15
Experimental Investigation of High Voltage and High Current Gain of a Lateral Bipolar Transistor Based on a
Lateral DMOS Structure
U.A.
Shibib
AT&T Bell
Lab.,
Reading, USA
......................................................................................................211
8.16
Fabrication of SOI Structures by Uniform Zone Melting Recrystaliization for High Voltage ICs
J.-M. Dilhac, D. Zerrouk,
С
Ganlbal, P.
Rossel,
M.Bafleuŕ
LAAS-CNRS, Toulouse, France
*
Motorola,
Tempe, USA
...............................................................................................................215
8.17
Undamped Inductive Switching of Integrated Quasi-Vertical DMOSFETs
R. Constapel
Daimler-Benz
AG,
Frankfurt, Germany
.........................................................................................219
8.18
Modeling the Thermal Transients in Automotive Power ICs
M.S. Shekar, A. Hartular, B. Wrathall, R.K. Williams
Siliconix, Santa Clara, USA
...........................................................................................................223
8.19
A Study on Edge Termination Technique at Low Temperature for High Voltage IGBT
R. Saitoh, M. Yoshino, M. Otsuki, K. Sakurai
Fuji Electric, Nagano, Japan
.........................................................................................................227
ISPSD-MAY
1996
18
SESSION 8
Maui
Suites
1,2
Tue.. 21
5-6:30
p.m.
POSTERS
8.20
Self-Shielding: New High Voltage Inter-Connection Technique for HVICs
T.Fujlhira, Y.
Vano ,
S. Obinata,
N.
Kumagal ,
K. Sakurai
Fuji Electric, Nagano, Japan
.........................................................................................................231
8.21
Thermal Management and Design Aspects of High Performance Plastic Quad Flat Packages for Smart-Power ICs
M.
Kasem
Siliconix, Santa Clara, USA
...........................................................................................................235
8.22
Optimization of UGBTs in a Dielectric Insulated IC-Technology using a Switched Anode
KG. Oppermann, At. Stoisiek
Siemens, Munich, Germany
..........................................................................................................239
8.23
A High Density Self-Aligned 4-Mask Planar VDMOS Process
D. Kinzer, J.S.. Ajit, K. Wagers, D.
Asselanis
International Rectifier,
El Segundo,
USA
.......................................................................................243
8.24
A New Spiral Junction Termination Structure
D.
Križaj,
S.
Amon
Univ. of Ljubljana, Ljubljana, Slovenia
...........................................................................................247
ISPSD-MAY
1996
19
Wed..
22
8:30 a.m.
SESSION
9
Regency Ballroom
MOS GATED
THYRISTORS
Chairs: T.P. Chow, Rensselaer Polytechnic, Troy, USA
H.J.
Schulze,
Siemens, Munich, Germany
9.1
4kV1n»ulate<l Gate Controlled
Thyristor (8:30)
with Low On-State
Vottage
Drop
J.
Salano,
Н.КоЬауа$Ш,М.Нада$и,Ш.ійогІ
Hitachi
Ud., Ibaraki-ken,
Japan
.....................................................................................................253
9.2
Mode-Transition Optimized ^SkVIGTT
(8:55)
(IGBT Mode
Turn-Off Thyristor)
M.
Yamaguchi,
T.
Ogura,
H.
Nìnomlya,
H.Ohashi
Toshiba
Соф.,
Kawasaki,
Japan...................................................................................................
257
9.3
Punchthrough Type GTO with Buffer
(9:20)
Layer and Homogeneous Low Efficiency
Anode Structure
5.
Eicher, F. Bauer, A. Weber,
НЛ
Zeller,
W.
Fichtner
ΕΤΗ,
Zurich, Switzerland
ABB,
Lenzburg,
Switzerland
.......................................................................................................261
9.4
Two-Dimensional Analysis of Surge
(9:45)
Responses in
Thyristor
Lightning Surge
Protection Devices
H. Satoh, Y. Stiimoda
NTT Labs., Tokyo, Japan
..............................................................................................................265
BREAK
(10:10)
ISPSD-MAY
1996
20
SESSION 10
Regency Ballroom
Wed..
22
10:25
a.m.
HV
THYRISTORS
Chairs: F. Bauer, ABB,
Lenzburg,
Switzeriand
R.
Sittig, Tech.
Univ. Braunschweig, Germany
10.1
The
DI
Lateral Insulated Gate Field
(10:25)
Controlled
Thyristor
(UGFT)
R. Sunkavalli,
A. Tamba,
B.J.
Baliga
PSRC, North Carolina State Univ., Raleigh, USA
.........................................................................271
10.2
A Fomentation Free Insulated-
(10:50)
Gate Controlled
Thyristor
and Comparisons
tothelGBT
K.
Ulja,
R.
Zlngg,
W.
Fichtner
ΕΤΗ,
Zurich, Switzerland
...............................................................................................................275
10.3
A New Structural Concept to Suppress
(11:15)
Parasitic Lateral Carrier Injection In
Insulated-Gate
Thyristors
J.S.Aß
International Rectifier,
El Segundo,
USA
.......................................................................................279
10.4
The SIMEST: A New MOS-Gated Emitter
(11:40)
Switched
Thyristor
Structure without
Parasitic
Thyristor
achieved using
SIMOX
Technology
S. Sridhar, B.J.
Baliga
PSRC, North Carolina State Univ., Raleigh, USA
.........................................................................283
ISPSD-MAY
1996
21
Wed..
22
1:30 p.m.
SESSION
11
Regency Ballroom, Maui Suites
1-4
WORKSHOP
Chair. P.LHower.Unitrode.Memmack.USA
INTRODUCTION: Regency Ballroom
BREAK OUT GROUP SESSIONS: Maid Suites
(1:30).
(1*5)
.287
•
High Power Devices and Power Modules
L
Lorenz
Siemens Seiconductor, Munich, Germany
•
Discrete Power Devices
D.Kinzer
International Rectifier,
El Segundo, USA
•
High Voltage and Power IC s
M.A. Shibib
AT&T Bell Labs., Reading, USA
BREAK
(3:45)
CONCLUSION: Regency Ballroom
(4:15)
Wednesday
22
LUAU
&
BANQUET:
Napili
Garden
(7:00)
ISPSD-MAY
1996
22
SESSION 12
Regency Ballroom
Thurs.,23
8:30 a.m.
IGBTs (I)
Chairs: S.P.
Robb,
Motorola, Phoenix, USA
Y. Seki, Fuji Electric, Matsumoto, Japan
12.1
Monolithic Integration of the Vertical IGBT
(8:30)
and Intelligent Protection Circuits
Z.H.
Shen, S.P.
Robb
Motorola, Phoenix, USA
...............................................................................................................295
12.2
2.5kV-1000A Power Pack IGBT (High Power
(8:55)
Flat-Packaged RC-IGBT)
Y. Takahashi, K. Yoshikawa, T.Koga, T. Fuji,
M. Ichijyou, Y. Seki
Fuji Electric, Matsumoto, Japan
....................................................................................................299
12.3
Current Sensing IGBT for Future Intelligent
(9:20)
Power Module
M. Kudoh, Y.Hoshi, S. Momota, T.Fujihlra,
K. Sakurai
Fuji Electric, Nagano, Japan
.........................................................................................................303
12.4
ADFET-A Simple Inexpensive Power Device
(9:45)
F.Y.Robb
Motorola, Phoenix, USA
...............................................................................................................307
BREAK
(10:10)
ISPSD- MAY
1996
23
Thurs..
23
10:25 a.m.
SESSION
13
Regency Ballroom
PACKAGING
Chaire: Y.
Choi, Ajou University, Seoul, South Korea
Y. Uchida, Fuji Electric, Tokyo, Japan
13.1
Thermally-Enhanced SOIC Packages
(10:25)
for Power
Ю
Devices
A.R. Chowdhury, B.M. Guenin, R. Groover,
S. Anderson
Amkor Electronics, Chandler, USA
................................................................................................313
13.2
A New Low Temperature Diffusion Bonding
(10:50)
Technology between Large-Area, High
Power Devices and Internal Mo Electrodes
Using Au-AI Films
J. Onuki,
M. Satou, S.
Murakami,
T. Monta,
T. Yatsuo
Hitachi
Ltd., Ibaraki-ken, Japan
.....................................................................................................317
13.3
An
Approach
f or
Packaging
High
Performance Power Devices
B.
Ormai
V.
Temple
Harris
Power R&O,
Latham,
USA
.......................................................................................
Withdrawn
13.4
A
Novel Low-Profile
Power Module
Aimed
(11:15)
at High Frequency Applications
&
Shinohara,
T. Suzuki, K.
Tanino,
H.
Kobay
astii, Y.Hasegawa
Origin Electric, Tokyo, Japan
.........................................................................................................321
ISPSD-MAY
1996
24
SESSION 14
Regency Ballroom
Thurs.,23
1:30
p.m.
IGBTs (II)
Chairs: K. Akahane,
Oki
Electric, Hachioji-shi, Japan
J. Shen, Motorola, Phoenix, USA
14.1
Design Considerations and Characteristics
(1
:30)
of Rugged Punchthrough (PT) IGBTs with
4.5kV Blocking Capability
F.Bauer, U. Thiemann, T. Stockmeler,
E
Herr, T.Frey
ABB Semiconductors,
El Segundo,
USA
......................................................................................327
14.2
NPT-IGBT
·
Optimizing for Manufacturability
(1
:55)
D. Burns, I.
Deram,
J.
Me/Io,
J. Morgan
/.Wan,
F. Robb
Motorola, Phoenix, USA...............................................................................................................331
14.3
Optimized Local Lifetime Control for the
(2:20)
Superior IGBTs
Y. Konishi, Y. Onishi, S. Momota, K. Sakurai
Fuji Electric, Nagano, Japan
.........................................................................................................335
14.4
Analysis of Direct Wafer Bond IGBTs with
(2:45)
Heavily Doped N+ Buffer Layer
S.L.
Tu, G. Tam,
P.
Tam,
H.-Y.
Tsoi,
A.
Taomoto
Motorola,
Mesa, USA
...................................................................................................................339
BREAK
(3:10)
ISPSD-MAY
1996
25
Thurs..
23
3:25 p.m.
SESSION
15
Regency Ballroom
BIPOLAR DEVICES
Chairs: B.J.
Baliga,
North Carolina State Univ., Raleigh, USA
P.
Spirito, Univ. Napoli, Napoli,
Italy
15.1 Grounded-Trench-MOS
Structure Assisted
(3:25)
Normally-Off Bipolar-Mode Power
FET
Y.
Murakami, Y.Nakajima, T.Hayashl,
T.Mihara
Nissan Motor Co., Yokosuka-shi, Japan
........................................................................................345
15.2
Carrier Stored Trench-Gate Bipolar
(3:50)
Transistor (CSTBT)
-
A Novel Power
Device for High Voltage Application
H. Takahashi, T. Yamada
Mitsubishi Electric, Fukuoka, Japan
..............................................................................................349
15.3
An Analysis and Improvement of
(4:15)
Destruction Immunity During Reverse
Recovery for High Voltage Planar Diode
under High dlrr/dt Condition
Y. Tomomatsu ,
£
Suekawa, M. Takeda,
T.
Enjąi ,
H. Kondoh, H. Hagino, T. Yamada
Mitsubishi Electric, Fukuoka,
Japan
*
Fukuryo
Semiconductor,
Fukuoka,
Japan
**
MELNIC, Fukuoka,
Japan
.........................................................................................................353
Thursday
23
Regency Ballroom
(4:40)
BEST STUDENT PAPER AWARD
CA. T. Salarna
CLOSING REMARKS R.K. Williams
ISPSD-MAY
1996
26
|
| any_adam_object | 1 |
| author_corporate | ISPSD |
| author_corporate_role | aut |
| author_facet | ISPSD |
| author_sort | ISPSD |
| building | Verbundindex |
| bvnumber | BV011138119 |
| classification_rvk | ZN 1900 |
| classification_tum | ELT 318f |
| ctrlnum | (OCoLC)258220189 (DE-599)BVBBV011138119 |
| discipline | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Conference Proceeding Book |
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| genre | (DE-588)1071861417 Konferenzschrift 1996 Maui gnd-content |
| genre_facet | Konferenzschrift 1996 Maui |
| id | DE-604.BV011138119 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T18:04:37Z |
| institution | BVB |
| institution_GND | (DE-588)5184614-7 |
| isbn | 0780331060 0780331079 0780331087 0780333322 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007464456 |
| oclc_num | 258220189 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM DE-83 |
| owner_facet | DE-91 DE-BY-TUM DE-83 |
| physical | 362 S.: Ill. u. graph. Darst. |
| publishDate | 1996 |
| publishDateSearch | 1996 |
| publishDateSort | 1996 |
| publisher | IEEE Service Center |
| record_format | marc |
| spelling | ISPSD 8 1996 Verfasser (DE-588)5184614-7 aut Proceedings ISPSD '96, the 8th International Symposium on Power Semiconductor Devices and ICs, Hyatt Regency, Maui, Hawaii, USA, May 20 - 23, 1996. [Ed. by C. A. T. Salama ...] Piscataway, NJ IEEE Service Center 1996 362 S.: Ill. u. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Leistungshalbleiter (DE-588)4167286-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1996 Maui gnd-content Leistungshalbleiter (DE-588)4167286-0 s DE-604 Integrierte Schaltung (DE-588)4027242-4 s Salama, C. A. Sonstige oth Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007464456&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Proceedings Integrierte Schaltung (DE-588)4027242-4 gnd Leistungshalbleiter (DE-588)4167286-0 gnd |
| subject_GND | (DE-588)4027242-4 (DE-588)4167286-0 (DE-588)1071861417 |
| title | Proceedings |
| title_auth | Proceedings |
| title_exact_search | Proceedings |
| title_full | Proceedings ISPSD '96, the 8th International Symposium on Power Semiconductor Devices and ICs, Hyatt Regency, Maui, Hawaii, USA, May 20 - 23, 1996. [Ed. by C. A. T. Salama ...] |
| title_fullStr | Proceedings ISPSD '96, the 8th International Symposium on Power Semiconductor Devices and ICs, Hyatt Regency, Maui, Hawaii, USA, May 20 - 23, 1996. [Ed. by C. A. T. Salama ...] |
| title_full_unstemmed | Proceedings ISPSD '96, the 8th International Symposium on Power Semiconductor Devices and ICs, Hyatt Regency, Maui, Hawaii, USA, May 20 - 23, 1996. [Ed. by C. A. T. Salama ...] |
| title_short | Proceedings |
| title_sort | proceedings |
| topic | Integrierte Schaltung (DE-588)4027242-4 gnd Leistungshalbleiter (DE-588)4167286-0 gnd |
| topic_facet | Integrierte Schaltung Leistungshalbleiter Konferenzschrift 1996 Maui |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007464456&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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