Circuits and systems tutorials:
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| Format: | Book |
|---|---|
| Language: | English |
| Published: |
New York
IEEE Press
1996
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| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Physical Description: | XXXVIII, 659 S.: Ill., graph. Darst. |
| ISBN: | 0780311701 |
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| 245 | 1 | 0 | |a Circuits and systems tutorials |c ed.: Chris Toumazou ... |
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| 650 | 4 | |a Electric filters |v Congresses | |
| 650 | 4 | |a Electronic circuits |v Congresses | |
| 650 | 4 | |a Signal processing |v Congresses | |
| 650 | 4 | |a Telecommunication systems |v Congresses | |
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| adam_text | IMAGE 1
CIRCUITS AND SYSTEMS
TLITORIALS
EDITOR
CHRIS TOUMAZOU IMPERIAL COLLEGE LONDON, U. K.
ASSISTANT EDITORS
NICK BATTERSBY NORTHERN TELECOM ONTARIO, CANADA
SONIA PORTA OXFORD BROOKES UNIVERSITY OXFORD, U. K.
IEEE PRESS
THE INSTITUTE OF ELECTRICA! AND ELECTRONICS ENGINEERS, INC., NEW YORK
*
IMAGE 2
CONTENTS
LIST OF CONTRIBUTORS XXV
FOREWORD XXIX
PREFACE XXXI
ACKNOWLEDGMENTS XXXII
INTRODUCTION XXXIII
TUTORIAL 1
1.0 INTRODUCTION TO NONLINEAR SIGNAL PROCESSING 1
C. F. N. COWAN, E. J. COYLE, M. GABBOUJ, V. J. MATHEWS, I. PITAS AND G.
SICURANZA 1.0.1 INTRODUCTION 1
1.0.2 OVERVIEW 1
1.0.3 ORDER STATISTICS BASED SIGNAL PROCESSING 3
1.0.4 POLYNOMIAL SIGNAL PROCESSING TECHNIQUES 3
1.11 WEIGHTED MEDIAN FILTERING - STRIKING ANALOGIES TO FIR FILTERS 5 M.
GABBOUJ ABSTRACT 5
1.11.1 INTRODUCTION 5
1.11.2 MEDIAN AND WEIGHTED MEDIAN FILTERE 6
1.11.2.1 MEDIAN FILTERING 6
(I) DETERMINISTIC PROPERTIES OF MEDIAN FILTERE: ROOT SIGNALS. 6 (II)
STATISTICAL PROPERTIES OF MEDIAN FILTERE 7
1.11.2.2 WEIGHTED MEDIAN FILTERE 8
(I) ANALOGY BETWEEN WM FILTERE AND LINEAR FIR FILTERE 9 1.11.3
PROPERTIES OF WEIGHTED MEDIAN FILTERE 10
1.11.3.1 ROOT PROPERTIES OF WEIGHTED MEDIAN FILTERE 10 1.11.3.2
STATISTICAL PROPERTIES OF WEIGHTED MEDIAN FILTERE 10 1.11.4 OPTIMAL
WEIGHTED MEDIAN FILTERING 12
1.11.4.1 PROBLEM FORMULATION 12
1.11.4.2 OPTIMAL WM FILTERING WITH STRUCTURAL CONSTRAINTS 13 1.11.5
APPLICATIONS OF WEIGHTED MEDIAN FILTERE 14
1.11.5.1 SPEECH SIGNAL PROCESSING 14
1.11.5.2 OPTIMAL WEIGHTED MEDIAN IMAGE FILTERING 16 1.11.6 SUMMARY 17
ACKNOWLEDGEMENTS 17
REFERENCES 17
1.12 STACK FILTERS IN SIGNAL AND IMAGE PROCESSING 22
E. J. COYLE 1.12.1 TWO APPROACHES TO SIGNAL AND IMAGE PROCESSING 22
1.12.2 PROBLEMS AND PERFORMANCE MEASURES IN IMAGE PROCESSING 23 1.12.3
THE REGULARIZATION APPROACH AND STACK FILTERE 24
1.12.4 THE FILTER-CLASS APPROACH AND STACK FILTERE 25
1.12.5 NOTATION AND PRECISE STATEMENT OF STACK FILTER PROPERTIES 27
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1.12.6 MINIMUM MEAN ABSOLUTE ERROR STACK FILTERING 28
1.12.7 COMPUTATIONAL REQUIREMENTS OF STACK FILTERS 29
1.12.8 AN APPLICATION OF STACK FILTERS: NOISE REDUCTION 30
1.12.9 AN APPLICATION OF STACK FILTERS: EDGE DETECTION 30
1.12.10 EDGE DETECTION AND STACK FILTERS 33
1.12.11 THE NONLINEAR PREFILTERING APPROACH TO EDGE DETECTION 34 1.12.12
THE DIFFERENCE OF ESTIMATES APPROACH TO EDGE DETECTION 34 1.12.13
COMPARISONS WITH OTHER APPROACHES 35
1.12.14 CONCLUSIONS AND FURTHER WORK 35
REFERENCES 36
1.13 MULTICHANNEL ORDER STATISTICAL FILTERING 40
I. PITAS
1.13.1 INTRODUCTION 40
1.13.2 MULTIVARIATE DATA ORDERING 40
1.13.3 MULTICHANNEL FILTERS BASED ON VECTOR ORDERING 42
1.13.4 NONLINEAR FILTERS OF DIRECTIONAL DATA 45
1.13.5 DISCUSSION 47
REFERENCES 48
1.21 THEORY AND APPROXIMATION OF POIYNOMIAL FILTERS 50
G. L. SICURANZA ABSTRACT 50
1.21.1 THE CONTINUOUS-TIME CASE 50
1.21.2 THE DISCRETE-TIME CASE 51
1.21.3 PROPERTIES OF VOLTERRA FILTERS 52
1.21.3.1 STNICTURAL PROPERTIES OF THE KERNEIS 52
1.21.3.2 STNICTURAL PROPERTIES OF THE INPUT-OUTPUT RELATIONSHIP.... 53
1.21.3.3 VOLTERRA SERIES EXPANSION FOR MULTIDIMENSIONAL SYSTEMS 54
1.21.4 REALIZATIONS AND APPROXIMATIONS OF POIYNOMIAL FILTERS 55 1.21.5
APPLICATIONS OF POIYNOMIAL FILTERS 56
REFERENCES 57
1.22 ADAPTIVE POIYNOMIAL FILTERS 59
V.J. MATHEWS 1.22.1 INTRODUCTION 59
1.22.2 ADAPTIVE VOLTERRA FILTERS 59
1.22.2.1 LEAST-MEAN-SQUARE (LMS) QUADRATIC FILTERS 59 1.22.2.2 VARIABLE
STEP SIZE ALGORITHMS 60
1.22.2.3 RECURSIVE LEAST-SQUARES (RLS) QUADRATIC FILTERS 61 1.22.2.4 AN
OVERVIEW OF OTHER APPROACHES 62
1.22.3 RECURSIVE NONLINEAR SYSTEMS 62
1.22.3.1 STABILITY OF RECURSIVE SYSTEMS 63
1.22.3.2 ADAPTIVE BILINEAR FILTERS 63
REFERENCES 64
1.23 APPLICATION OF ADAPTIVE VOLTERRA FILTERS TO EQUALIZATION 66
C. F. N. COWAN 1.23.1 INTRODUCTION 66
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1.23.2 ADAPTIVE EQUALIZATION 66
1.23.3 EQUALIZATION AS CLASSIFICATION 67
1.23.4 ADAPTIVE VOLTERRA EQUALIZATION 69
REFERCNCES 70
TUTORIAL 2
2 DESIGN AND APPLICATIONS OF A/D MULTIRATE SIGNAL PROCESSING 71 J. E.
FRANCA AND S. K. MITRA 2.1 AREVIEWOF MULTIRATE CONCEPTS 71
2.1.1 BASIC COMPONENTS 71
2.1.2 POLYPHASE IMPLEMENTATION 73
2.1.3 QUADRATURE-MIRROR FILTER (QMF) BANK 73
2.2 BASIC ASPECTS OF ANALOG MULTIRATE TECHNIQUES 74
2.2.1 INTRODUCTION 74
2.2.2 DIRECT-FORM POLYPHASE HR SC DECIMATORS AND INTERPOLATORS 75
(I) DIRECT-FORM SC DECIMATORS 75
(II) DIRECT-FORM SC INTERPOLATORS 78
2.2.3 ACTIVE-DELAYED BLOCK POLYPHASE FIR SC DECIMATORS 79 2.2.4 DR SC
DECIMATION AND INTERPOLATION BUILDING BLOCKS 82 (I) IIR SC DECIMATORS 82
(II) HR SC INTERPOLATORS 86
2.3 MULTIRATE SYSTEMS FOR HIGH-SELECTIVITY FILTERING 88
2.3.1 INTRODUCTION 88
2.3.2 FREQUENCY TRANSLATION IN SC FILTERE 88
(I) SINGLE-PATH FILTERE 88
(II) N-PATH FILTERE 89
2.3.3 REVIEW OF SC BANDPASS FILTER SYSTEMS 90
(I) GENERAL SYSTEM ARCHITECTURE 90
(II) SP SYSTEMS 90
(III) NP SYSTEMS USING LOWPASS PATH FILTERE 91
(IV) NP SYSTEMS USING HIGHPASS PATH FILTERE 92
2.3.4 NP SYSTEMS USING BANDPASS PATH FILTERE 93
2.3.5 A 20 KHZ 0.48% BANDPASS FILTER SYSTEM 94
(I) ARCHITECTURE 94
(II) EXPERIMENTAL CHARACTERIZATION 95
2.4 MULTIRATE FILTERING FOR HIGH-FREQUENCY FRONT-ENDS 96
2.4.1 DIGITIZATION OF STANDARD VIDEO (CCIR 601) 96
(I) PREDOMINANUEY DIGITAL VIDEO INTERFACE SYSTEM 96 (II) PREDOMINANUEY
ANALOG VIDEO INTERFACE SYSTEM 97 2.4.2 MAGNETIC-DISK READ CHANNELS 98
2.5 MULTIRATE TECHNIQUES FOR DATA CONVERSION 99
2.5.1 GENERALIZED DATA CONVERSION ARCHITECTURE 99
2.5.2 OVERSAMPLING SIGMA-DELTA CONVERTERS 100
2.5.3 QMF-BASED A/D CONVERTERS 101
2.6 CONCLUSIONS 103
REFERENCES 103
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TUTORIAL 3
3.11 MPEG-2. THE MAIN PROFILE 107
J. MORRIS 3.11.1 MPEG-2 -WHATISIT? 107
3.11.2 SCHEDULE AND METHOD OF WORKING 108
3.11.3 REQUIREMENTS 109
3.11.4 WHAT IS STANDARDIZED 109
3.11.5 COMPRESSION METHODS 109
3.11.5.1 COLOUR SAMPLING 110
3.11.5.2 INTERFACE 110
3.11.5.3 OVERVIEW OF THE ALGORITHM 111
3.11.5.4 MOTION COMPENSATION 112
(I) PREDICTION MODES 113
(II) MOTION ESTIMATION 114
(III) MOTION REPRESENTATION 115
3.11.5.5 SPATIAL CODING 115
(I) DCT 115
(II) QUANTIZATION 115
(III) RUN LENGTH CODING AND VLC CODING 116
(IV) CONSTANT AND VARIABLE BIT-RATE CODING AND BUFFERING... 117 3.11.6
ENCODING 118
3.11.7 DECODING 119
3.11.8 CONCLUSION 120
REFERENCES 120
3.12 STANDARDIZATION OF SCALABLE CODING SCHEMES 121
N. D. WELLS AND P. N. TUDOR ABSTRACT 121
3.12.1 INTRODUCTION 121
3.12.2 NON-SCALABLE ALGORITHM 121
3.12.3 SCALABLE SCHEMES 122
3.12.3.1 FREQUENCY SCALABLE 122
3.12.3.2 SPATIAL SCALABLE 126
3.12.3.3 SNR SCALABLE 127
3.12.4 CHROMINANCE SCALABILITY 128
3.12.5 STANDARDS CONVERSION 128
3.12.6 DISCUSSION 129
3.12.7 PERFORMANCE 130
3.12.8 CONCLUSIONS 130
ACKNOWLEDGMENTS 130
REFERENCES 130
3.13 MPEG-2 CODING SCHEMES FOR LOW DELAY REQUIREMENTS 131
G. BJ0NTEGAARD 3.13.1 INTRODUCTION 131
3.13.2 APPLICATIONS REQUIRING LOW DELAY 131
3.13.3 TWO PRINCIPAL TYPESOF DELAY 131
3.13.3.1 CODER TO DECODER DELAY 131
3.13.3.2 DELAY FROM ENTERING A BITSTREAM TO GETTING A
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FUELL QUALITY SIGNAL 132
3.13.4 IDENTIFICATION OF DIFFERENT SOURCES OF DELAY IN MPEG-2 CODING....
133 3.13.4.1 TOTAL DELAY FOR DIFFERENT VERSIONS OF MPEG-2 CODING... 133
3.13.4.2 MODES THAT FULFILL THE LOW DELAY REQUIREMENT OF 150 MS. 134
3.13.4.3 CHANNEL HOPPING DELAY 134
(I) PERFORMANCE LOSS WITH FREQUENT INTRA UPDATE 134 3.13.5 SPECIAL TOOLS
FOR USE IN LOW DELAY 135
3.13.5.1 INTRA SLICE UPDATE 135
3.13.5.2 DUAL PREDICTION 136
3.13.6 CODING PERFORMANCE AT LOW DELAY CODING 136
3.13.7 CONCLUSIONS 137
3.14 MPEG-2 SYSTEMS AND THE TRANSPORT OVER ATM 138
M. T. SUN ABSTRACT 138
3.14.1 INTRODUCTION 138
3.14.2 MPEG-2 SYSTEMS 139
3.14.2.1 ATM 141
3.14.3 TECHNICAL ISSUES 143
3.14.3.1 TIMING RECOVERY 143
3.14.3.2 BIT-ERROR AND CELL-LOSS DETECTION/CORRECTION 143
3.14.3.3 MPEG-2 STREAMS TO ATM CELLS MAPPING 144
3.14.4 SUMMARY 145
ACKNOWLEDGMENT 145
REFERENCES 145
3.21 VLSI ARCHITECTURES FOR MULTIMEDIA AND VIDEO CONFERENCING 147 B.
ACKLAND 3.21.1 INTRODUCTION 147
3.21.2 VIDEO COMPRESSION 148
3.21.2.1 CHROMINANCE SUB-SAMPLING 149
3.21.2.2 TRANSFORM CODING 149
3.21.2.3 FRAME DIFFERENCING 149
3.21.2.4 MOTION COMPENSATION 149
3.21.2.5 INTERPOLATION 150
3.21.2.6 ENTROPY CODING 150
3.21.3 VLSI ARCHITECTURES 152
3.21.3.1 VIDEO SIGNAL PROCESSORS 153
3.21.3.2 BUILDING BLOCK 154
3.21.3.3 MONOLITHIC CODEC 154
3.21.4 AVP 4000 MULTIMEDIA CODEC 154
3.21.4.1 VIDEO ENCODER 155
3.21.4.2 SYSTEM CONTROLLER 158
3.21.4.3 VIDEO DECODER 160
3.21.5 DESIGN CHALLENGES 160
3.21.5.1 ALGORITHMIC MODELLING 162
3.21.5.2 CAD TOOLS AND PROCESSORS 162
3.21.5.3 POWER AND PACKAGING 162
3.21.5.4 SOFTWARE DEVELOPMENT 162
3.21.6 SUMMARY 162
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REFERENCES 163
3.22 VLSI IMPLEMENTATION OF MPEG DECODERS 164
T. FAUTIER 3.22.1 INTRODUCTION 164
3.22.2 OVERVIEW OF MPEG STANDARDS 164
3.22.2.1 MPEG1 164
3.22.2.2 MPEG2 164
3.22.3 REQUIREMENTS FOR MPEG VIDEO DECODING 165
3.22.3.1 GLOBAL ARCHITECTURE 165
3.22.3.2 PROCESSING POWER 165
(I) QUALITATIVE APPROACH 165
(II) QUANTITATIVE APPROACH 166
3.22.3.3 MEMORY BANDWIDTH 167
(I) QUALITATIVE APPROACH 167
(II) QUANTITATIVE APPROACH 168
3.22.4 DIMENSIONING OF THE ARCHITECTURE 169
3.22.4.1 ACCESS TO THE DRAM 169
(I) STRATEGYOFACCESS 169
(II) CACHE STRATEGY 169
3.22.4.2 PROCESSING UNITS 169
(I) DATAPARSING 169
(II) START CODE DETECTION 170
(III) VLD 170
(IV) INVERSE QUANTIZATION 171
(V) INVERSE DCT 171
(VI) PREDICTION 171
(VII) DISPLAY 171
(VIII) MEMORY MANAGEMENT UNIT 172
3.22.4.3 CLOCK FREQUENCY 172
3.22.5 CONCLUSION 172
REFERENCES 172
3.31 OBJECT-BASED ANALYSIS-SYNTHESIS CODING 173
H. G. MUSMANN ABSTRACT 173
3.31.1 INTRODUCTION 173
3.31.2 GENERAL STRUCTURE OF AN OBJECT-ORIENTED ANALYSIS-SYNTHESIS
CODER.. 174 3.31.3 PARAMETER SETS AND PARAMETER CODING 175
3.31.4 CODING EFFICIENCY 177
3.31.5 CONCLUSION 179
REFERENCES 179
3.32 MODEL-BASED IMAGE CODING 180
K. AIZAWA 3.32.1 INTRODUCTION 180
3.32.2 IMAGE CODING SCHEMES AND THEIR ASSOCIATED IMAGE MODEIS 180 3.32.3
3-D MODEL-BASED CODING FOR FACIAL IMAGES 181
3.32.3.1 MODELLING A PERSON S FACE 182
3.32.3.2 SYNTHESIS OF FACIAL MOVEMENTS 183
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3.32.3.3 ANALYSISOFFACIALIMAGES 184
3.32.3.4 IMPLEMENTATIONS AND APPLICATIONS 185
3.32.4 2-D DEFORMABLE TRIANGULAER MODEL FOR ADVANCED MOTION COMPENSATION
185
3.32.4.1 2-D DEFORMABLE TRIANGLE BASED MOTION COMPENSATION 185
3.32.4.2 CODING AT VERY LOW BIT RATES 188
(I) THE NUMBER OF MOTION VECTORS 188
(II) CODING AT 16 KB/S 188
3.32.4.3 HYBRID OF 3-D AND 2-D MODEL-BASED CODING SCHEMES... 189 3.32.5
REMAINING PROBLEMS FOR 3-D MODEL BASED CODING 190
3.32.5.1 MODELLING OBJECTS 190
3.32.5.2 EVALUATION PROBLEM 191
REFERENCES 191
TUTORIAL 4
4.1 THEORY OF Z-A ANALOG TO DIGITAL CONVERTER 195
B. LEUNG TERMINOLOGY 195
4.1.1 INTRODUCTION 196
4.1.2 NYQUIST RATE A/D CONVERTERS 196
4.1.2.1 CLASSIFICATIONS 196
4.1.2.2 LIMITATIONS OF NYQUIST RATE A/D CONVERTERS 197
(I) ANTI-ALIASING 197
(II) QUANTIZATION 198
4.1.3 MODULATORS FOR OVERSAMPLED A/D CONVERSION 199
4.1.3.1 PREDICTIVE CONVERTER 199
4.1.3.2 NOISE SHAPING CONVERTOR 199
4.1.3.3 COMPARISONS 200
4.1.4 SIGMA-DELTA MODULATOR ARCHITECTURES 201
4.1.4.1 FIRST AND SECOND ORDER SIGMA-DELTA MODULATORS 201 (I) PRINCIPLE
OF OPERATION 201
(II) SECOND-ORDER SIGMA-DELTA MODULATOR 203
(III) PATTERN NOISE 205
4.1.4.2 INTERPOLATIVE MODULATORS 208
4.1.4.3 CASCADED (MASH) ARCHITECTURE 209
4.1.4.4 SINGLE-PATH MODULATOR WITH LOCAL FEEDBACK LOOP 211 (I)
CANCELLATION CIRCUITRY 212
(II) SELECTION OF LOOP FILTER COEFFICIENTS 213
4.1.4.5 MULTI-BIT SIGMA-DELTA MODULATORS 213
4.1.5 DECIMATION FILTERS 215
4.1.5.1 SINE DEEIMATORS 216
4.1.5.2 FIR DECIMATION FILTERS BASED ON QUADRATIC PROGRAMMING.. 217
4.1.5.3 POLYPHASE HR DECIMATION FILTER BASED ON OPTIMIZATION.... 218
REFERENCES 219
4.2 DELTA-SIGMA D/A CONVERTERS 224
G. C. TEMES ACKNOWLEDGEMENT 234
IMAGE 9
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REFERENCES 234
4 .3 DESIGN ASPECTS OF HIGH-ORDER DELTA-SIGMA A/D CONVERTERS 235
R. ADAMS 4.3.1 INTRODUCTION 235
4.3.2 MOTIVATION FOR USING HIGH-ORDER SINGLE-BIT LOOPS 235
4.3.2.1 LOW-ORDER SINGLE-LOOP SINGLE-BIT 235
4.3.2.2 HIGH-ORDER SINGLE-LOOP SINGLE-BIT 235
4.3.2.3 MULTI-LOOP CASCADE 236
4.3.2.4 MULTI-BIT 236
4.3.3 DESIGN CHOICES. SC OR ACTIVE-RC? 237
4.3.3.1 ADVANTAGES AND DISADVANTAGES OF SC AND ACTIVE-RC MODULATORS 237
(I) ADVANTAGES 237
(II) DISADVANTAGES 237
4.3.4 STABILITY 239
4.3.4.1 STABILITY AND THE UNCONTROLLED INPUT SIGNAL 240
4.3.5 TRANSIENT INPUT SIGNALS AND STABILITY 240
4.3.6 CHOICES FOR THE NTF 241
4.3.6.1 NTH-ORDER PURE DIFFERENTIATION 241
4.3.6.2 BUTTERWORTH HIGH-PASS RESPONSE 243
4.3.6.3 COMPLEX ZEROS ON THE UNIT CIRCLE 243
4.3.7 COMPARISON OF LOOP TOPOLOGIES 244
4.3.7.1 CHAIN OF INTEGRATORS WITH WEIGHTED FEED-FORWARD SUMMATION 245
4.3.7.2 CHAIN OF INTEGRATORS WITH FEED-FORWARD SUMMATION AND LOCAL
RESONATOR FEEDBACKS 246
4.3.7.3 CHAIN OF INTEGRATORS WITH DISTRIBUTED FEEDBACK 247
4.3.7.4 CHAIN OF INTEGRATORS WITH DISTRIBUTED FEEDBACK, DISTRIBUTED
FEEDFORWARD INPUTS 248
4.3.7.5 ERROR-FEEDBACK ONLY 250
4.3.8 LOOP FILTER DESIGN EXAMPLE 250
4.3.9 NON-LINEAR GLOBAL STABILIZATION TECHNIQUES 252
4.3.10 PRACTICAL MEASURES FOR PREVENTING IDLE TONES 254
4.3.11 PRACTICAL IMPLEMENTATION OF A STEREO DELTA-SIGMA 18-BIT ADC IC...
255 4.3.12 NOISE-SHAPING MODULATOR IC 255
4.3.13 SWITCHED-CAPACITOR LOOP FILTER DESIGN 256
4.3.14 CIRCUIT NOISE CONSIDERATIONS 257
4.3.15 STABILIZATION USING INTEGRATOR RESET 258
4.3.16 OP-AMP DESIGN 258
4.3.17 RESULTS AND COMMENTS 259
ACKNOWLEDGEMENTS 260
REFERENCES 260
TUTORIAL 5
5 .1 MOBILE TELEPHONY 2 61
T. ALI-VEHMAS AND Y. NEUVO 5.1.1 INTRODUCTION 261
5.1.2 USAGE 263
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5.1.3 EVOLUTIONS AND REVOLUTIONS 264
5.1.4 BASIC CONCEPTS 264
5.2 DIGITAL SIGNAL PROCESSING IN MOBILE TELEPHONY 266
N. COURTIS ABSTRACT 266
5.2.1 INTRODUCTION 266
5.2.2 THE ADVERSE RADIO CHANNEL 267
5.2.3 THE TRANSMITTER 268
5.2.3.1 SPEECH CODING 268
5.2.3.2 CHANNEL CODING 270
5.2.3.3 BURST ASSEMBLING 271
5.2.3.4 MODULAUEON 271
5.2.4 RECEIVER ARCHITECTURES 273
5.2.4.1 NON-LINEAR RECEIVERS 273
5.2.4.2 LINEAR RECEIVERS 275
5.2.4.3 BIT RECOVERY 275
5.2.4.4 DIVERSITY 276
5.2.4.5 DECODING 277
5.2.5 IMPLEMENTATION ISSUES 277
ACKNOWLEDGMENTS 277
REFERENCES 278
5.3 HIGH SPEED DSP LOW POWER CIRCUITS FOR FUTURE MOBILE PHONE 279 M.
YAMASHINA 5.3.1 INTRODUCTION ,...279
5.3.2 DSPS FOR FUTURE MOBILE SYSTEMS 280
5.3.3 PARALLEL OR HIGH SPEED? 281
5.3.3.1 IS PARALLEL PROCESSING PRACTICAL FOR LOW-POWER DSPS? 281 5.3.3.2
HOW TO PRODUCE HIGH SPEED DSPS 282
(I) REDUCTION OF THE CRITICAL PATH GATE NUMBER 282
(II) INCREASE OF TRANSISTOR CURRENT 283
5.3.3.3 IS A DEVELOPED HIGH SPEED DSP PRACTICAL FOR MOBILE SYSTEMS? 283
5.3.4 LOW POWER CIRCUITS FOR HIGH SPEED DSPS 284
5.3.5 SUMMARY 286
REFERENCES 286
TUTORIAL 6
6.1 BASIC CONCEPTS ON NONLINEAR DYNAMICS AND CHAOS 289
M. P. KENNEDY 6.1.1 ELECTRICAL AND ELECTRONIC CIRCUITS AS DYNAMICAL
SYSTEMS 289 6.1.1.1 CONTINUOUS-TIME DYNAMICAL SYSTEMS 289
6.1.1.2 AUTONOMOUS CONTINUOUS-TIME DYNAMICAL SYSTEMS 290 6.1.1.3
NON-AUTONOMOUS DYNAMICAL SYSTEMS 291
6.1.1.4 DISCRETE-TIME DYNAMICAL SYSTEM 291
6.1.2 CLASSIFICATION AND UNIQUENESS OF STEADY-STATE BEHAVIOURS 293
6.1.2.1 EQUILIBRIUM POINT 294
6.1.2.2 PERIODIC STEADY-STATE 296
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6.1.2.3 SUBHARMONIC PERIODIC STEADY-STATE 296
6.1.2.4 QUASIPERIODIC STEADY-STATE 296
6.1.2.5 CHAOTIC STEADY-STATE 297
6.1.3 STABILITY OF STEADY-STATE TRAJECTORIES 298
6.1.3.1 STABILITY OF EQUILIBRIUM POINTS 298
6.1.3.2 EIGENVALUES 299
6.1.3.3 DISCRETE-TIME SYSTEMS 299
6.1.3.4 EIGENVECTORS, EIGENSPACES, STABLE AND UNSTABLE MANIFOLDS .299
6.1.3.5 STABILITY OF LIMIT CYCLES 300
6.1.3.6 POINCARE SECTIONS 301
6.1.4 HORSESHOES ANDCHAOS 302
6.1.4.1 CHAOS IN THE SENSE OF SHIL NIKOV 303
6.1.4.2 LYAPUNOV EXPONENTS 305
6.1.4.3 LYAPUNOV EXPONENTS OF STEADY-STATE SOLUTIONS 306 6.1.5
STRUCTURAL STABILITY AND BIFURCATIONS 307
6.1.5.1 BIFURCATION TYPES 309
(I) HOPF BIFURCATION 309
(II) SADDLE-NODE BIFURCATION 309
(III) PERIOD-DOUBLING BIFURCATION 309
6.1.5.2 ROUTES TOCHAOS 309
6.1.5.3 PERIOD-DOUBLING ROUTE TO CHAOS 311
6.1.5.4 INTERMITTENCY ROUTE TO CHAOS 311
6.1.5.5 QUASIPERIODIC (TORUS BREAKDOWN) ROUTE TO CHAOS 312 6.1.5.6
BIFURCATION DIAGRAMS 312
REFERENCES 312
6.2 SYNCHRONIZATION PRINCIPLES AND APPLICATIONS 314
M. HASLER 6.2.1 INTRODUCTION 314
6.2.2 SYNCRONIZATION BY DECOMPOSITION INTO SUBSYSTEMS 315
6.2.3 SYNCHRONIZATION BY LINEAR FEEDBACK 319
6.2.4 SYNCHRONIZATION BY THE INVERSE SYSTEM 321
6.2.5 TRANSMISSION WITH A CHAOTIC CARRIER SIGNAL 323
6.2.6 CHAOTIC MASKING 323
6.2.7 CHAOTIC SWITCHING 324
6.2.8 DIRECT CHAOTIC MODULATION 326
6.2.9 CONCLUSION 326
REFERENCES 326
6.3 CONTROL CONCEPTS AND APPLICATIONS 328
M. J. OGORZALEK ABSTRACT 328
6.3.1 INTRODUCTION 328
6.3.2 SIMPLE TECHNIQUES FOR SUPPRESSING CHAOTIC OSCIUATIONS 329 6.3.2.1
PARAMETER VARIATION TECHNIQUE 329
6.3.2.2 SHOCK ABSORBER CONCEPT 329
6.3.2.3 PROPERTIES OF THE SIMPLEST METHODS FOR SUPPRESSION OF CHAOTIC
OSCIUATIONS 330
6.3.3 EXTERNA! PERTURBATION TECHNIQUES 330
IMAGE 12
XVII
6.3.3.1 ENTRAINMENT - OPEN LOOP CONTROL 330
6.3.3.2 PROPERTIES OF THE ENTRAINMENT METHOD 331
6.3.3.3 WEAK PERIODIC PERTURBATION 331
6.3.4 CONTROL ENGINEERING APPROACH 331
6.3.4.1 LINEAR FEEDBACK CONTROL 332
6.3.4.2 PROPERTIES OF THE LINEAR FEEDBACK METHOD 332
6.3.4.3 TIME - DELAY FEEDBACK CONTROL (PYRAGAS METHOD) 333 6.3.4.4
PROPERTIES OF THE DELAY FEEDBACK CONTROL METHOD 333 6.3.5 CONTROL IN
TERMS OF STABILISING UNSTABLE PERIODIC ORBITS. OTT-GREBOGI-YORKE
APPROACH (OGY) 333
6.3.5.1 PROPERTIES OF THE OGY TECHNIQUE 6.3.5.2 SAMPLED INPUT WAVEFORM
METHOD 336
6.3.5.3 PROPERTIES OF THE SAMPLED INPUT CONTROL METHOD 336 6.3.5.4
ELECTRONIC CHAOS CONTROLLERS- OPF 336
6.3.5.5 PROPERTIES OF THE OPF METHOD 336
6.3.6 CONTROLLING SYSTEMS TOWARDS CHAOTIC STATES- SYNCHRONISATION AS A
CONTROL PROBLEM 337
6.3.7 DISCUSSION 337
ACKNOWLEDGEMENT 338
REFERENCES 338
6.4 FRACTALS IN SIGNAL PROCESSING 341
A. JACQUIN 6.4.1 INTRODUCTION 341
6.4.2 FRACTALS AND CHAOS 342
6.4.2.1 WHAT IS A FRACTAL OBJECT ? 342
(I) TWO SIMPLE EXAMPLES OF SELF-SIMILAR FRACTALS 6.4.2.2 FRACTALS AND
CHAOS IN THE REAL WORLD 343
(I) FRACTAL OBJECTS IN NATURE 343
(II) CHAOTIC DYNAMICAL SYSTEMS 345
(III) CHAOS IN THE REAL WORLD 347
6.4.3 MODELLING REAL WORLD OBJECTS WITH FRACTALS 347
6.4.3.1 ITERATED FUNCTION SYSTEMS THEORY 348
(I) FRACTALS AS ATTRACTORS OF ITERATED FUNCTION SYSTEMS 348 (II) THE
INVERSE PROBLEM OF MODELLING AN OBJECT AS THEATTRACTOROFANIFS 349
(III) SYNTHETIC NATURAL SCENES 350
(IV) PIECE-WISE SELF-TRANSFORMABILITY, RCCURRENT IFS 350 6.4.3.2
RECURRENT IFS THEORY FOR CONTOUR MODELLING 352
(I) FRACTAL CURVES AS ATTRACTORS OF RECURRENT IFSS 352
(II) CONTOUR MODELLING 353
6.4.3.3 FRACTAL BLOCK CODING OF DIGITAL IMAGES 357
(I) DECODING/RECONSTRUCTION 358
(II) EXTENSIONS 358
6.4.4 CONCLUSION 360
REFERENCES 360
IMAGE 13
XV111
TUTORIAL 7
7 THE FUNDAMENTALS OF ANALOG MICROPOWER DESIGN 365
E. VITTOZ 7.1 INTRODUCTION 365
7.2 DEVICES FOR LOW-VOLTAGE AND VERY LOW-CURRENT 365
7.3 CIRCUIT LIMITATIONS AND SOLUTIONS 368
7.4 CONCLUSION 371
REFERENCES 371
TUTORIAL 8
8 LOW POWER DIGITAL DESIGN 373
J. M. RABAEY 8.1 INTRODUCTION 373
8.2 SOURCES OF POWER DISSIPATION IN DIGITAL CIRCUITS 374
8.2.1 DYNAMIC POWER DISSIPATION 374
8.2.2 GLITCHING IN STATIC CMOS CIRCUITS 375
8.2.3 SHORT-CIRCUIT CURRENTS IN STATIC CMOS CIRCUITS 377
8.3 LOW POWER CMOS DESIGN 378
8.3.1 REDUCING THE SUPPLY VOLTAGE 378
8.3.2 REDUCING THE EFFECTIVE CAPACITANCE 382
8.4 ACASE STUDY 385
8.5 SUMMARY 385
REFERENCES 386
TUTORIAL 9
9.1 TAKING THE MYSTERY OUT OF RF DESIGN 387
B. GILBERT 9.1.1 INTRODUCTION 387
9.1.2 THE MYSTERY OF TERMINOLOGY 389
9.1.3 MYSTERIES OF MEASUREMENT 390
9.1.4 MYSTERIOUS BEHAVIOUR 392
9.2 DIRECT DIGITAL SYNTHESIS 393
P. SAUL 9.2.1 INTRODUCTION 393
9.2.2 THEMATHEMATICSOFDDS 394
9.2.3 DDS SYSTEMS 397
9.2.3.1 THE SPURIOUS CONTENT 399
9.2.4 CONCLUSIONS 403
REFERENCES 404
9.3 RF DESIGN IN GAAS AND BICMOS 405
P. MOLE AND K. SEARLE 9.3.1 INTRODUCTION 405
9.3.2 RF DESIGN 405
9.3.2.1 WHATISRF? 405
9.3.2.2 THE UNEXPECTED PARASITIC COMPONENT 405
9.3.2.3 MATCHING CIRCUIT IMPEDANCES 407
IMAGE 14
XIX
9.3.2.4 PACKAGING 410
9.3.2.5 FEEDBACK 411
9.3.2.6 BALANCED OR SINGLE-ENDED 412
9.3.2.7 MEASUREMENT AND TESTING 412
9.3.2.8 INTEGRATION OF RF CIRCUITRY 413
9.3.3 DESIGNING RF CIRCUITRY IN A SILICON BICMOS TECHNOLOGY 413 9.3.3.1
WHAT A BICMOS TECHNOLOGY HAS TO OFFER 413
9.3.3.2 DESIGN WITH BIPOLAR TRANSISTORS AT RF FREQUENCIES 414 9.3.3.3
THE DESIGN OF A BIPOLAR LNA GAIN STAGE 416
9.3.4 GAAS DESIGN 418
9.3.4.1 DESIGN ROUTE 418
9.3.4.2 WHERE HAS GAAS BEEN? 418
9.3.4.3 TRANSISTORS 418
9.3.4.4 TYPICAL DESIGN 419
9.3.4.5 OSCILLATORS 422
9.3.4.6 CONSTRUCTION 422
9.3.4.7 CADTOOLS 422
REFERENCES 423
FURTHER READING 423
INTRODUCTION TO SPREAD SPECTRUM TECHNIQUES 424
P. E. CHADWICK 9.4.1 INTRODUCTION 424
9.4.2 WHAT IS SPREAD SPECTRUM ? 424
9.4.2.1 TYPES OF SPREAD SPECTRUM 424
(I) FREQUENCY HOPPING SYSTEMS 424
(II) DIRECT SEQUENCE SYSTEMS 425
(III) CHIRP SYSTEMS 426
9.4.2.2 SPREADING GAIN 427
9.4.3 WHY SPREAD SPECTRUM ? 427
9.4.3.1 APPLICATIONS 428
9.4.4 THE NEAR-FAR PROBLEM, JAMMING AND INTERFERENCE 428
9.4.4.1 DIRECT SEQUENCE SYSTEMS 429
9.4.4.2 FREQUENCY HOPPING SYSTEMS 429
9.4.4.3 JAMMING 429
(I) MUTUAL JAMMING BY DS AND FH SYSTEMS 430
(II) JAMMING OF NARROW BAND SYSTEMS BY FH AND DS SYSTEMS 430
9.4.5 SPECIALISED EQUIPMENT REQUIREMENTS 431
9.4.6 CODING SEQUENCES 431
9.4.7 CONCLUSION 432
REFERENCES 432
TAKING THE MYSTERY OUT OF RF DESIGN: OBEY THE LAW ! 433
J. BRYANT 9.5.1 INTRODUCTION 433
9.5.2 RESISTORS 434
9.5.3 CAPACITORS 436
9.5.4 INDUCTORS 439
9.5.5 GROUNDS 441
IMAGE 15
XX
9.5.6 DECOUPLING 444
9.5.7 CONCLUSION 446
9.6 RF RECEIVERS FOR CELLULAR TELEPHONE BASE STATIONS 448
J. D. RHODES ABSTRACT 448
9.6.1 UK 900 MHZ 448
9.6.2 USA 800 MHZ 455
9.6.3 CONCLUSIONS 458
ACKNOWLEDGEMENTS 458
TUTORIAL 10. PART 1
10.1 SWITCHED-CURRENT CIRCUITS AND SYSTEMS 459
C. TOUMAZOU AND E. G. SAETHER 10.1.1 INTRODUCTION 459
10.1.2 THE SWITCHED-CURRENT APPROACH 460
10.1.3 SI ZA MODULATOR BUILDING BLOCKS IN CMOS TECHNOLOGY 460 10.1.3.1
SI MEMORY CELL 461
10.1.3.2 SWITCHED-CURRENT INTEGRATOR 464
10.1.4 CMOSCURRENT-COMPARATOR/QUANTISER 464
10.1.5 SINGLE BIT CURRENT-MODE D/A CONVERTER 465
10.1.6 CMOS SI ZA MODULATOR 466
10.1.6.1 SI ZA MODULATOR PERFORMANCE.. 467
10.1.7 SWITCHED-CURRENT ZA BUILDING BLOCKS IN GAAS TECHNOLOGY 468
10.1.7.1 GAAS SWITCHED-CURRENT INTEGRATOR 469
10.1.7.2 ONE-BIT GAAS VOLTAGE COMPARATOR 470
10.1.7.3 ONE-BIT GAAS D/A CONVERTER 471
10.1.7.4 FIRST ORDER MODULATOR 471
10.1.8 ENHANCED CMOS MEMORY CELL DEVELOPMENT 472
10.1.8.1 N-STEP HIGH PRECISION MEMORY CELL (S N I) SCHEME 473 10.1.8.2
CMOS CLASS AB CELL 475
10.1.9 ENHANCED GAAS MEMORY CELL DEVELOPMENT 475
10.1.9.1 GAAS SI MEMORY CELL 475
10.1.9.2 SECOND GENERATION TWO-STEP GAAS S 2 I CELL 476
10.1.9.3 GENERALISED SECOND GENERATION GAAS INTEGRATOR 477 10.1.9.4
SIMULATION RESULTS 478
10.1.10 SOME USEFUL TIPS BEFORE TESTING SI CELLS 479
10.1.10.1 APPLYING INPUT SIGNALS 479
10.1.10.2 CANCELLATIONOFTHEEFFECTOFCP 480
10.1.10.3 MEASURING THE OUTPUT SIGNAL 481
10.1.11 CAD TOOLS AND SIMULATION RESULTS 482
10.1.11.1 ABOUT SI SIMULATIONS 482
10.1.11.2 SIMULATION OFS 2 I CELL 483
(I) CLOCK SCHEME AND CLOCK SIGNALS 483
(II) A ONE TRANSISTOR SETTLING PROBLEM 483
10.1.12 CONCLUSIONS 484
ACKNOWLEDGEMENTS 485
REFERENCES 485
IMAGE 16
XXI
10.2 ANALYSIS AND DESIGN OF SPEED AND DYNAMIC RANGE IN SI CELLS 487
P. SHAH AND C. TOUMAZOU 10.2.1 INTRODUCTION 487
10.2.2 FUNDAMENTAL CHARACTERISTICS OF SWITCHED-CURRENT MEMORY CELLS....
487 10.2.3 DESIGNING FOR A SPECIFIC SPEED AND DYNAMIC RANGE-EXAMPLE 491
10.2.4 SPEED-DYNAMIC RAENGE TRADE-OFF BY FEEDBACK AMPLIFICATION OR
ATTENUATION 496
10.2.5 USING AMPLIFICATION OR ATTENUATION IN CONNECTION WITH THE S 2 I
CELL 499
10.2.6 A TWO-STEP FEEDBACK VOLTAGE ATTENUATION TECHNIQUE 501
10.2.7 DESIGN EXAMPLE 503
10.2.8 CONCLUSION 507
REFERENCES 507
10.2.A ALTERNATIVE DEFINITION FOR INTRINSIC DYNAMIC RAENGE 508
10.2.B SPEED AND DYNAMIC RAENGE FOR MEMORY CELLS WITH BIAS 510 10.2.C
SPEED AND DYNAMIC RAENGE FOR S^I CELLS WITH AMPLIFYING OR ATTENUATING
FEEDBACK 512
10.3 SWITCHED-CURRENT DATA CONVERTERS 514
G. W. ROBERTS 10.3.1 INTRODUCTION 514
10.3.2 PRINCIPLES OF DATA CONVERSION 514
10.3.2.1 NYQUIST-RATE CONVERTERS 514
(I) DIGITAL-TO-ANALOG CONVERSION 514
(II) ANALOG-TO-DIGITAL CONVERSION 515
10.3.2.2 OVERSAMPLING NOISE-SHAPING CONVERTERS 518
10.3.3 DATA CONVERTER ALGORITHMS 519
10.3.3.1 NYQUIST-RATE D/A CONVERTERS 519
10.3.3.2 NYQUIST-RATE A/D CONVERTERS 523
10.3.3.3 OVERSAMPLING NOISE-SHAPING DATA CONVERTERS 526 10.3.4 SI
BUILDING BLOCKS 527
10.3.4.1 THE CURRENT MEMORY CELL 528
10.3.4.2 SLDELAYCELL 529
10.3.4.3 SI INTEGRATOR CIRCUIT 529
10.3.4.4 SCALING CIRCUITS 530
(I) MULTIPLY-BY-TWO CIRCUIT 530
(II) DIVIDE-BY-TWO CIRCUIT 531
10.3.4.5 CURRENT COMPARATOR CIRCUIT 533
10.3.4.6 ONE-BIT D/A CIRCUIT 533
10.3.5 SI CIRCUIT EXAMPLES.... 533
10.3.5.1 ALGORITHMIC D/A CONVERTER 533
10.3.5.2 ALGORITHMIC A/D CONVERTER 534
10.3.5.3 NOISE-SHAPING A/D CIRCUIT 535
10.3.6 CONCLUSION 535
REFERENCES 535
10.4 SWITCHED-CURRENT CELLULAR NONLINEAR NETWORKS 537
A. RODRIGUEZ-VAZQUEZ 10.4.1 SUMMARY 537
ACKNOWLEDGMENTS 538
IMAGE 17
XX11
REFERENCES 538
10.5 ANALYSIS OF SWITCHED-CURRENT FILTERS 542
A. C. MOREL RAEO DE QUEIROZ 10.5.1 INTRODUCTION 542
10.5.2 SIGNALS IN SWITCHED-CURRENT ALTERS 542
10.5.3 Z-DOMAIN ANALYSIS OF IDEAL SWITCHED-CURRENT FILTERS 543
10.5.4 LINEARIZED MODELLING OF SWITCHED-CURRENT CIRCUITS 544
10.5.5 Z-DOMAIN NODAL ANALYSIS OF SWITCHED-CURRENT FILTERS 546 10.5.6
EXAMPLE OF UTILIZATION OF THE ASIZ PROGRAM 548
10.5.7 CONCLUSIONS 549
REFERENCES 549
10.6 CURRENT MONITORING FOR TEST 551
K. R. ECKERSHALL, G. E. TAYLOR, I. M. BELL AND C. TOUMAZOU 10.6.1
INTRODUCTION 551
10.6.2 TESTING MIXED SIGNAL CIRCUITS 552
10.6.3 TEST SOLUTIONS 552
10.6.4 SUPPLY CURRENT MONITORING 553
10.6.4.1 BACKGROUND 553
10.6.4.2 APPLICATION TO MIXED SIGNAL DEVICES 554
10.6.4.3 SIMULATION RESULTS 554
10.6.5 BUILT-IN CURRENT SENSING 559
10.6.6 TESTING SWITCHED-CURRENT CELLS 560
10.6.6.1 TESTPATTERNS 560
10.6.6.2 CIRCUIT EXAMPLES 560
10.6.6.3 SIMULATION RESULTS 561
10.6.7 BUILT IN SEIF TEST FOR SI CELLS 562
10.6.7.1 FUNCTIONAL INVERSION TESTCIRCUIT 563
10.6.7.2 FAULT COVERAGE 564
10.6.8 CONCLUSIONS 566
ACKNOWLEDGEMENT 566
REFERENCES 566
TUTORIAL 10. PART 2
11.1 CURRENT-CONVEYOR BASICS AND APPLICATIONS 569
J. LIDGEY AND C. TOUMAZOU 11.1.1 INTRODUCTION 569
11.1.2 BACKGROUND 569
11.1.3 AMPLIFIERS BUILT WITH CURRENT-CONVEYORS 570
11.1.4 ANALOG COMPUTATION 573
11.1.5 IMPEDANCE CONVERSION 574
11.1.5.1 GROUNDED NEGATIVE IMPEDANCE CONVERTERS (NIC) 574 11.1.5.2
GROUNDED GENERALISED IMPEDANCE CONVERTER (GIC) 574 11.1.5.3 FLOATING
NEGATIVE IMPEDANCE CONVERTER 576
11.1.5.4 FLOATING GENERALISED IMPEDANCE CONVERTER 576
11.1.6 FILTERS 577
11.1.7 THE IDEAL TRANSISTOR AND THE CURRENL-CONVEYOR 580
11.1.8 SUPPLY-CURRENT SENSING, CURRENT-FEEDBACK OP-AMPS AND THE CCII.
581
IMAGE 18
XXU1
11.1.9 CCIIOL CURRENT-CONVEYOR 582
11.1.10 IA AND PFWR APPLICATION EXAMPLES OF THE CCIIOL 582
11.1.10.1 CCIIOL INSTRUMENTATION AMPLIFIER 582
11.1.10.2 CCIIOL PRECISION FULL-WAVE RECTIFIER 583
11.1.11 THE FUTURE OF THE CURRENT-CONVEYOR 585
ACKNOWLEDGEMENTS 585
REFERENCES 585
11.2 PRACTICAL INTEGRATED CURRENT-CONVEYORS 588
A. PAYNE AND C. TOUMAZOU 11.2.1 INTRODUCTION 588
11.2.2 THE CURRENT-MODE/VOLTAGE-MODE DILEMMA 588
11.2.3 FIRST GENERATION CURRENT-CONVEYORS 590
11.2.4 SECOND GENERATION CURRENT-CONVEYORS 591
11.2.5 INPUT BIAS-CURRENT SCALING 594
11.2.6 LOCAL NEGATIVE FEEDBACK 595
11.2.7 A CLOSED-LOOP CURRENT-CONVEYOR 596
11.2.8 A GENERAL PURPOSE DUAL CURRENT-CONVEYOR 599
11.2.9 CONCLUSIONS 600
REFERENCES 600
11.3 COMMERCIAL APPLICATIONS OF THE CURRENT-CONVEYOR 601
D. G. WADSWORTH 11.3.1 INTRODUCTION 601
11.3.2 VISTA FAMILY OF TELEPHONE SETS 602
11.3.2.1 VISTA ANALOG ASIC 603
(I) SHUNT REGULATOR 603
(II) SERIES REGULATOR 604
(III) TRANSMIT OUTPUT STAGE 605
11.3.2.2 ELECTRONIC SWITCH ASIC 605
11.3.3 DIGITAL AUDIO HI-FI APPLICATIONS 607
11.3.3.1 SENTEC DIANA AUDIO DAC 608
11.3.3.2 PA630 CURRENT-CONVEYOR IC 610
11.3.3.3 DIANA ANALOG ARCHITECTURE 610
11.3.3.4 ACCURATE CURRENT CONVEYOR TOPOLOGY 611
11.3.4 CONCLUSIONS 614
REFERENCES 614
11.4 CURRENT-MODE OSCILLATORS 616
S. POOKAIYAUDOM 11.4.1 INTRODUCTION 616
11.4.2 CURRENT-MODE BUILDING-BLOCKS 616
11.4.3 FUNDAMENTAL OPERATIONS IN CURRENT-MODE CIRCUITS 618
11.4.4 BASIC THEORYOFCMOS 619
11.4.4.1 EXAMPLEL 620
11.4.4.2 EXAMPLE 2 621
11.4.5 APPROACHES TO THE INVENTION OF NEW CMOS 622
11.4.6 SOME DESIRABLE OSCILLATOR PROPERTIES 623
11.4.7 AUTOMATIC AMPLITUDE CONTROL (AAC) 623
IMAGE 19
XXIV
11.4.8 EXAMPLES OF CMOS 624
11.4.8.1 CURRENT-MIRROR PHASE-SHIFTER CMO 624
11.4.8.2 RC CURRENT-MIRROR CMO 625
11.4.8.3 DYNAMIC RESISTANCE CONTROLLED CMO 626
11.4.8.4 CURRENT-CONVEYOR CMO 627
11.4.8.5 UNITY-GAIN CURRENT-MIRROR CMO 628
11.4.8.6 LC-CMO 629
11.4.8.7 CRYSTAL CONTROLLED CMOS 630
11.4.9 CONCLUSIONS 630
REFERENCES 630
11.5 CMOS CURRENT-CONVEYORS 632
E. BRUUN 11.5.1 INTRODUCTION 632
11.5.2 BASIC CMOS IMPLEMENTATIONS 632
11.5.3 IMPROVED CONFIGURATIONS 634
11.5.4 CONFIGURATIONS WITH FEEDBACK 637
11.5.5 CONCLUSION 640
REFERENCES 640
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| publisher | IEEE Press |
| record_format | marc |
| spelling | Circuits and systems tutorials ed.: Chris Toumazou ... New York IEEE Press 1996 XXXVIII, 659 S.: Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Electric filters Congresses Electronic circuits Congresses Signal processing Congresses Telecommunication systems Congresses Digitale Signalverarbeitung (DE-588)4113314-6 gnd rswk-swf (DE-588)1071861417 Konferenzschrift gnd-content Digitale Signalverarbeitung (DE-588)4113314-6 s DE-604 Toumazou, Chris Sonstige oth GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007425603&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Circuits and systems tutorials Electric filters Congresses Electronic circuits Congresses Signal processing Congresses Telecommunication systems Congresses Digitale Signalverarbeitung (DE-588)4113314-6 gnd |
| subject_GND | (DE-588)4113314-6 (DE-588)1071861417 |
| title | Circuits and systems tutorials |
| title_auth | Circuits and systems tutorials |
| title_exact_search | Circuits and systems tutorials |
| title_full | Circuits and systems tutorials ed.: Chris Toumazou ... |
| title_fullStr | Circuits and systems tutorials ed.: Chris Toumazou ... |
| title_full_unstemmed | Circuits and systems tutorials ed.: Chris Toumazou ... |
| title_short | Circuits and systems tutorials |
| title_sort | circuits and systems tutorials |
| topic | Electric filters Congresses Electronic circuits Congresses Signal processing Congresses Telecommunication systems Congresses Digitale Signalverarbeitung (DE-588)4113314-6 gnd |
| topic_facet | Electric filters Congresses Electronic circuits Congresses Signal processing Congresses Telecommunication systems Congresses Digitale Signalverarbeitung Konferenzschrift |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007425603&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT toumazouchris circuitsandsystemstutorials |