Parallel logic-level simulation system on a distributed memory machine:
Abstract: "We have just constructed a parallel logic-level simulation system based on Virtual Time. It was implemented on the Multi- PSI, the experimental parallel inference machine developed at ICOT. Our system simulates sequential circuits of practical size. Different delay times can be assig...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Tokyo, Japan
1991
|
| Schriftenreihe: | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical memorandum
1030 |
| Schlagworte: | |
| Zusammenfassung: | Abstract: "We have just constructed a parallel logic-level simulation system based on Virtual Time. It was implemented on the Multi- PSI, the experimental parallel inference machine developed at ICOT. Our system simulates sequential circuits of practical size. Different delay times can be assigned to gates in the circuits. This paper proposes a new partitioning strategy of circuit data that is efficient for Virtual Time and also reports the measurement results of the simulator. In our experiment, a sequential circuit consisting of over 10,000 gates was simulated. Using 64 processors, the system indicated about 47k events/sec as its performance, and also indicated about 47 times speedup This paper, using these results, denotes that Virtual Time is an efficient local synchronization mechanism and the new partitioning strategy proposed here can be a practical strategy. |
| Beschreibung: | 7 S. |
Internformat
MARC
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| 100 | 1 | |a Matsumoto, Yukinori |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Parallel logic-level simulation system on a distributed memory machine |c by Y. Matsumoto & K. Taki |
| 264 | 1 | |a Tokyo, Japan |c 1991 | |
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| 490 | 1 | |a Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical memorandum |v 1030 | |
| 520 | 3 | |a Abstract: "We have just constructed a parallel logic-level simulation system based on Virtual Time. It was implemented on the Multi- PSI, the experimental parallel inference machine developed at ICOT. Our system simulates sequential circuits of practical size. Different delay times can be assigned to gates in the circuits. This paper proposes a new partitioning strategy of circuit data that is efficient for Virtual Time and also reports the measurement results of the simulator. In our experiment, a sequential circuit consisting of over 10,000 gates was simulated. Using 64 processors, the system indicated about 47k events/sec as its performance, and also indicated about 47 times speedup | |
| 520 | 3 | |a This paper, using these results, denotes that Virtual Time is an efficient local synchronization mechanism and the new partitioning strategy proposed here can be a practical strategy. | |
| 650 | 4 | |a Integrated circuits |x Design and construction | |
| 700 | 1 | |a Taki, Kazuo |e Verfasser |4 aut | |
| 830 | 0 | |a Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical memorandum |v 1030 |w (DE-604)BV010943497 |9 1030 | |
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Datensatz im Suchindex
| _version_ | 1804125458608947200 |
|---|---|
| any_adam_object | |
| author | Matsumoto, Yukinori Taki, Kazuo |
| author_facet | Matsumoto, Yukinori Taki, Kazuo |
| author_role | aut aut |
| author_sort | Matsumoto, Yukinori |
| author_variant | y m ym k t kt |
| building | Verbundindex |
| bvnumber | BV010970708 |
| ctrlnum | (OCoLC)25797516 (DE-599)BVBBV010970708 |
| format | Book |
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| id | DE-604.BV010970708 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T18:01:53Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007340373 |
| oclc_num | 25797516 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM |
| owner_facet | DE-91G DE-BY-TUM |
| physical | 7 S. |
| publishDate | 1991 |
| publishDateSearch | 1991 |
| publishDateSort | 1991 |
| record_format | marc |
| series | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical memorandum |
| series2 | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical memorandum |
| spelling | Matsumoto, Yukinori Verfasser aut Parallel logic-level simulation system on a distributed memory machine by Y. Matsumoto & K. Taki Tokyo, Japan 1991 7 S. txt rdacontent n rdamedia nc rdacarrier Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical memorandum 1030 Abstract: "We have just constructed a parallel logic-level simulation system based on Virtual Time. It was implemented on the Multi- PSI, the experimental parallel inference machine developed at ICOT. Our system simulates sequential circuits of practical size. Different delay times can be assigned to gates in the circuits. This paper proposes a new partitioning strategy of circuit data that is efficient for Virtual Time and also reports the measurement results of the simulator. In our experiment, a sequential circuit consisting of over 10,000 gates was simulated. Using 64 processors, the system indicated about 47k events/sec as its performance, and also indicated about 47 times speedup This paper, using these results, denotes that Virtual Time is an efficient local synchronization mechanism and the new partitioning strategy proposed here can be a practical strategy. Integrated circuits Design and construction Taki, Kazuo Verfasser aut Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical memorandum 1030 (DE-604)BV010943497 1030 |
| spellingShingle | Matsumoto, Yukinori Taki, Kazuo Parallel logic-level simulation system on a distributed memory machine Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical memorandum Integrated circuits Design and construction |
| title | Parallel logic-level simulation system on a distributed memory machine |
| title_auth | Parallel logic-level simulation system on a distributed memory machine |
| title_exact_search | Parallel logic-level simulation system on a distributed memory machine |
| title_full | Parallel logic-level simulation system on a distributed memory machine by Y. Matsumoto & K. Taki |
| title_fullStr | Parallel logic-level simulation system on a distributed memory machine by Y. Matsumoto & K. Taki |
| title_full_unstemmed | Parallel logic-level simulation system on a distributed memory machine by Y. Matsumoto & K. Taki |
| title_short | Parallel logic-level simulation system on a distributed memory machine |
| title_sort | parallel logic level simulation system on a distributed memory machine |
| topic | Integrated circuits Design and construction |
| topic_facet | Integrated circuits Design and construction |
| volume_link | (DE-604)BV010943497 |
| work_keys_str_mv | AT matsumotoyukinori parallellogiclevelsimulationsystemonadistributedmemorymachine AT takikazuo parallellogiclevelsimulationsystemonadistributedmemorymachine |