Abstract: "This paper presents the features of PIM/k, one of the Parallel Inference Machines being developed under the Japan's Fifth Generation Computer Project. One of the primary goals of the project is to realize a fast inference machine by means of parallel processing. Towards this goa...

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Bibliographic Details

Format:	Book
Language:	English
Published:	Tokyo, Japan 1992
Series:	Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report 768
Subjects:	Fifth generation computers KL1 (Computer program language) Logic programming Parallel processing (Electronic computers)
Summary:	Abstract: "This paper presents the features of PIM/k, one of the Parallel Inference Machines being developed under the Japan's Fifth Generation Computer Project. One of the primary goals of the project is to realize a fast inference machine by means of parallel processing. Towards this goal, PIM/k employs a cache hierarchy to reduce the memory access latency, while the other PIMs employ inter-cluster networks to obtain high band-width of the whole systems. This paper describes the design considerations of a hierarchical cache consistency protocol with an efficient replacement algorithm. The KL1 system software which was initially designed for the inter-cluster networks of the other PIMs should be tuned for the cache hierarchy This paper shows that the cache hierarchy is advantageous from the software points of view and that stop-and-copy GC employed by the PIMs requires adapting in order to avoid an efficiency problem. Though PIM/k is still under development, this paper also reports a KL1 program evaluation on the actual machine with 4 processing elements (PEs).
Physical Description:	14 S.