Hardware implementation of dynamic load balancing in the parallel inference machine PIM c:
Abstract: "This paper proposes and evaluates the hardware implementation required for dynamic load balancing in the prototype PIM/c of the Parallel Inference Machine (PIM). In fine grain multiprocessing, dynamic load balancing is suffering from the high overhead due to the frequent access to lo...
Saved in:
| Format: | Book |
|---|---|
| Language: | English |
| Published: |
Tokyo, Japan
1992
|
| Series: | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report
755 |
| Subjects: | |
| Summary: | Abstract: "This paper proposes and evaluates the hardware implementation required for dynamic load balancing in the prototype PIM/c of the Parallel Inference Machine (PIM). In fine grain multiprocessing, dynamic load balancing is suffering from the high overhead due to the frequent access to load information. Proposed hardware can reduce the overhead by speeding up the access to the load information. In order to utilize the high locality of logic programs, PIM/c is configured along a hierarchical structure of network-connected clusters each of which is a bus-connected multiprocessor. Therefore two kinds of hardware suitable for each hierarchy are implemented for dynamic load balancing First, in the clusters, we propose a register with broadcast write feature. The evaluation determines the reduction of overhead due to memory polling which detects a load request. The proposed hardware reduces the execution time of logic programs by 15%. Second, in the network, we propose the use of a shortcut path to request the value of the total load within a cluster. The evaluation shows that the overhead due to the request of that value is reduced as a result of introducing the shortcut path. The proposed hardware reduces the execution time by 50%. The results obtained confirm that the use of hardware can reduce the high overhead of dynamic load balancing. |
| Physical Description: | 8 S. |
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| 520 | 3 | |a Abstract: "This paper proposes and evaluates the hardware implementation required for dynamic load balancing in the prototype PIM/c of the Parallel Inference Machine (PIM). In fine grain multiprocessing, dynamic load balancing is suffering from the high overhead due to the frequent access to load information. Proposed hardware can reduce the overhead by speeding up the access to the load information. In order to utilize the high locality of logic programs, PIM/c is configured along a hierarchical structure of network-connected clusters each of which is a bus-connected multiprocessor. Therefore two kinds of hardware suitable for each hierarchy are implemented for dynamic load balancing | |
| 520 | 3 | |a First, in the clusters, we propose a register with broadcast write feature. The evaluation determines the reduction of overhead due to memory polling which detects a load request. The proposed hardware reduces the execution time of logic programs by 15%. Second, in the network, we propose the use of a shortcut path to request the value of the total load within a cluster. The evaluation shows that the overhead due to the request of that value is reduced as a result of introducing the shortcut path. The proposed hardware reduces the execution time by 50%. The results obtained confirm that the use of hardware can reduce the high overhead of dynamic load balancing. | |
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| id | DE-604.BV010956625 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T18:01:39Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007328738 |
| oclc_num | 27482818 |
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| owner | DE-91G DE-BY-TUM |
| owner_facet | DE-91G DE-BY-TUM |
| physical | 8 S. |
| publishDate | 1992 |
| publishDateSearch | 1992 |
| publishDateSort | 1992 |
| record_format | marc |
| series | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |
| series2 | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |
| spelling | Hardware implementation of dynamic load balancing in the parallel inference machine PIM c by T. Nakagawa ... Tokyo, Japan 1992 8 S. txt rdacontent n rdamedia nc rdacarrier Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report 755 Abstract: "This paper proposes and evaluates the hardware implementation required for dynamic load balancing in the prototype PIM/c of the Parallel Inference Machine (PIM). In fine grain multiprocessing, dynamic load balancing is suffering from the high overhead due to the frequent access to load information. Proposed hardware can reduce the overhead by speeding up the access to the load information. In order to utilize the high locality of logic programs, PIM/c is configured along a hierarchical structure of network-connected clusters each of which is a bus-connected multiprocessor. Therefore two kinds of hardware suitable for each hierarchy are implemented for dynamic load balancing First, in the clusters, we propose a register with broadcast write feature. The evaluation determines the reduction of overhead due to memory polling which detects a load request. The proposed hardware reduces the execution time of logic programs by 15%. Second, in the network, we propose the use of a shortcut path to request the value of the total load within a cluster. The evaluation shows that the overhead due to the request of that value is reduced as a result of introducing the shortcut path. The proposed hardware reduces the execution time by 50%. The results obtained confirm that the use of hardware can reduce the high overhead of dynamic load balancing. KL1 (Computer program language) Logic programming Multiprocessors Nakagawa, Toshio Sonstige oth Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report 755 (DE-604)BV010923438 755 |
| spellingShingle | Hardware implementation of dynamic load balancing in the parallel inference machine PIM c Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report KL1 (Computer program language) Logic programming Multiprocessors |
| title | Hardware implementation of dynamic load balancing in the parallel inference machine PIM c |
| title_auth | Hardware implementation of dynamic load balancing in the parallel inference machine PIM c |
| title_exact_search | Hardware implementation of dynamic load balancing in the parallel inference machine PIM c |
| title_full | Hardware implementation of dynamic load balancing in the parallel inference machine PIM c by T. Nakagawa ... |
| title_fullStr | Hardware implementation of dynamic load balancing in the parallel inference machine PIM c by T. Nakagawa ... |
| title_full_unstemmed | Hardware implementation of dynamic load balancing in the parallel inference machine PIM c by T. Nakagawa ... |
| title_short | Hardware implementation of dynamic load balancing in the parallel inference machine PIM c |
| title_sort | hardware implementation of dynamic load balancing in the parallel inference machine pim c |
| topic | KL1 (Computer program language) Logic programming Multiprocessors |
| topic_facet | KL1 (Computer program language) Logic programming Multiprocessors |
| volume_link | (DE-604)BV010923438 |
| work_keys_str_mv | AT nakagawatoshio hardwareimplementationofdynamicloadbalancingintheparallelinferencemachinepimc |