Parallel logic simulator based on time warp and its evaluation:
Abstract: "This paper focuses on parallel logic simulation. An efficient logic simulator on a large-scale multiprocessor is targeted. The Time Warp mechanism, an optimistic method for time keeping, was experimented and evaluated. Synchronous mechanisms and conservative mechanisms for time keepi...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Tokyo, Japan
1991
|
| Schriftenreihe: | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report
711 |
| Schlagworte: | |
| Zusammenfassung: | Abstract: "This paper focuses on parallel logic simulation. An efficient logic simulator on a large-scale multiprocessor is targeted. The Time Warp mechanism, an optimistic method for time keeping, was experimented and evaluated. Synchronous mechanisms and conservative mechanisms for time keeping have been already examined, and their inefficiency on large-scale distributed memory machines has been pointed out. On the other hand, there have been few reports on evaluation of the Time Warp mechanism although rollback processes have been presumed to be heavy. We aim at evaluating the efficiency of this mechanism Several devices such as a local message scheduler, an antimessage reduction mechanism and a load distribution scheme are added in order to reduce rollback overhead. The simulator is implemented on the Multi-PSI, a distributed memory multiprocessor. The simulator is written in concurrent logic language KL1. KL1 is expected to be suitable for parallel programming because it supports data-flow synchronization and global name space across the processor boundary. In our experiment using 64 processors, 48-fold speedup and 99K events/sec performance was obtained. The result showed that the simulator has fairly good performance as a full-software logic simulator. Also we ascertained that rollback processes slightly affected performance. |
| Beschreibung: | 16 S. |
Internformat
MARC
| LEADER | 00000nam a2200000 cb4500 | ||
|---|---|---|---|
| 001 | BV010956069 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | t | ||
| 008 | 960918s1991 |||| 00||| engod | ||
| 035 | |a (OCoLC)26483721 | ||
| 035 | |a (DE-599)BVBBV010956069 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-91G | ||
| 100 | 1 | |a Matsumoto, Yukinori |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Parallel logic simulator based on time warp and its evaluation |c by Y. Matsumoto & K. Taki |
| 264 | 1 | |a Tokyo, Japan |c 1991 | |
| 300 | |a 16 S. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |v 711 | |
| 520 | 3 | |a Abstract: "This paper focuses on parallel logic simulation. An efficient logic simulator on a large-scale multiprocessor is targeted. The Time Warp mechanism, an optimistic method for time keeping, was experimented and evaluated. Synchronous mechanisms and conservative mechanisms for time keeping have been already examined, and their inefficiency on large-scale distributed memory machines has been pointed out. On the other hand, there have been few reports on evaluation of the Time Warp mechanism although rollback processes have been presumed to be heavy. We aim at evaluating the efficiency of this mechanism | |
| 520 | 3 | |a Several devices such as a local message scheduler, an antimessage reduction mechanism and a load distribution scheme are added in order to reduce rollback overhead. The simulator is implemented on the Multi-PSI, a distributed memory multiprocessor. The simulator is written in concurrent logic language KL1. KL1 is expected to be suitable for parallel programming because it supports data-flow synchronization and global name space across the processor boundary. In our experiment using 64 processors, 48-fold speedup and 99K events/sec performance was obtained. The result showed that the simulator has fairly good performance as a full-software logic simulator. Also we ascertained that rollback processes slightly affected performance. | |
| 650 | 4 | |a KL1 (Computer program language) | |
| 650 | 4 | |a Multiprocessors | |
| 650 | 4 | |a Parallel computers | |
| 700 | 1 | |a Taki, Kazuo |e Verfasser |4 aut | |
| 830 | 0 | |a Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |v 711 |w (DE-604)BV010923438 |9 711 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-007328250 | ||
Datensatz im Suchindex
| _version_ | 1804125443249405952 |
|---|---|
| any_adam_object | |
| author | Matsumoto, Yukinori Taki, Kazuo |
| author_facet | Matsumoto, Yukinori Taki, Kazuo |
| author_role | aut aut |
| author_sort | Matsumoto, Yukinori |
| author_variant | y m ym k t kt |
| building | Verbundindex |
| bvnumber | BV010956069 |
| ctrlnum | (OCoLC)26483721 (DE-599)BVBBV010956069 |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02442nam a2200337 cb4500</leader><controlfield tag="001">BV010956069</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">960918s1991 |||| 00||| engod</controlfield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)26483721</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV010956069</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91G</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Matsumoto, Yukinori</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Parallel logic simulator based on time warp and its evaluation</subfield><subfield code="c">by Y. Matsumoto & K. Taki</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Tokyo, Japan</subfield><subfield code="c">1991</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">16 S.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report</subfield><subfield code="v">711</subfield></datafield><datafield tag="520" ind1="3" ind2=" "><subfield code="a">Abstract: "This paper focuses on parallel logic simulation. An efficient logic simulator on a large-scale multiprocessor is targeted. The Time Warp mechanism, an optimistic method for time keeping, was experimented and evaluated. Synchronous mechanisms and conservative mechanisms for time keeping have been already examined, and their inefficiency on large-scale distributed memory machines has been pointed out. On the other hand, there have been few reports on evaluation of the Time Warp mechanism although rollback processes have been presumed to be heavy. We aim at evaluating the efficiency of this mechanism</subfield></datafield><datafield tag="520" ind1="3" ind2=" "><subfield code="a">Several devices such as a local message scheduler, an antimessage reduction mechanism and a load distribution scheme are added in order to reduce rollback overhead. The simulator is implemented on the Multi-PSI, a distributed memory multiprocessor. The simulator is written in concurrent logic language KL1. KL1 is expected to be suitable for parallel programming because it supports data-flow synchronization and global name space across the processor boundary. In our experiment using 64 processors, 48-fold speedup and 99K events/sec performance was obtained. The result showed that the simulator has fairly good performance as a full-software logic simulator. Also we ascertained that rollback processes slightly affected performance.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">KL1 (Computer program language)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Multiprocessors</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Parallel computers</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Taki, Kazuo</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="830" ind1=" " ind2="0"><subfield code="a">Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report</subfield><subfield code="v">711</subfield><subfield code="w">(DE-604)BV010923438</subfield><subfield code="9">711</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-007328250</subfield></datafield></record></collection> |
| id | DE-604.BV010956069 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T18:01:38Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007328250 |
| oclc_num | 26483721 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM |
| owner_facet | DE-91G DE-BY-TUM |
| physical | 16 S. |
| publishDate | 1991 |
| publishDateSearch | 1991 |
| publishDateSort | 1991 |
| record_format | marc |
| series | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |
| series2 | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |
| spelling | Matsumoto, Yukinori Verfasser aut Parallel logic simulator based on time warp and its evaluation by Y. Matsumoto & K. Taki Tokyo, Japan 1991 16 S. txt rdacontent n rdamedia nc rdacarrier Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report 711 Abstract: "This paper focuses on parallel logic simulation. An efficient logic simulator on a large-scale multiprocessor is targeted. The Time Warp mechanism, an optimistic method for time keeping, was experimented and evaluated. Synchronous mechanisms and conservative mechanisms for time keeping have been already examined, and their inefficiency on large-scale distributed memory machines has been pointed out. On the other hand, there have been few reports on evaluation of the Time Warp mechanism although rollback processes have been presumed to be heavy. We aim at evaluating the efficiency of this mechanism Several devices such as a local message scheduler, an antimessage reduction mechanism and a load distribution scheme are added in order to reduce rollback overhead. The simulator is implemented on the Multi-PSI, a distributed memory multiprocessor. The simulator is written in concurrent logic language KL1. KL1 is expected to be suitable for parallel programming because it supports data-flow synchronization and global name space across the processor boundary. In our experiment using 64 processors, 48-fold speedup and 99K events/sec performance was obtained. The result showed that the simulator has fairly good performance as a full-software logic simulator. Also we ascertained that rollback processes slightly affected performance. KL1 (Computer program language) Multiprocessors Parallel computers Taki, Kazuo Verfasser aut Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report 711 (DE-604)BV010923438 711 |
| spellingShingle | Matsumoto, Yukinori Taki, Kazuo Parallel logic simulator based on time warp and its evaluation Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report KL1 (Computer program language) Multiprocessors Parallel computers |
| title | Parallel logic simulator based on time warp and its evaluation |
| title_auth | Parallel logic simulator based on time warp and its evaluation |
| title_exact_search | Parallel logic simulator based on time warp and its evaluation |
| title_full | Parallel logic simulator based on time warp and its evaluation by Y. Matsumoto & K. Taki |
| title_fullStr | Parallel logic simulator based on time warp and its evaluation by Y. Matsumoto & K. Taki |
| title_full_unstemmed | Parallel logic simulator based on time warp and its evaluation by Y. Matsumoto & K. Taki |
| title_short | Parallel logic simulator based on time warp and its evaluation |
| title_sort | parallel logic simulator based on time warp and its evaluation |
| topic | KL1 (Computer program language) Multiprocessors Parallel computers |
| topic_facet | KL1 (Computer program language) Multiprocessors Parallel computers |
| volume_link | (DE-604)BV010923438 |
| work_keys_str_mv | AT matsumotoyukinori parallellogicsimulatorbasedontimewarpanditsevaluation AT takikazuo parallellogicsimulatorbasedontimewarpanditsevaluation |