A cooperative logic design expert system on a multiprocessor:
Abstract: "CAD systems that can quickly produce quality designs are needed for the expanding VLSI market. This paper presents a cooperative design mechanism in a cooperative logic design expert system on a multiprocessor, co-LODEX. co-LODEX accepts constraints on area and speed, and outputs a C...
Saved in:
| Format: | Book |
|---|---|
| Language: | English |
| Published: |
Tokyo, Japan
1991
|
| Series: | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report
699 |
| Subjects: | |
| Summary: | Abstract: "CAD systems that can quickly produce quality designs are needed for the expanding VLSI market. This paper presents a cooperative design mechanism in a cooperative logic design expert system on a multiprocessor, co-LODEX. co-LODEX accepts constraints on area and speed, and outputs a CMOS standard cell netlist that satisfies the constraints. The user can even get an optimal circuit for area or speed by iteratively strengthening the corresponding constraint. Short turnaround is expected through the combination of parallel processing by several processors and their cooperation. The cooperative design mechanism is based on an evaluation-redesign mechanism using assumption-based reasoning within a single processor Design alternatives are considered as assumptions and constraint violations as contradictions. Redesign is implemented as contradiction resolution. The evaluation-redesign cycle repeats itself until the design satisfies the specified constraints. Global evaluation-redesign takes place by processors exchanging design results for subcircuits in terms of gate counts and delays (in case of success) or justifications for constraint violations (in case of failure). Experimental results show that (1) co-LODEX can efficiently carry out global optimization. For example, a circuit with the minimum number of gates has been obtained while satisfying constraint on speed. (2) Linear speedup has been observed at best. |
| Physical Description: | 15 S. |
Staff View
MARC
| LEADER | 00000nam a2200000 cb4500 | ||
|---|---|---|---|
| 001 | BV010955899 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | t | ||
| 008 | 960918s1991 |||| 00||| engod | ||
| 035 | |a (OCoLC)26737697 | ||
| 035 | |a (DE-599)BVBBV010955899 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-91G | ||
| 245 | 1 | 0 | |a A cooperative logic design expert system on a multiprocessor |c by Y. Minoda ... |
| 264 | 1 | |a Tokyo, Japan |c 1991 | |
| 300 | |a 15 S. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |v 699 | |
| 520 | 3 | |a Abstract: "CAD systems that can quickly produce quality designs are needed for the expanding VLSI market. This paper presents a cooperative design mechanism in a cooperative logic design expert system on a multiprocessor, co-LODEX. co-LODEX accepts constraints on area and speed, and outputs a CMOS standard cell netlist that satisfies the constraints. The user can even get an optimal circuit for area or speed by iteratively strengthening the corresponding constraint. Short turnaround is expected through the combination of parallel processing by several processors and their cooperation. The cooperative design mechanism is based on an evaluation-redesign mechanism using assumption-based reasoning within a single processor | |
| 520 | 3 | |a Design alternatives are considered as assumptions and constraint violations as contradictions. Redesign is implemented as contradiction resolution. The evaluation-redesign cycle repeats itself until the design satisfies the specified constraints. Global evaluation-redesign takes place by processors exchanging design results for subcircuits in terms of gate counts and delays (in case of success) or justifications for constraint violations (in case of failure). Experimental results show that (1) co-LODEX can efficiently carry out global optimization. For example, a circuit with the minimum number of gates has been obtained while satisfying constraint on speed. (2) Linear speedup has been observed at best. | |
| 650 | 4 | |a Computer-aided design | |
| 650 | 4 | |a Expert systems (Computer science) | |
| 650 | 4 | |a Logic design | |
| 650 | 4 | |a Multiprocessors | |
| 700 | 1 | |a Minoda, Yoriko |e Sonstige |4 oth | |
| 830 | 0 | |a Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |v 699 |w (DE-604)BV010923438 |9 699 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-007328097 | ||
Record in the Search Index
| _version_ | 1804125443056467968 |
|---|---|
| any_adam_object | |
| building | Verbundindex |
| bvnumber | BV010955899 |
| ctrlnum | (OCoLC)26737697 (DE-599)BVBBV010955899 |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02506nam a2200337 cb4500</leader><controlfield tag="001">BV010955899</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">960918s1991 |||| 00||| engod</controlfield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)26737697</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV010955899</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91G</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">A cooperative logic design expert system on a multiprocessor</subfield><subfield code="c">by Y. Minoda ...</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Tokyo, Japan</subfield><subfield code="c">1991</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">15 S.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report</subfield><subfield code="v">699</subfield></datafield><datafield tag="520" ind1="3" ind2=" "><subfield code="a">Abstract: "CAD systems that can quickly produce quality designs are needed for the expanding VLSI market. This paper presents a cooperative design mechanism in a cooperative logic design expert system on a multiprocessor, co-LODEX. co-LODEX accepts constraints on area and speed, and outputs a CMOS standard cell netlist that satisfies the constraints. The user can even get an optimal circuit for area or speed by iteratively strengthening the corresponding constraint. Short turnaround is expected through the combination of parallel processing by several processors and their cooperation. The cooperative design mechanism is based on an evaluation-redesign mechanism using assumption-based reasoning within a single processor</subfield></datafield><datafield tag="520" ind1="3" ind2=" "><subfield code="a">Design alternatives are considered as assumptions and constraint violations as contradictions. Redesign is implemented as contradiction resolution. The evaluation-redesign cycle repeats itself until the design satisfies the specified constraints. Global evaluation-redesign takes place by processors exchanging design results for subcircuits in terms of gate counts and delays (in case of success) or justifications for constraint violations (in case of failure). Experimental results show that (1) co-LODEX can efficiently carry out global optimization. For example, a circuit with the minimum number of gates has been obtained while satisfying constraint on speed. (2) Linear speedup has been observed at best.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer-aided design</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Expert systems (Computer science)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Logic design</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Multiprocessors</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Minoda, Yoriko</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="830" ind1=" " ind2="0"><subfield code="a">Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report</subfield><subfield code="v">699</subfield><subfield code="w">(DE-604)BV010923438</subfield><subfield code="9">699</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-007328097</subfield></datafield></record></collection> |
| id | DE-604.BV010955899 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T18:01:38Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007328097 |
| oclc_num | 26737697 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM |
| owner_facet | DE-91G DE-BY-TUM |
| physical | 15 S. |
| publishDate | 1991 |
| publishDateSearch | 1991 |
| publishDateSort | 1991 |
| record_format | marc |
| series | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |
| series2 | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |
| spelling | A cooperative logic design expert system on a multiprocessor by Y. Minoda ... Tokyo, Japan 1991 15 S. txt rdacontent n rdamedia nc rdacarrier Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report 699 Abstract: "CAD systems that can quickly produce quality designs are needed for the expanding VLSI market. This paper presents a cooperative design mechanism in a cooperative logic design expert system on a multiprocessor, co-LODEX. co-LODEX accepts constraints on area and speed, and outputs a CMOS standard cell netlist that satisfies the constraints. The user can even get an optimal circuit for area or speed by iteratively strengthening the corresponding constraint. Short turnaround is expected through the combination of parallel processing by several processors and their cooperation. The cooperative design mechanism is based on an evaluation-redesign mechanism using assumption-based reasoning within a single processor Design alternatives are considered as assumptions and constraint violations as contradictions. Redesign is implemented as contradiction resolution. The evaluation-redesign cycle repeats itself until the design satisfies the specified constraints. Global evaluation-redesign takes place by processors exchanging design results for subcircuits in terms of gate counts and delays (in case of success) or justifications for constraint violations (in case of failure). Experimental results show that (1) co-LODEX can efficiently carry out global optimization. For example, a circuit with the minimum number of gates has been obtained while satisfying constraint on speed. (2) Linear speedup has been observed at best. Computer-aided design Expert systems (Computer science) Logic design Multiprocessors Minoda, Yoriko Sonstige oth Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report 699 (DE-604)BV010923438 699 |
| spellingShingle | A cooperative logic design expert system on a multiprocessor Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report Computer-aided design Expert systems (Computer science) Logic design Multiprocessors |
| title | A cooperative logic design expert system on a multiprocessor |
| title_auth | A cooperative logic design expert system on a multiprocessor |
| title_exact_search | A cooperative logic design expert system on a multiprocessor |
| title_full | A cooperative logic design expert system on a multiprocessor by Y. Minoda ... |
| title_fullStr | A cooperative logic design expert system on a multiprocessor by Y. Minoda ... |
| title_full_unstemmed | A cooperative logic design expert system on a multiprocessor by Y. Minoda ... |
| title_short | A cooperative logic design expert system on a multiprocessor |
| title_sort | a cooperative logic design expert system on a multiprocessor |
| topic | Computer-aided design Expert systems (Computer science) Logic design Multiprocessors |
| topic_facet | Computer-aided design Expert systems (Computer science) Logic design Multiprocessors |
| volume_link | (DE-604)BV010923438 |
| work_keys_str_mv | AT minodayoriko acooperativelogicdesignexpertsystemonamultiprocessor |