The complexity of simple computer architectures:
Saved in:
| Main Authors: | , |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Berlin u.a.
Springer
1995
|
| Series: | Lecture notes in computer science
995 |
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Physical Description: | XII, 270 S. graph. Darst. |
| ISBN: | 3540605800 |
Staff View
MARC
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| 100 | 1 | |a Müller, Silvia Melitta |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a The complexity of simple computer architectures |c Silvia M. Müller ; Wolfgang J. Paul |
| 264 | 1 | |a Berlin u.a. |b Springer |c 1995 | |
| 300 | |a XII, 270 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Lecture notes in computer science |v 995 | |
| 650 | 4 | |a Computer architecture | |
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Record in the Search Index
| _version_ | 1820874848367280128 |
|---|---|
| adam_text |
CONTENTS
1
INTRODUCTION
1
2
THE
FORMAL
ARCHITECTURE
MODEL
5
2.1
THE
PERFORMANCE
MODEL
.
5
2.2
QUALITY
METRICS
.
6
2.3
COMPARISON
OF
ARCHITECTURES
.
7
2.4
THE
HARDWARE
MODEL
.
8
2.4.1
BASIC
COMPONENTS
.
9
2.4.2
COMBINATORIAL
CIRCUITS
.
11
2.4.3
CLOCKED
CIRCUITS
.
12
2.4.4
MODIFIED
HARDWARE
.
13
2.4.5
CONTROL
DRIVEN
CIRCUITS
.
15
2.4.6
A
SPECIAL
DEVICE:
MAIN
MEMORY
.
16
2.4.7
POWERUP
CONVENTION
AND
EXTERNAL
SIGNALS
.
18
2.4.8
EXTENDED
NOMENCLATURE
OF
DELAY
FORMULAE
.
18
3
FUNCTIONAL
MODULES
21
3.1
N-BIT
COMPONENTS
.
21
3.2
DECODERS
.
23
3.3 A
HALF-DECODER
.
26
3.4
AN
ENCODER
.
26
3.5
TESTING
FOR
ZERO
.
28
3.6
THE
RIPPLE
CARRY
INCREMENTER
.
28
3.7
ARITHMETIC
CIRCUITS
.
29
3.7.1
THE
TWO
'
S
COMPLEMENT
ADDER
.
30
3.7.2
THE
RIPPLE
CARRY
ADDER
(RCA)
.
32
3.7.3
THE
CARRY
LOOK-AHEAD
ADDER
(CLA)
.
34
3.7.4
THE
CONDITIONAL
SUM
ADDER
(CSA)
.
35
3.7.5
THE
SUBTRACTION
.
37
3.7.6
THE
ARITHMETIC
UNIT
.
38
3.8
CYCLIC
SHIFTERS
.
38
3.8.1
A
CYCLIC
LEFT
SHIFTER
.
39
3.8.2
CYCLIC
RIGHT
SHIFTS
.
40
3.9
EXERCISES
.
41
X
CONTENTS
4
HARDWIRED
CONTROL
43
4.1
REPRESENTATION
OF
THE
CONTROL
.
43
4.2
IMPLEMENTATION
OF
MOORE
MACHINES
.
45
4.2.1
THE
STATE
.
45
4.2.2
GENERATING
THE
OUTPUTS
OJ
.
45
4.2.3
COMPUTING
THE
NEXT
STATE
.
46
4.2.4
COST
AND
DELAY
.
48
4.2.5
UNARY
CODING
.
48
4.3
MEALY
IMPLEMENTATION
.
49
4.3.1
TRANSFORMATIONS
.
50
4.3.2
UNARY
CODING
.
53
4.4
COST
IMPACT
OF
BINARY
CODING
.
54
4.4.1
IMPACT
ON
THE
MOORE
IMPLEMENTATION
.
54
4.4.2
IMPACT
ON
THE
MEALY
IMPLEMENTATION
.
56
4.5
EXERCISES
.
57
5
DESIGN
OF
A
MINIMAL
CPU
(BY
T.
GRIM)
59
5.1
DESIGN
.
59
5.1.1
INSTRUCTION
SET
.
59
5.1.2
DATA
PATHS
.
60
5.1.3
CONTROL
.
62
5.2
EVALUATION
.
62
5.2.1
COST
.
63
5.2.2
CYCLE-TIME
.
64
5.2.3
RUN
TIME
OF
A
BENCHMARK
.
66
5.2.4
QUALITY
.
68
5.3
TRADE-OFF
ANALYSIS
.
69
5.3.1
USING
SPECIAL
PURPOSE
COMPONENTS
.
69
5.3.2
ELIMINATING
SUPERFLUOUS
INSTRUCTIONS
.
69
5.3.3
CONDITIONAL
JUMP
OPTIMIZATION
.
70
5.3.4
DIFFERENT
ADDER
IMPLEMENTATIONS
.
71
5.3.5
INTRODUCING
A
SEPARATE
MEMORY
CYCLE
.
72
5.3.6
ADDING
A
NEW
INSTRUCTION
.
73
5.3.7
SUMMARY
.
74
5.4
EXERCISES
.
75
6
DESIGN
OF
THE
DLX
MACHINE
77
6.1
INSTRUCTION
SET
ARCHITECTURE
.
77
6.1.1
INSTRUCTION
FORMATS
.
78
6.1.2
INSTRUCTION
SET
CODING
.
78
6.1.3
COMMENTS
.
78
6.2
THE
DATA
PATHS
.
81
6.2.1
THE
ALU
ENVIRONMENT
.
82
6.2.2
THE
SHIFTER
ENVIRONMENT
.
86
6.2.3
THE
IR-ENVIRONMENT
.
93
6.2.4
THE
GPR-ENVIRONMENT
.
94
CONTENTS
XI
6.2.5
THE
PC-ENVIRONMENT
.
96
6.2.6
THE
MAIN
MEMORY
ENVIRONMENT
.
97
6.3
HARDWIRED
CONTROL
.
100
6.3.1
EXECUTION
SCHEME
.
101
6.3.2
COST
AND
DELAY
OF
THE
CONTROL
.
106
6.4
HARDWARE
COST
AND
CYCLE
TIME
.
110
6.4.1
HARDWARE
COST
.
ILL
6.4.2
CYCLE
TIME
.
112
6.4.3
DESIGN
EVALUATION
.
119
6.5
EXERCISES
.
120
7
TRADE-OFF
ANALYSES
123
7.1
MODIFICATION
OF
THE
ARITHMETIC
UNIT
.
123
7.2
MODIFICATIONS
OF
THE
CONDITION
TEST
.
124
7.2.1
TESTING
ALU
INPUTS
.
125
7.2.2
TWO
CYCLE
CONDITION
TEST
.
126
7.3
EVALUATION
OF
THE
DESIGN
MODIFICATIONS
.
128
7.3.1
WORKLOAD
INDEPENDENT
COMPARISON
.
129
7.3.2
WORKLOAD
DEPENDENT
COMPARISON
.
132
7.4
EXERCISES
.
140
8
INTERRUPT
141
8.1
SUPPORTING
INTERRUPTS
.
143
8.1.1
SPECIAL
PURPOSE
REGISTERS
AND
SPECIAL
INSTRUCTIONS
.
144
8.1.2
EXECUTION
OF
AN
INTERRUPT
SERVICE
ROUTINE
.
145
8.1.3
EXTENSIONS
OF
THE
DATA
PATHS
.
148
8.1.4
CONTROL
.
152
8.2
COST
AND
CYCLE
TIME
.
164
8.2.1
HARDWARE
COST
.
164
8.2.2
CYCLE
TIME
.
166
8.2.3
DESIGN
EVALUATION
.
171
8.3
CORRECTNESS
OF
INTERRUPT
HANDLING
.
173
8.4
EXERCISES
.
177
9
MICROPROGRAMMED
CONTROL
179
9.1
BASIC
PRINCIPLES
.
179
9.1.1
THE
ADDRESS
SELECTION
UNIT
.
181
9.1.2
IMPLEMENTATION
OF
A
TABLE
LOOKUP
.
183
9.1.3
MODIFICATIONS
OF
THE
MICROCODED
CONTROL
.
183
9.2
MICROCODED
DLX
ARCHITECTURE
.
185
9.2.1
THE
MICROINSTRUCTION
WORD
.
185
9.2.2
ADDRESS
SELECTION
UNIT
.
188
9.2.3
ENCODED
CONTROL
SIGNALS
.
192
9.2.4
HARDWARE
COST
AND
CYCLE
TIME
.
194
10
FURTHER
APPLICATIONS
OF
THE
ARCHITECTURE
MODEL
199
XII
CONTENTS
A
REGISTER
TRANSFER
LANGUAGE
201
B
COST
AND
RUN
TIME
PROGRAMS
203
B.L
MODULE
OF
THE
QUALITY
METRIC
.
204
B.L.L
HEADER
FILE
OF
THE
QUALITY
FUNCTIONS
.
204
B.L.
2
CODE
FILE
FOR
THE
QUALITY
FUNCTIONS
.
204
B.2
TECHNOLOGY
SPECIFICATION
.
205
B.2.1
HEADER
FILE
OF
THE
TECHNOLOGY
MODULE
.
205
B.2.
2
CODE
FILE
OF
THE
TECHNOLOGY
MODULE
.
206
B.3
LIBRARY
OF
FUNCTIONAL
CIRCUITS
.
210
B.3.1
HEADER
FILE
OF
THE
MACRO
LIBRARY
.
210
B.3.
2
CODE
FILE
OF
THE
MACRO
LIBRARY
.
210
B.4
HARDWIRED
CONTROL
.
216
B.4.1
HEADER
FILE
OF
THE
HARDWIRED
CONTROL
.
216
B.4.
2
CODE
FILE
OF
THE
HARDWIRED
CONTROL
.
217
B.5
MARK
1
LIKE
DESIGNS
.
222
B.5.1
ORIGINAL
MARK
1
DESIGN
.
222
B.5.
2
MODIFIED
DESIGN
ML_L
.
227
B.6
DLX
WITHOUT
INTERRUPT
HANDLING
.
229
B.7
DLX
WITH
IMPROVED
ALU
.
240
B.8
DLX
WITH
INTERRUPT
HANDLING
.
246
B.9
DLX
WITH
MICROPROGRAMMED
CONTROL
.
253
B.9.1
HEADER
FILE
OF
THE
MICROCODED
CONTROL
.
257
B.9.
2
CODE
FILE
OF
THE
MICROCODED
CONTROL
.
258
BIBLIOGRAPHY
263
INDEX
267 |
| any_adam_object | 1 |
| author | Müller, Silvia Melitta Paul, Wolfgang J. 1951- |
| author_GND | (DE-588)132287005 |
| author_facet | Müller, Silvia Melitta Paul, Wolfgang J. 1951- |
| author_role | aut aut |
| author_sort | Müller, Silvia Melitta |
| author_variant | s m m sm smm w j p wj wjp |
| building | Verbundindex |
| bvnumber | BV010477147 |
| callnumber-first | Q - Science |
| callnumber-label | QA76 |
| callnumber-raw | QA76.9.A73M84 1995 |
| callnumber-search | QA76.9.A73M84 1995 |
| callnumber-sort | QA 276.9 A73 M84 41995 |
| callnumber-subject | QA - Mathematics |
| classification_rvk | ST 150 |
| classification_tum | DAT 200f DAT 517f |
| ctrlnum | (OCoLC)845067835 (DE-599)BVBBV010477147 |
| dewey-full | 004.2/220 |
| dewey-hundreds | 000 - Computer science, information, general works |
| dewey-ones | 004 - Computer science |
| dewey-raw | 004.2/2 20 |
| dewey-search | 004.2/2 20 |
| dewey-sort | 14.2 12 220 |
| dewey-tens | 000 - Computer science, information, general works |
| discipline | Informatik |
| format | Book |
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| id | DE-604.BV010477147 |
| illustrated | Illustrated |
| indexdate | 2025-01-10T15:06:16Z |
| institution | BVB |
| isbn | 3540605800 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-006980917 |
| oclc_num | 845067835 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM DE-384 DE-739 DE-29T DE-19 DE-BY-UBM DE-20 DE-83 DE-11 DE-188 DE-706 |
| owner_facet | DE-91G DE-BY-TUM DE-384 DE-739 DE-29T DE-19 DE-BY-UBM DE-20 DE-83 DE-11 DE-188 DE-706 |
| physical | XII, 270 S. graph. Darst. |
| publishDate | 1995 |
| publishDateSearch | 1995 |
| publishDateSort | 1995 |
| publisher | Springer |
| record_format | marc |
| series | Lecture notes in computer science |
| series2 | Lecture notes in computer science |
| spelling | Müller, Silvia Melitta Verfasser aut The complexity of simple computer architectures Silvia M. Müller ; Wolfgang J. Paul Berlin u.a. Springer 1995 XII, 270 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Lecture notes in computer science 995 Computer architecture Effizienz (DE-588)4013585-8 gnd rswk-swf Computerarchitektur (DE-588)4048717-9 gnd rswk-swf Komplexität (DE-588)4135369-9 gnd rswk-swf Computerarchitektur (DE-588)4048717-9 s Effizienz (DE-588)4013585-8 s DE-604 Komplexität (DE-588)4135369-9 s Paul, Wolfgang J. 1951- Verfasser (DE-588)132287005 aut Lecture notes in computer science 995 (DE-604)BV000000607 995 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006980917&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Müller, Silvia Melitta Paul, Wolfgang J. 1951- The complexity of simple computer architectures Lecture notes in computer science Computer architecture Effizienz (DE-588)4013585-8 gnd Computerarchitektur (DE-588)4048717-9 gnd Komplexität (DE-588)4135369-9 gnd |
| subject_GND | (DE-588)4013585-8 (DE-588)4048717-9 (DE-588)4135369-9 |
| title | The complexity of simple computer architectures |
| title_auth | The complexity of simple computer architectures |
| title_exact_search | The complexity of simple computer architectures |
| title_full | The complexity of simple computer architectures Silvia M. Müller ; Wolfgang J. Paul |
| title_fullStr | The complexity of simple computer architectures Silvia M. Müller ; Wolfgang J. Paul |
| title_full_unstemmed | The complexity of simple computer architectures Silvia M. Müller ; Wolfgang J. Paul |
| title_short | The complexity of simple computer architectures |
| title_sort | the complexity of simple computer architectures |
| topic | Computer architecture Effizienz (DE-588)4013585-8 gnd Computerarchitektur (DE-588)4048717-9 gnd Komplexität (DE-588)4135369-9 gnd |
| topic_facet | Computer architecture Effizienz Computerarchitektur Komplexität |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006980917&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV000000607 |
| work_keys_str_mv | AT mullersilviamelitta thecomplexityofsimplecomputerarchitectures AT paulwolfgangj thecomplexityofsimplecomputerarchitectures |