PowerPC system architecture:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Reading, Mass. [u.a.]
Addison-Wesley
1995
|
| Ausgabe: | 1. print. |
| Schriftenreihe: | PC system architecture series
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XLI, 609 S. graph. Darst. |
| ISBN: | 0201409909 |
Internformat
MARC
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| 100 | 1 | |a Shanley, Tom |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a PowerPC system architecture |c Tom Shanley |
| 250 | |a 1. print. | ||
| 264 | 1 | |a Reading, Mass. [u.a.] |b Addison-Wesley |c 1995 | |
| 300 | |a XLI, 609 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 0 | |a PC system architecture series | |
| 650 | 7 | |a Computerarchitectuur |2 gtt | |
| 650 | 7 | |a PowerPC |2 gtt | |
| 650 | 4 | |a Computer architecture | |
| 650 | 4 | |a PowerPC microprocessors | |
| 650 | 0 | 7 | |a PowerPC |0 (DE-588)4359646-0 |2 gnd |9 rswk-swf |
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| 999 | |a oai:aleph.bib-bvb.de:BVB01-006973045 | ||
Datensatz im Suchindex
| _version_ | 1804124897227571200 |
|---|---|
| adam_text | PowerPC System
Architecture
MINDSHARE, INC
TOM SHANLEY
• T
Addison-Wesley Publishing Company
Reading, Massachusetts • Menlo Park, California • New York
Don Mills, Ontario • Wokingham, England • Amsterdam
Bonn • Sydney • Singapore • Tokyo • Madrid • San Juan
Paris • Seoul • Milan • Mexico City • Taipei
Contents
Contents
Foreword xxxix
Acknowledgments xli
About This Book
The MindShare Architecture Series 1
Use the Glossary! 2
Organization of The Book 2
Part One — Background and Introduction 2
Volume One — PowerPC Processor Specification 2
Part Two — User Privilege Level Facilities 3
Part Three — Supervisor Privilege Level Facilities 3
Volume Two — The PPC 601 Processor 4
Part Four — The PowerPC 601 Processor 4
Who Should Read This Book 5
Prerequisite Knowledge 5
Documentation Conventions 5
Hex Notation 5
Binary Notation 5
Decimal Notation 5
Signal Name Representation 6
Bit Field Identification (logical bit or signal groups) 6
Processor Register Bit Identification 6
We Want Your Feedback 7
Bulletin Board 7
Mailing Address 7
Part One
Background and Introduction
Chapter 1: Technology Background
Memory Bottleneck ° 11
Prefetcher 12
Internal, Level One (LI) Cache 13
PowerPC System Architecture
General 13
Unified Code/Data Cache 14
Split Code and Data Caches 14
External, Level Two (L2) Cache 15
General 15
Look-Aside Cache 16
Look-Through Cache 17
Cache Handling of Memory Writes 19
General 19
Write-Through Cache 19
Write-Back Cache 19
MESI Cache Protocol 20
General 20
Snoop-Related Signals 21
Exclusive State 22
Shared State 23
Modified State 23
Backoff or Retry 24
Read Attempt and Backoff 24
Snoop Push-Back 25
Retry 25
Snoop Hit On Modified Block During Memory Write 25
Mass Storage — Very Slow Access Device 26
Paging Uses System DRAM As Mass Storage Cache 27
Paging Summary 28
Chapter 2: PowerPC System Overview
System Overview 31
Intro to Subsystem and Bus Relationships 37
Host Processor Transactions 37
PCI Bus Master Transactions 37
Standard Expansion Bus Master Transactions 38
Concurrent Bus Operation 39
Chapter 3: Processor Microarchitecture Overview
Introduction 42
Contents
Instruction Unit 44
Instruction Dispatcher 44
Integer, or Fixed-Point, Processor 44
Floating-Point Processor 44
Branch Processor 45
Memory Management Unit (MMU) 45
Cache 46
Memory Unit (MU) 46
System Interface 47
User vs Supervisor Privilege Level 50
Chapter 4: Intro To PowerPC Processor Spec
Software vs Hardware Architecture 50
Introduction to PowerPC Software Architecture 51
General 51
Instruction Length and Alignment 52
Length of Data Operands 52
64 and 32-Bit Processor Implementations 52
Basic Characteristics of 64-Bit Processor Implementations 52
Basic Characteristics of 32-Bit Processor Implementations 53
Instruction Classes 53
General 53
Forms of Defined Instructions 54
POWER vs PowerPC Architecture 54
Volume One
PowerPC Processor Specification
Part Two
User Privilege Level Facilities
Chapter 5: Applications Registers
General 59
General Purpose Registers (GPRs) 60
PowerPC Systen Architecture
Condition Register (CR) 61
Integer Exception Register (XER) 62
Link Register (LR) 62
Count Register (CTR) 63
TimeBase Registers (TBU, TBL) 64
Floating-Point Registers 64
Chapter 6: Applications Instructions
Branch-Oriented Instructions 67
Integer Memory Access Instructions 68
Non-Memory Integer Instructions 69
Floating-Point Instructions 69
Memory Access Floating-Point Instructions 69
Floating-Point Register-to-Register Move Instructions 70
Floating-Point Arithmetic Instructions 70
Floating-Point Rounding and Conversion Instructions 70
Floating-Point Compare Instructions 70
FPSCR Register Access Instructions 70
Cache Management Instructions 71
Brief Definition of WIM Bits 71
Instruction Cache Block Invalidate (icbi) Instruction 72
Data Cache Block Store (dcbst) Instruction 72
Purpose 72
Cache Miss 73
Hit on Cache Block in Exclusive State 73
Hit on Cache Block in Shared State : 73
Hit on Cache Block in Modified State 73
Rules 74
Data Cache Block Flush (dcbf) Instruction 74
Data Cache Block Set to Zero (dcbz) Instruction 74
Results 74
Specified Area Not Accessed by Other Processors (M = 0) 75
Specified Area Accessed by Other Processors (M = 1) 75
If Paging Disabled — Possible Problem When Least Expected 75
Rules 76
Data Cache Block Touch (debt) Instruction 77
^ Contents
Description 77
Example Usage 77
Rules 78
Data Cache Block Touch for Store (dcbtst) Instruction 78
Chapter 7: Address Modes, Branch Prediction
Introduction 79
Load/Store Addressing 80
General 80
Indirect with Immediate Index 80
Indirect with Index 81
Indirect 82
Branch Addressing 83
General 83
Branch (unconditional) 83
Branch Conditional 84
Branch Conditional to Count Register 86
Branch Conditional to Link Register 86
Instruction Prefetcher Effective Address Generation 87
Branch Prediction 87
Chapter 8: Real and Virtual Paging Models
MMU Disabled — Real Mode Addressing 89
Addressing With MMU Enabled 93
Chapter 9: Cache Management Issues
General 95
Self-Modifying Code and the icbi Instruction 96
isync Instruction Eliminates Stale Code from Pipeline 97
dcbst Instruction Writes Modified Instruction to Memory 97
Unified Code/Data Cache 97
Considerations for Write-Through Cache 98
General 98
Write-Through to Main Memory 98
Write-Through to L2 Cache 99
PowerPC System Architecture
Chapter 10: Misaligned Transfers and Performance
Transfers Guaranteed to Complete in Single Access 103
Misaligned Transfer Performance Impact 104
General 104
Crossing Cache Block Boundary 104
Crossing Page Boundary 105
Crossing Block Boundary 105
Crossing Segment Boundary 105
Dealing with Instruction Restart 105
General 105
Example Problem 106
Rules • 106
Special Note 107
Chapter 11: Shared Resource Acquisition
Protecting Access to Shared Resource 108
Semaphore Contention 108
PowerPC Architecture Solution 109
Semaphore Read and Establishing Reservation 109
Bit Test and Set Operation I l l
Another Processor Cancels Reservation I l l
Semaphore Update I l l
When Update Is Unsuccessful 112
An Example 113
Step One — Establish Resource Lock 113
Step Two — Access the Resource 116
Step Three — Unlock Resource 116
OS Supplies Semaphore Primitives 117
Chapter 12: Memory Usage Bits (WIMG)
Introduction 119
Write-Through (W) Bit 120
General „ 120
Write-Through Policy 120
Write-Back Policy 121
Store Miss 121
* Contents
Store Hit on Cache Block in Exclusive State 121
Store Hit on Cache Block in Shared State 122
Store Hit on Cache Block in Modified State 122
Cache Inhibit (I) Bit 122
Memory Coherency (M) Bit 123
General 123
Page or Block Local to This Processor (M = 0) 123
Page or Block Accessed by Other Processors (M = 1) 124
General 124
Snoop Miss 124
Snooper(s) Busy — Try Again Later 124
Snoop Hit on Modified Cache Block 125
Snoop Hit on Clean Cache Block 125
M=1 and Write-Through Page or Block 125
Supported WIM Bit Settings 126
Guarded Storage (G) Bit 127
Speculative Accesses 127
Speculative Access Problem 128
Solution — Mark Misbehaved Areas Guarded 129
Chapter 13: Access Order
Time and Order of Memory Accesses 131
Sync Instruction — Processor Stalls Until MU Flushed 132
eieio Instruction — Specifying Order of Posted Writes 133
Other Flush Method Yields Better Performance than Sync 134
Multiple-Access Instruction Accesses Cannot Be Ordered 134
eieio and sync on PPC 601 Processor 135
Chapter 14: The Timebase
The Time Base 137
PowerPC System Architecture
Part Three
The Operating System — Supervisor Privilege Level
Chapter 15: Operating System Registers
Placing Processor In Supervisor Mode 141
32-Bit Processor s OS Register Set 141
Machine State Register (MSR) 142
Power Management, Bit 13 (POW) 143
Interrupt Endian Mode, Bit 15 (ILE) 143
External Interrupt Enable, Bit 16 (EE) 143
Privilege Mode, Bit 17 (PR) 143
Floating-Point Available, Bit 18 (FP) 144
Machine Check Enable, Bit 19 (ME) 144
Floating-Point Interrupt Mode, Bits 20 and 23 (FE[0:l]) 144
Single-Step Trace Enable, Bit 21 (SE) 145
Branch Trace Enable, Bit 22 (BE) 145
Interrupt Prefix, Bit 25 (IP) 145
Instruction Address Relocation, Bit 26 (IR) 145
Data Address Relocation, Bit 27 (DR) 145
Recoverable Interrupt, Bit 30 (RI) 146
General 146
On Entry To an Interrupt Handler 146
On Exit From an Interrupt Handler 147
On Entry To the Machine Check or System Reset
Interrupt Handlers 147
Endian Mode, Bit 31 (LE) 147
State of MSR After Reset Removed 148
Interrupt-Related Registers 150
Save/Restore Register 0 (SRRO) 150
Save/Restore Register 1 (SRR1) 151
Special Purpose Registers GO - G3 152
Data Address Register (DAR) 153
Data Storage Interrupt Status Register (DSISR) 153
• ^ Contents
Paging-Related Registers 156
SDR1 — Page Table Base Address and Length 156
Segment Registers 156
Block Address Translation (BAT) Registers 156
Time Base Register (TBR) 156
Decrementer Register (DEC) 157
Processor ID Register (PIR) 157
Processor Version Register (PVR) 158
External Access Register (EAR) 158
64-Bit Processor s OS Register Set 159
Machine State Register (MSR) 160
General 160
Sixty-Four Bit Mode, Bit 0 (SF) 161
Interrupt-Related Registers 163
Save/Restore Register 0 (SRRO) 163
Save/Restore Register 1 (SRR1) 163
Special Purpose Registers GO - G3 163
Data Address Register (DAR) 163
Data Storage Interrupt Status Register (DSISR) 163
Paging-Related Registers 164
SDR1 — Page Table Base Address and Size 164
Address Space Register (ASR) - Segment Table Base Address 164
Block Address Translation (BAT) Registers 164
Time Base Register (TBR) 164
Processor ID Register (PIR) 164
Processor Version Register (PVR) 165
EAR Register 165
Chapter 16: Operating System Instructions
Interrupt-Related Instructions 167
System Call Instruction 167
Trap Instruction 168
Return from Interrupt (rfi) Instruction 168
SPR-Related Privileged Instructions 168
MSR-Related Privileged Instructions 168
Privileged Cache Management Instruction — dcbi 169
PowerPC System Architecture
Paging-Related Privileged Instructions 169
Segment Register Read/Write Instructions 169
TLB Management Instructions 170
SLB Management Instructions 170
Chapter 17: Address Translation Overview
Memory Areas Defined as Blocks or Pages 173
General 173
Block — Large Memory Region With One Set of Operational Rules 175
Effective, or Logical, Segments 176
General 176
Segment Type — Memory or I/O 179
Memory Segment Consists of Pages 181
Virtual Segments and Address Translation 182
Physical Memory Pages 182
Role of Page Table 182
Converting Effective Address to Physical Address 182
Overview of Demand-Mode Paging 183
General 183
Introduction to Page Table Scan 184
Indexing Into Page Table 185
Page Table Scan 185
Rationale for Table Scanning 186
Chapter 18: Virtual Paging
32-bit PowerPC Processor Paging Implementation 189
4GB = 16 Segments of Space 189
Segment Type Determination 191
Identifying Target Page Within Virtual Segment 194
Role of Page Table 194
Page Table Location and Length Determination 195
Organization of Page Table 196
Creating Page Table Index 198
Adjusting Index Length to Match Page Table Size 198
Converting Index Into Offset Within Page Table 199
Primary Scan, or Hash 199
Contents
Secondary Scan, or Hash 199
Testing Page Table Entry 200
Access Rights : 202
Why Entire Page Address Doesn t Have to Be in PTE 203
Two Examples of Page Address Translation 203
Example One 203
Assumptions
; 2O3
Step-by-Step Explanation of Example One 204
Example Two : - 206
Assumptions for Example Two 206
Step-by-Step Explanation of Example Two 207
TLB — Performance Enhancement Tool 209
Managing TLB • 210
Page Fault Handler s Job 210
Page Fault Interrupt : 210
Is Current Program Permitted to Access Target Page? 210
Memory Allocation Call 210
Successful Memory Allocation Call — Page Read Initiated , 211
Mass Storage Read Request by Operating System 211
Request Passed to Device Driver : 211
Application Program Put to Sleep 211
Transfer of Page to Memory 212
Page Transfer Completed 212
Making Page Table Entry 212
Re-Execution of Instruction 212
Unsuccessful Memory Allocation Call —Reuse a PTE 213
General 213
Replacing Page That Hasn t Been Referenced 213
Replacing Page That Has Been Referenced but not Updated 213
Replacing Page That Has Been Modified 215
64-bit PowerPC Processor Paging Implementation 217
264 Bytes = 236 Segments of Space 217
Segment Type Determination 217
Creating STAB Index 221
Primary Hash 221
Secondary Hash 221
X V
PowerPC SystemoArchitecture
Segment Fault Handler 222
SLB — Performance Enhancement Tool 222
Managing SLB 222
Identifying Target Page Within Virtual Segment 223
Role of Page Table 223
Page Table Location and Length 223
Organization of Page Table 224
Creating Index Into Page Table 226
Adjusting Index Length To Match Page Table Size 226
Converting Index Into Offset Within Page Table 226
Primary Page Table Hash 226
Secondary Page Table Hash 228
Page Fault Handler s Job 228
Chapter 19: Block: Large Memory Region
Block Address Translation Overview 229
Block Address Translation (BAT) Process 232
BAT Registers 234
Block Address Translation 236
Determining If BAT Entry Valid 236
Determining If Effective Address Is Within Block 236
Access Rights 237
Effective-to-Physical Address Translation 238
Access Rules (WIMG) 238
Chapter 20: I/O and Memory-Mapped I/O
Introduction 239
I/O Mapped Ports 239
I/O Segment 239
I/O Bus Transaction 243
Memory-Mapped I/O Ports 243
Chapter 21: Interrupts
Location of Interrupt Table 245
Interrupt Handler Entry Points 246
Examples 246
Contents
T
Interrupts Cause a Context Switch 247
SRRO = CIA If Instruction-Caused Interrupt 247
SRRO = NIA If Not Instruction-Caused Interrupt 247
SRR1 Used for MSR State Save 247
Context Switch 248
The Stack and the State Save 249
Return from Interrupt (rfi) 250
Recoverable Interrupt Bit 250
General 250
On Entry to Interrupt Handler 250
On Exit from Interrupt Handler 251
On Entry to Machine Check or System Reset Handlers 251
Interrupts Originated by Instruction Execution 252
Data Storage Interrupt 252
Instruction Storage Interrupt 255
Alignment Interrupt 255
Program Interrupt 259
Floating-Point Unavailable Interrupt 261
System Call Interrupt 261
Trace Interrupt 261
Floating-Point Assist Interrupt 262
Interrupts from Source Other than Instruction 262
System Reset Interrupt 263
Machine Check Interrupt and Checkstop State 264
External Interrupt 264
Decrementer Interrupt 265
Precise Interrupts 266
Imprecise Interrupts 266
Partially-Executed Instructions 266
Ordered Interrupts — Caused by Instruction Fetch, Decode or
Execution 268
General 268
Integer Instruction Interrupt Ordering 269
Floating-Point Instruction Interrupt Ordering 269
Unordered Interrupts: External Source and Asynchronous To
Program Flow 270
xvn
PowerPC System Architecture
Interrupt Priorities 270
General 270
Instruction-Specific Interrupts 271
Chapter 22: The Timebase and the Decrementer
Time Base and Decrementer 273
General 273
Time Base 274
Decrementer 275
Chapter 23: Big vs Little-Endian
General 277
Intel Little-Endian vs PowerPC Big-Endian Storage 278
Explanation of Big and Little-Endian Addressing 279
PowerPC Little-Endian Storage Method 286
Load/Store of a Doubleword 286
Load/Store of a Word 289
Load/Store of a Halfword 289
Load/Store of a Byte 292
PowerPC Storage of Misaligned Operands 294
In Big-Endian Mode 294
In Little-Endian Mode 296
601 Alignment Interrupt and Little-Endian Mode 299
Switching Endian Modes 299
PowerPC Processors In General 299
601 Endian Mode Selection 299
Selection of Interrupt Handler Endian Mode 300
Problems Related to Endian Storage Mode 300
Passing Data to Bus Masters through Memory 301
Example — SCSI Host Bus Adapter (HBA) 301
Processor Operating In Big-Endian Storage Mode 302
Processor Operating In Little-Endian Storage Mode 305
Receiving Data from Bus Masters through Memory 305
Processor Operating In Big-Endian Storage Mode 305
Processor Operating In Little-Endian Storage Mode 305
Accessing Little-Endian Memory-Mapped I/O Ports 305
|
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| id | DE-604.BV010464813 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T17:52:58Z |
| institution | BVB |
| isbn | 0201409909 |
| language | English |
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| spelling | Shanley, Tom Verfasser aut PowerPC system architecture Tom Shanley 1. print. Reading, Mass. [u.a.] Addison-Wesley 1995 XLI, 609 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier PC system architecture series Computerarchitectuur gtt PowerPC gtt Computer architecture PowerPC microprocessors PowerPC (DE-588)4359646-0 gnd rswk-swf PowerPC (DE-588)4359646-0 s DE-604 HEBIS Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006973045&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Shanley, Tom PowerPC system architecture Computerarchitectuur gtt PowerPC gtt Computer architecture PowerPC microprocessors PowerPC (DE-588)4359646-0 gnd |
| subject_GND | (DE-588)4359646-0 |
| title | PowerPC system architecture |
| title_auth | PowerPC system architecture |
| title_exact_search | PowerPC system architecture |
| title_full | PowerPC system architecture Tom Shanley |
| title_fullStr | PowerPC system architecture Tom Shanley |
| title_full_unstemmed | PowerPC system architecture Tom Shanley |
| title_short | PowerPC system architecture |
| title_sort | powerpc system architecture |
| topic | Computerarchitectuur gtt PowerPC gtt Computer architecture PowerPC microprocessors PowerPC (DE-588)4359646-0 gnd |
| topic_facet | Computerarchitectuur PowerPC Computer architecture PowerPC microprocessors |
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