Digital timing macromodeling for VLSI design verification:
Saved in:
| Main Authors: | , |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Boston, Mass. [u.a.]
Kluwer
1995
|
| Series: | The Kluwer International Series in Engineering and Computer Science
319 : VLSI, Computer Architecture and Digital Signal Processing |
| Subjects: | |
| Physical Description: | XXI, 265 Seiten graph. Darst. |
| ISBN: | 0792395808 |
Staff View
MARC
| LEADER | 00000nam a2200000 cb4500 | ||
|---|---|---|---|
| 001 | BV010444149 | ||
| 003 | DE-604 | ||
| 005 | 20200504 | ||
| 007 | t | ||
| 008 | 951024s1995 d||| |||| 00||| eng d | ||
| 020 | |a 0792395808 |9 0-7923-9580-8 | ||
| 035 | |a (OCoLC)32348956 | ||
| 035 | |a (DE-599)BVBBV010444149 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-91G |a DE-188 | ||
| 050 | 0 | |a TK7874 | |
| 082 | 0 | |a 621.39/5/011 |2 20 | |
| 084 | |a ST 190 |0 (DE-625)143607: |2 rvk | ||
| 084 | |a ELT 272f |2 stub | ||
| 100 | 1 | |a Kong, Chŏng-t'aek |e Verfasser |0 (DE-588)1158284829 |4 aut | |
| 245 | 1 | 0 | |a Digital timing macromodeling for VLSI design verification |c by Jeong-Taek and David Overhauser |
| 264 | 1 | |a Boston, Mass. [u.a.] |b Kluwer |c 1995 | |
| 300 | |a XXI, 265 Seiten |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a The Kluwer International Series in Engineering and Computer Science |v 319 : VLSI, Computer Architecture and Digital Signal Processing | |
| 650 | 4 | |a Datenverarbeitung | |
| 650 | 4 | |a Integrated circuits |x Verification |x Data processing | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |v Computer-aided design | |
| 650 | 0 | 7 | |a Entwurf |0 (DE-588)4121208-3 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 0 | 1 | |a Entwurf |0 (DE-588)4121208-3 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Overhauser, David |e Verfasser |4 aut | |
| 830 | 0 | |a The Kluwer International Series in Engineering and Computer Science |v 319 : VLSI, Computer Architecture and Digital Signal Processing |w (DE-604)BV023545171 |9 319 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-006960836 | ||
Record in the Search Index
| _version_ | 1804124878415069184 |
|---|---|
| any_adam_object | |
| author | Kong, Chŏng-t'aek Overhauser, David |
| author_GND | (DE-588)1158284829 |
| author_facet | Kong, Chŏng-t'aek Overhauser, David |
| author_role | aut aut |
| author_sort | Kong, Chŏng-t'aek |
| author_variant | c t k ctk d o do |
| building | Verbundindex |
| bvnumber | BV010444149 |
| callnumber-first | T - Technology |
| callnumber-label | TK7874 |
| callnumber-raw | TK7874 |
| callnumber-search | TK7874 |
| callnumber-sort | TK 47874 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ST 190 |
| classification_tum | ELT 272f |
| ctrlnum | (OCoLC)32348956 (DE-599)BVBBV010444149 |
| dewey-full | 621.39/5/011 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5/011 |
| dewey-search | 621.39/5/011 |
| dewey-sort | 3621.39 15 211 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01717nam a2200433 cb4500</leader><controlfield tag="001">BV010444149</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20200504 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">951024s1995 d||| |||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0792395808</subfield><subfield code="9">0-7923-9580-8</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)32348956</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV010444149</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91G</subfield><subfield code="a">DE-188</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK7874</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.39/5/011</subfield><subfield code="2">20</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 190</subfield><subfield code="0">(DE-625)143607:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ELT 272f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Kong, Chŏng-t'aek</subfield><subfield code="e">Verfasser</subfield><subfield code="0">(DE-588)1158284829</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Digital timing macromodeling for VLSI design verification</subfield><subfield code="c">by Jeong-Taek and David Overhauser</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boston, Mass. [u.a.]</subfield><subfield code="b">Kluwer</subfield><subfield code="c">1995</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XXI, 265 Seiten</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">The Kluwer International Series in Engineering and Computer Science</subfield><subfield code="v">319 : VLSI, Computer Architecture and Digital Signal Processing</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Datenverarbeitung</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits</subfield><subfield code="x">Verification</subfield><subfield code="x">Data processing</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits</subfield><subfield code="x">Very large scale integration</subfield><subfield code="v">Computer-aided design</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Entwurf</subfield><subfield code="0">(DE-588)4121208-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Entwurf</subfield><subfield code="0">(DE-588)4121208-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Overhauser, David</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="830" ind1=" " ind2="0"><subfield code="a">The Kluwer International Series in Engineering and Computer Science</subfield><subfield code="v">319 : VLSI, Computer Architecture and Digital Signal Processing</subfield><subfield code="w">(DE-604)BV023545171</subfield><subfield code="9">319</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-006960836</subfield></datafield></record></collection> |
| id | DE-604.BV010444149 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T17:52:40Z |
| institution | BVB |
| isbn | 0792395808 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-006960836 |
| oclc_num | 32348956 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM DE-188 |
| owner_facet | DE-91G DE-BY-TUM DE-188 |
| physical | XXI, 265 Seiten graph. Darst. |
| publishDate | 1995 |
| publishDateSearch | 1995 |
| publishDateSort | 1995 |
| publisher | Kluwer |
| record_format | marc |
| series | The Kluwer International Series in Engineering and Computer Science |
| series2 | The Kluwer International Series in Engineering and Computer Science |
| spelling | Kong, Chŏng-t'aek Verfasser (DE-588)1158284829 aut Digital timing macromodeling for VLSI design verification by Jeong-Taek and David Overhauser Boston, Mass. [u.a.] Kluwer 1995 XXI, 265 Seiten graph. Darst. txt rdacontent n rdamedia nc rdacarrier The Kluwer International Series in Engineering and Computer Science 319 : VLSI, Computer Architecture and Digital Signal Processing Datenverarbeitung Integrated circuits Verification Data processing Integrated circuits Very large scale integration Computer-aided design Entwurf (DE-588)4121208-3 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf VLSI (DE-588)4117388-0 s Entwurf (DE-588)4121208-3 s DE-604 Overhauser, David Verfasser aut The Kluwer International Series in Engineering and Computer Science 319 : VLSI, Computer Architecture and Digital Signal Processing (DE-604)BV023545171 319 |
| spellingShingle | Kong, Chŏng-t'aek Overhauser, David Digital timing macromodeling for VLSI design verification The Kluwer International Series in Engineering and Computer Science Datenverarbeitung Integrated circuits Verification Data processing Integrated circuits Very large scale integration Computer-aided design Entwurf (DE-588)4121208-3 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4121208-3 (DE-588)4117388-0 |
| title | Digital timing macromodeling for VLSI design verification |
| title_auth | Digital timing macromodeling for VLSI design verification |
| title_exact_search | Digital timing macromodeling for VLSI design verification |
| title_full | Digital timing macromodeling for VLSI design verification by Jeong-Taek and David Overhauser |
| title_fullStr | Digital timing macromodeling for VLSI design verification by Jeong-Taek and David Overhauser |
| title_full_unstemmed | Digital timing macromodeling for VLSI design verification by Jeong-Taek and David Overhauser |
| title_short | Digital timing macromodeling for VLSI design verification |
| title_sort | digital timing macromodeling for vlsi design verification |
| topic | Datenverarbeitung Integrated circuits Verification Data processing Integrated circuits Very large scale integration Computer-aided design Entwurf (DE-588)4121208-3 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Datenverarbeitung Integrated circuits Verification Data processing Integrated circuits Very large scale integration Computer-aided design Entwurf VLSI |
| volume_link | (DE-604)BV023545171 |
| work_keys_str_mv | AT kongchongtaek digitaltimingmacromodelingforvlsidesignverification AT overhauserdavid digitaltimingmacromodelingforvlsidesignverification |