Asynchronous circuits:
Saved in:
| Main Authors: | , |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
New York u.a.
Springer
1995
|
| Series: | Monographs in computer science
|
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Item Description: | Literaturverz. S. 367 - 378 |
| Physical Description: | XVI, 404 S. graph. Darst. |
| ISBN: | 0387944206 |
Staff View
MARC
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| 100 | 1 | |a Brzozowski, Janusz A. |d 1935- |e Verfasser |0 (DE-588)114980187 |4 aut | |
| 245 | 1 | 0 | |a Asynchronous circuits |c Janusz A. Brzozowski ; Carl-Johan H. Seger |
| 264 | 1 | |a New York u.a. |b Springer |c 1995 | |
| 300 | |a XVI, 404 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 0 | |a Monographs in computer science | |
| 500 | |a Literaturverz. S. 367 - 378 | ||
| 650 | 4 | |a Circuits asynchrones | |
| 650 | 4 | |a Asynchronous circuits | |
| 650 | 0 | 7 | |a Asynchrones Schaltwerk |0 (DE-588)4271581-7 |2 gnd |9 rswk-swf |
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| 700 | 1 | |a Seger, Carl-Johan H. |e Verfasser |0 (DE-588)114980209 |4 aut | |
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Record in the Search Index
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|---|---|
| adam_text |
CONTENTS
FOREWORD
VII
PREFACE
IX
1
INTRODUCTORY
EXAMPLES
1
1.1
LOGIC
GATES
.
2
1.2
PERFORMANCE
ESTIMATION
.
3
1.3
RS
FLIP-FLOP
.
8
1.4
DYNAMIC
CMOS
LOGIC
.
10
1.5
DIVIDE-BY-2
COUNTER
.
16
1.6
SUMMARY
.
21
2
MATHEMATICAL
BACKGROUND
23
2.1
SETS
AND
RELATIONS
.
23
2.2
BOOLEAN
ALGEBRA
.
25
2.3
TERNARY
ALGEBRA
.
28
2.4
DIRECTED
GRAPHS
.
32
3
DELAY
MODELS
35
3.1
ENVIRONMENT
MODES
.
35
3.2
GATES
WITH
DELAYS
.
36
3.3
IDEAL
DELAYS
.
38
3.4
INERTIAL
DELAYS
.
40
4
GATE
CIRCUITS
45
4.1
PROPERTIES
OF
GATES
.
45
4.2
CLASSES
OF
GATE
CIRCUITS
.
47
4.3
THE
CIRCUIT
GRAPH
.
50
4.4
NETWORK
MODELS
.
53
4.5
MODELS
OF
MORE
COMPLEX
GATES
.
57
5
CMOS
TRANSISTOR
CIRCUITS
61
5.1
CMOS
CELLS
.
61
5.2
COMBINATIONAL
CMOS
CIRCUITS
.
67
5.3
GENERAL
CMOS
CIRCUITS
.
69
5.4
NODE
EXCITATION
FUNCTIONS
.
71
5.5
PATH
STRENGTH
MODELS
.
73
5.6
CAPACITANCE
EFFECTS
.
75
5.7
NETWORK
MODEL
OF
CMOS
CIRCUITS
.
79
XIV
CONTENTS
6
UP-BOUNDED-DELAY
RACE
MODELS
83
6.1
THE
GENERAL
MULTIPLE-WINNER
MODEL
.
84
6.2
GMW
ANALYSIS
AND
UIN
DELAYS
.
92
6.3
THE
OUTCOME
IN
GMW
ANALYSIS
.
95
6.4
STABLE
STATES
AND
FEEDBACK-STATE
NETWORKS
.
97
6.5
GMW
ANALYSIS
AND
NETWORK
MODELS
.
99
6.6
THE
EXTENDED
GMW
MODEL
.
101
6.7
SINGLE-WINNER
RACE
MODELS
.
102
6.8
UP-BOUNDED
IDEAL
DELAYS
.
103
6.9
PROOFS
.
107
6.9.1
PROOFS
FOR
SECTION
6.2
.
107
6.9.2
PROOFS
FOR
SECTION
6.3
.
110
7
TERNARY
SIMULATION
113
7.1
INTRODUCTORY
EXAMPLES
.
113
7.2
ALGORITHM
A
.
118
7.3
ALGORITHM
B
.
121
7.4
FEEDBACK-DELAY
MODELS
.
123
7.5
HAZARDS
.
127
7.5.1
STATIC
HAZARDS
.
127
7.5.2
DYNAMIC
HAZARDS
.
129
7.6
TERNARY
SIMULATION
AND
THE
GSW
MODEL
.
129
7.7
TERNARY
SIMULATION
AND
THE
XMW
MODEL
.
131
7.8
PROOFS
OF
MAIN
RESULTS
.
132
8
BI-BOUNDED
DELAY
MODELS
143
8.1
DISCRETE
BINARY
MODELS
.
144
8.2
CONTINUOUS
BINARY
MODEL
.
148
8.3
ALGORITHMS
FOR
CONTINUOUS
BINARY
ANALYSIS
.
152
8.4
CONTINUOUS
TERNARY
MODEL
.
156
8.5
DISCRETE
TERNARY
MODEL
.
162
9
COMPLEXITY
OF
RACE
ANALYSIS
167
9.1
STABLE-STATE
REACHABILITY
.
167
9.2
LIMITED
REACHABILITY
.
181
10
REGULAR
LANGUAGES
AND
FINITE
AUTOMATA
187
10.1
REGULAR
LANGUAGES
.
187
10.1.1
SEMIGROUPS
.
187
10.1.2
LANGUAGES
.
188
10.1.3
REGULAR
LANGUAGES
.
189
10.1.4
QUOTIENTS
OF
LANGUAGES
.
190
10.2
REGULAR
EXPRESSIONS
.
192
10.2.1
EXTENDED
REGULAR
EXPRESSIONS
.
192
10.2.2
QUOTIENTS
OF
REGULAR
EXPRESSIONS
.
193
CONTENTS
XV
10.3
QUOTIENT
EQUATIONS
.
198
10.4
FINITE
AUTOMATA
.
202
10.4.1
BASIC
CONCEPTS
.
202
10.4.2
RECOGNIZABLE
LANGUAGES
.
204
10.5
EQUIVALENCE
AND
REDUCTION
OF
AUTOMATA
.
205
10.6
NONDETERMINISTIC
AUTOMATA
.
207
10.7
EXPRESSION
AUTOMATA
.
209
11
BEHAVIORS
AND
REALIZATIONS
213
11.1
MOTIVATION
.
214
11.2
BEHAVIORS
.
215
11.3
PROJECTIONS
OF
IMPLEMENTATIONS
TO
SPECIFICATIONS
.
220
11.4
RELEVANT
WORDS
.
223
11.4.1
SAME
INPUT
AND
OUTPUT
ALPHABETS
.
223
11.4.2
DIFFERENT
INPUT
AND
OUTPUT
ALPHABETS
.
224
11.5
PROPER
BEHAVIORS
.
225
11.6
REALIZATION
.
229
11.6.1
SAFETY
AND
CAPABILITY
.
229
11.6.2
DEADLOCK
.
230
11.6.3
LIVELOCK
.
232
11.6.4
DEFINITION
OF
REALIZATION
.
234
11.7
BEHAVIOR
SCHEMAS
.
235
11.8
CONCLUDING
REMARKS
.
240
12
TYPES
OF
BEHAVIORS
241
12.1
INTRODUCTORY
EXAMPLES
.
241
12.2
FUNDAMENTAL-MODE
SPECIFICATIONS
.
244
12.3
FUNDAMENTAL-MODE
NETWORK
BEHAVIORS
.
246
12.4
DIRECT
BEHAVIORS
.
249
12.5
SERIAL
BEHAVIORS
.
251
13
LIMITATIONS
OF
UP-BOUNDED
DELAY
MODELS
255
13.1
DELAY-INSENSITIVITY
IN
FUNDAMENTAL
MODE
.
256
13.2
COMPOSITE
FUNCTIONS
.
258
13.3
MAIN
THEOREM
FOR
FUNDAMENTAL
MODE
.
259
13.4
DELAY-INSENSITIVITY
IN
INPUT/OUTPUT
MODE
.
263
13.4.1
THE
MAIN
LEMMA
.
263
13.4.2
SOME
BEHAVIORS
WITHOUT
DI
REALIZATIONS
.
269
13.4.3
NONTRIVIAL
SEQUENTIAL
BEHAVIORS
.
270
13.5
CONCLUDING
REMARKS
.
272
14
SYMBOLIC
ANALYSIS
275
14.1
REPRESENTING
BOOLEAN
FUNCTIONS
.
276
14.2
SYMBOLIC
REPRESENTATIONS
.
279
14.2.1
FINITE
DOMAINS
.
279
XVI
CONTENTS
14.2.2
SETS
.
280
14.2.3
RELATIONS
.
281
14.2.4
BEHAVIORS
.
283
14.3
DERIVING
SYMBOLIC
BEHAVIORS
.
284
14.4
SYMBOLIC
RACE
ANALYSIS
.
288
14.4.1
SYMBOLIC
TERNARY
SIMULATION
.
289
14.4.2
SYMBOLIC
BOUNDED-DELAY
ANALYSIS
.
290
14.5
SYMBOLIC
VERIFICATION
OF
REALIZATION
.
297
14.6
SYMBOLIC
MODEL
CHECKING
.
303
15
DESIGN
OF
ASYNCHRONOUS
CIRCUITS
313
15.1
INTRODUCTION
.
315
15.2
FUNDAMENTAL-MODE
HUFFMAN
CIRCUITS
.
318
15.3
HOLLAAR
CIRCUITS
.
320
15.4
BURST-MODE
CIRCUITS
.
321
15.5
MODULE
SYNTHESIS
USING
I-NETS
.
325
15.6
SIGNAL
TRANSITION
GRAPHS
.
331
15.7
CHANGE
DIAGRAMS
.
339
15.8
PROTOCOLS
IN
DI
CIRCUITS
.
341
15.9
EBERGEN
'
S
TRACE
THEORY
METHOD
.
343
15.10
COMPILATION
OF
COMMUNICATING
PROCESSES
.
348
15.11
HANDSHAKE
CIRCUITS
.
357
15.12
MODULE-BASED
COMPILATION
SYSTEMS
.
360
15.13
DCVSL
AND
INTERCONNECTION
MODULES
.
361
15.14
MICROPIPELINES
.
363
15.15
CONCLUDING
REMARKS
.
366
BIBLIOGRAPHY
367
LIST
OF
FIGURES
379
LIST
OF
TABLES
385
LIST
OF
MATHEMATICAL
CONCEPTS
387
INDEX
391 |
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| author | Brzozowski, Janusz A. 1935- Seger, Carl-Johan H. |
| author_GND | (DE-588)114980187 (DE-588)114980209 |
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| dewey-ones | 621 - Applied physics |
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| id | DE-604.BV010201235 |
| illustrated | Illustrated |
| indexdate | 2024-08-18T00:16:03Z |
| institution | BVB |
| isbn | 0387944206 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-006779266 |
| oclc_num | 31514494 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM DE-384 DE-29T DE-473 DE-BY-UBG DE-634 DE-83 |
| owner_facet | DE-91 DE-BY-TUM DE-384 DE-29T DE-473 DE-BY-UBG DE-634 DE-83 |
| physical | XVI, 404 S. graph. Darst. |
| publishDate | 1995 |
| publishDateSearch | 1995 |
| publishDateSort | 1995 |
| publisher | Springer |
| record_format | marc |
| series2 | Monographs in computer science |
| spelling | Brzozowski, Janusz A. 1935- Verfasser (DE-588)114980187 aut Asynchronous circuits Janusz A. Brzozowski ; Carl-Johan H. Seger New York u.a. Springer 1995 XVI, 404 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Monographs in computer science Literaturverz. S. 367 - 378 Circuits asynchrones Asynchronous circuits Asynchrones Schaltwerk (DE-588)4271581-7 gnd rswk-swf Digitalschaltung (DE-588)4012295-5 gnd rswk-swf Digitalschaltung (DE-588)4012295-5 s Asynchrones Schaltwerk (DE-588)4271581-7 s DE-604 Seger, Carl-Johan H. Verfasser (DE-588)114980209 aut DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006779266&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Brzozowski, Janusz A. 1935- Seger, Carl-Johan H. Asynchronous circuits Circuits asynchrones Asynchronous circuits Asynchrones Schaltwerk (DE-588)4271581-7 gnd Digitalschaltung (DE-588)4012295-5 gnd |
| subject_GND | (DE-588)4271581-7 (DE-588)4012295-5 |
| title | Asynchronous circuits |
| title_auth | Asynchronous circuits |
| title_exact_search | Asynchronous circuits |
| title_full | Asynchronous circuits Janusz A. Brzozowski ; Carl-Johan H. Seger |
| title_fullStr | Asynchronous circuits Janusz A. Brzozowski ; Carl-Johan H. Seger |
| title_full_unstemmed | Asynchronous circuits Janusz A. Brzozowski ; Carl-Johan H. Seger |
| title_short | Asynchronous circuits |
| title_sort | asynchronous circuits |
| topic | Circuits asynchrones Asynchronous circuits Asynchrones Schaltwerk (DE-588)4271581-7 gnd Digitalschaltung (DE-588)4012295-5 gnd |
| topic_facet | Circuits asynchrones Asynchronous circuits Asynchrones Schaltwerk Digitalschaltung |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006779266&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT brzozowskijanusza asynchronouscircuits AT segercarljohanh asynchronouscircuits |