Parallel architectures and compilation techniques: proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques, PACT '94, Montréal, Cananda, 24 - 26 August, 1994
Saved in:
| Format: | Conference Proceeding Book |
|---|---|
| Language: | English |
| Published: |
Amsterdam u.a.
North-Holland
1994
|
| Series: | International Federation for Information Processing: [IFIP transactions / A]
50 |
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Physical Description: | XII, 362 S. Ill., graph. Darst. |
| ISBN: | 0444819266 |
Staff View
MARC
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| 245 | 1 | 0 | |a Parallel architectures and compilation techniques |b proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques, PACT '94, Montréal, Cananda, 24 - 26 August, 1994 |c ed. by Michel Cosnard ... |
| 264 | 1 | |a Amsterdam u.a. |b North-Holland |c 1994 | |
| 300 | |a XII, 362 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a International Federation for Information Processing: [IFIP transactions / A] |v 50 | |
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| 650 | 7 | |a compilation architecture |2 inriac | |
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Record in the Search Index
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| adam_text |
TABLE
OF
CONTENTS
Preface
v
Programme Committee
vii
List Of Referees
viii
Part I
-
High-Performance Architectures
EM
-С:
Programming with Explicit Parallelism and Locality for EM-4 Multiprocessor
Mitsuhisa Sato, Yuetsu Kodama, Shuichi Sakai and Yoshinori Yamaguchi
3
A Fine-Grain Threaded Abstract Machine
Jesper Vaseli
15
Tradeoffs in the Design of Single Chip Multiprocessors
David H. Albonesi and Israel
Koren
25
Part II
-
Code Generation for Multithreaded and Dataflow
Architectures
An Evaluation of Optimized Threaded Code Generation
Lucas
Roh,
Walid A. Najjar, Bhanu Shankar, and A.P.
Wim Böhm 37
Functional /-structure, and M-structure Implementations of
NAS
Benchmark FT
S. Sur
and W.
Böhm 47
The Plan-Do Style Compilation Technique for Eager Data Transfer in Thread-Based
Execution
M. Yasugi, S. Matsuoka, and A. Yonezawa
57
Part III
-
Memory and Cache Issues
A Compiler-Assisted Scheme for Adaptive Cache Coherence Enforcement
Trung
N.
Nguyen, Farnaz Mounes-Toussi, David J.
Lilja,
and Zhiyuan Li
69
The Impact of Cache Coherence Protocols on Systems using Fine-Grain Data
Synchronization
David B.
Glaseo,
Bruce A.Delagi, and Michael J. Flynn
79
Towards a Programming Environment for a Computer with Intelligent Memory
Abhaya Asthana, Mark
Cravatte,
and Paul Krzyzanowski
89
Part IV
-
Distributed Memory Machines
Communication Analysis for Multicomputer Compilers
Inkyu Kim and Michael Wolfe
101
Automatic
Data Layout Using
0-1
Integer Programming
Robert Bixby, Ken Kennedy, and
Ulrich
Кгеюег
111
Processor Tagged Descriptors: A Data Structure for Compiling for Distributed-Memory
Multicomputers
Ernesto
Su,
Daniel J. Palermo, and Prithviraj Banerjee
123
Part V
-
Multi-Level Parallelism
Resource Speckling: A Framework for Integrating Register Allocation in Local and Glo¬
bal Schedulers
David A. Berson, Rajiv Gupta, and Mary
Lou Soffa
135
An Approach to Combine Predicated/Speculative Execution for Programs with Unpre¬
dictable Branches
Mantipragada Srinivas, Alexandra
Nicolau,
and Vicki H. Allan
147
A PDG-based Tool and its Use in Analyzing Program Control Dependences
Chris J. Newburn, Derek B. Noonburg, and John P. Shen
157
Part VI
-
Compiling for Parallel Machines
Static Analysis of Barrier Synchronization in Explicitly Parallel Programs
Tor
Б.
Jeremiassen and Susan J. Eggers
171
Exploiting the Parallelism Exposed by Partial Evaluation
R. Surati and A. A. Berlin
181
Effects of Loop Fusion and Statement Migration on the Speedup of Vector
Multiprocessors
Mayez Al-Mouhamed and
Lubomir
Bic
193
Part
VII
-
Logic Languages
Practical Static Mode Analyses of Concurrent Logic Languages
E. Tick
205
Demand-Driven Dataflow for Concurrent Committed-Choice Code
Bart Massey and Evan Tick
215
Exploitation of Fine-grain Parallelism in Logic Languages on Massively Parallel
Architectures
Hiecheol Kim and Jean-Luc Gaudiot
225
Part
VIII -
Application
Specific Architectures
From SIGNAL to fine-grain parallel implementations
Olivier Maffeis and Paul
Le Guernic
237
Microcode Generation for Flexible Parallel Target Architectures
Rainer
Leupers, Wolfgang
Schenk,
and Peter Marwedel
247
A Fleng Compiler for
PIE6Ą
Hidemoto Nakada, Takuya
Araki,
Hanpei Koike, and Hidehiko Tanaka
257
Part IX
-
Functional Languages, Dataflow Models and
Implementation
Compiling Higher-Order Functions for Tagged-Dataflow
P. Rondogiannis and W.W. Wadge
269
Dataflow-Based Lenient Implementation of a Functional Language, Valid, on Conven¬
tional Multi-processors
Shigeru Kusakabe, Eiichi Takahashi, Rin-ichiro Taniguchi, and Makoto Amamiya
279
Dataflow and Logicflow Models for Defining a Parallel Prolog Abstract Machine
P.
Kacsuk
289
Towards a Computational Model for UFO
John Sargeant, Chris Kirkham, and Steve Anderson
299
Part X
-
Short Papers
Software pipelining: A Genetic Algorithm Approach
V.H. Allan and M.R. O'Neill
311
Parallel Compilation on Associative Computers
Chandra R. Asthagiri and Jerry L. Potter
315
Partitioning of Variables for Multiple-Register-File Architectures via Hypergraph
Coloring
A. Capitanio,
N. Dutt
and
Α.
Nicolau 319
Realizing Parallel Reduction Operations in Sisal
1.2
Scott M.
Dentón,
John T.
Feo
and Patrick J. Miller
323
An Introduction to Simplex Scheduling
Benoît Dupont de Dinechin
327
Speculative Evaluation for Parallel Graph Reduction
James S.
Mattson
Jr. and William G. Griswoldd
331
Toward a General-Purpose Multi-Stream System
Avi Mendelson
and
Bilha Mendelson
335
Representing Control Flow Behaviour of Programs
Cyril Meurillon and
Ciaran O'Donnell
339
Transformations on Doubly Nested Loops
Ron Sass and Matt Mutka
343
A Comparative Study of Data-Flow Architectures
David
F. Snelling
and Gregory K. Egan
347
Progress Report on Porting Sisal to the
EM-Ą
Multiprocessor
Andrew
Sohn, Lingmian
Kong and Mistuhisa Sato
351
Static vs. Dynamic Strategies for Fine-Grain Dataflow Synchronization
Jonas Vasell
355
Trace Software Pipelining: A Novel Technique for Parallelization of Loops with
Branches
Jian
Wang, Andreas
Krall,
M.
Anton
Erti
and Christine Eisenbeis
359 |
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| discipline | Informatik |
| format | Conference Proceeding Book |
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| genre_facet | Konferenzschrift 1994 Montréal |
| id | DE-604.BV010111548 |
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| spelling | Parallel architectures and compilation techniques proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques, PACT '94, Montréal, Cananda, 24 - 26 August, 1994 ed. by Michel Cosnard ... Amsterdam u.a. North-Holland 1994 XII, 362 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier International Federation for Information Processing: [IFIP transactions / A] 50 Compilation (informatique) - Congrès ram Parallélisme (informatique) - Congrès ram antémémoire inriac architecture flot donnée inriac architecture parallèle inriac compilation architecture inriac génération code inriac langage fonctionnel inriac langage logique inriac machine parallèle inriac parallélisme inriac Computer architecture Congresses Parallel computers Congresses Compiler (DE-588)4148248-7 gnd rswk-swf Parallelrechner (DE-588)4173280-7 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1994 Montréal gnd-content Parallelrechner (DE-588)4173280-7 s Compiler (DE-588)4148248-7 s DE-604 Cosnard, Michel Sonstige oth Working Conference on Parallel Architectures and Compilation Techniques 1994 Montréal Sonstige (DE-588)5112624-2 oth A] International Federation for Information Processing: [IFIP transactions 50 (DE-604)BV006188900 50 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006713786&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Parallel architectures and compilation techniques proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques, PACT '94, Montréal, Cananda, 24 - 26 August, 1994 Compilation (informatique) - Congrès ram Parallélisme (informatique) - Congrès ram antémémoire inriac architecture flot donnée inriac architecture parallèle inriac compilation architecture inriac génération code inriac langage fonctionnel inriac langage logique inriac machine parallèle inriac parallélisme inriac Computer architecture Congresses Parallel computers Congresses Compiler (DE-588)4148248-7 gnd Parallelrechner (DE-588)4173280-7 gnd |
| subject_GND | (DE-588)4148248-7 (DE-588)4173280-7 (DE-588)1071861417 |
| title | Parallel architectures and compilation techniques proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques, PACT '94, Montréal, Cananda, 24 - 26 August, 1994 |
| title_auth | Parallel architectures and compilation techniques proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques, PACT '94, Montréal, Cananda, 24 - 26 August, 1994 |
| title_exact_search | Parallel architectures and compilation techniques proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques, PACT '94, Montréal, Cananda, 24 - 26 August, 1994 |
| title_full | Parallel architectures and compilation techniques proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques, PACT '94, Montréal, Cananda, 24 - 26 August, 1994 ed. by Michel Cosnard ... |
| title_fullStr | Parallel architectures and compilation techniques proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques, PACT '94, Montréal, Cananda, 24 - 26 August, 1994 ed. by Michel Cosnard ... |
| title_full_unstemmed | Parallel architectures and compilation techniques proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques, PACT '94, Montréal, Cananda, 24 - 26 August, 1994 ed. by Michel Cosnard ... |
| title_short | Parallel architectures and compilation techniques |
| title_sort | parallel architectures and compilation techniques proceedings of the ifip wg10 3 working conference on parallel architectures and compilation techniques pact 94 montreal cananda 24 26 august 1994 |
| title_sub | proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques, PACT '94, Montréal, Cananda, 24 - 26 August, 1994 |
| topic | Compilation (informatique) - Congrès ram Parallélisme (informatique) - Congrès ram antémémoire inriac architecture flot donnée inriac architecture parallèle inriac compilation architecture inriac génération code inriac langage fonctionnel inriac langage logique inriac machine parallèle inriac parallélisme inriac Computer architecture Congresses Parallel computers Congresses Compiler (DE-588)4148248-7 gnd Parallelrechner (DE-588)4173280-7 gnd |
| topic_facet | Compilation (informatique) - Congrès Parallélisme (informatique) - Congrès antémémoire architecture flot donnée architecture parallèle compilation architecture génération code langage fonctionnel langage logique machine parallèle parallélisme Computer architecture Congresses Parallel computers Congresses Compiler Parallelrechner Konferenzschrift 1994 Montréal |
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| volume_link | (DE-604)BV006188900 |
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